Updated on 2022/08/26

 
UENOHARA Seiji
 
Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 3

Citation count denotes the number of citations in papers published for a particular year.

Affiliation
Graduate School of Life Science and Systems Engineering Department of Human Intelligence Systems
Job
Specially Appointed Assistant Professor

Degree

  • Kyushu Institute of Technology  -  Doctor of Engineering   2016.03

Biography in Kyutech

  • 2020.08
     

    Kyushu Institute of Technology   Graduate School of Life Science and Systems Engineering   Department of Human Intelligence Systems   Specially Appointed Assistant Professor  

Papers

  • A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor with 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain Reviewed

    Uenohara S., Aihara K.

    IEEE Access   10   48338 - 48348   2022.01

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    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/ACCESS.2022.3170579

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    Other Link: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85129645576&origin=inward

  • CMOS mixed-signal spiking neural network circuit using a time-domain digital-to-analog converter Reviewed

    Uenohara S., Aihara K.

    Proceedings - IEEE International Symposium on Circuits and Systems   2021-May   2021.01

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    This paper proposes a high energy efficiency CMOS mixed-signal spiking neural network circuit using a time-domain digital-to-analog converter (TDAC) for realizing online and on-chip brainmorphic learning hardware. The circuit consists of a mixed-signal synapse circuit and an analog leaky integrate-and-fire neuron circuit. The TDAC converts synaptic weights held by digital memory into an analog current that realizes a biologically plausible synaptic response, which is employed as an output stage for our synapse circuit. To evaluate online and on-chip learning operation, the remote supervised method (ReSuMe) was implemented using TSMC 40-nm (1-poly, 8-metal) CMOS technology, and this circuit was evaluated by a Spectre circuit simulator. The circuit simulation results show that energy per synaptic event in our circuit was 20.1 fJ for multiply-accumulation operation and 92.1 fJ for ReSuMe.

    DOI: 10.1109/ISCAS51556.2021.9401230

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    Other Link: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85109050626&origin=inward

  • Reconstructing bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems Reviewed International journal

    Yoshitaka Itoh, Seiji Uenohara, Masaharu Adachi, Takashi Morie, Kazuyuki Aihara

    ( American Institute of Physics ) 30   013128-1 - 013128-11   2020.01

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    Language:English   Publishing type:Research paper (scientific journal)

    Bifurcation-diagram reconstruction estimates various attractors of a system without observing all of them but only from observing several attractors with different parameter values. Therefore, the bifurcation-diagram reconstruction can be used to investigate how attractors change with the parameter values, especially for real-world engineering and physical systems for which only a limited number of attractors can be observed. Although bifurcation diagrams of various systems have been reconstructed from time-series data generated in numerical experiments, the systems that have been targeted for reconstructing bifurcation diagrams from time series measured from physical phenomena so far have only been continuous-time dynamical systems. In this paper, we reconstruct bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems with different parameter values. The generated time-series datasets are perturbed by dynamical noise and contaminated by observational noise. To reconstruct the bifurcation diagrams only from the time-series datasets, we use an extreme learning machine as a time-series predictor because it has a good generalization property. Hereby, we expect that the bifurcation-diagram reconstruction with the extreme learning machine is robust against dynamical noise and observational noise. For quantitatively verifying the robustness, the Lyapunov exponents of the reconstructed bifurcation diagrams are compared with those of the bifurcation diagrams generated in numerical experiments and by the electronic circuits.

    Other Link: https://aip.scitation.org/doi/abs/10.1063/1.5119187

  • Time-Domain Digital-to-Analog Converter for Spiking Neural Network Hardware Reviewed

    Uenohara Seiji, Aihara Kazuyuki

    Circuits, Systems, and Signal Processing   2020.01

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    Authorship:Lead author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1007/s00034-020-01597-2

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  • Real-time implementation of ReSuMe learning in spiking neural network Reviewed

    Xia Yang, Seiji Uenohara, Kazuyuki Aihara, Takashi Kohno, Timothee Levi

    International Conference on Artificial Life and Robotics   45   2019.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

  • Noise-driven stochastic bistable circuits for brain-morphic systems Reviewed

    Yusuke Sakemi, Seiji Uenohara, Kazuyuki Aihara, Takashi Kohno,

    International Symposium on Nonlinear Theory and its Applications ( Institute of Electronics, Information and Communication Engineers )   666 - 669   2018.09

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    Language:English   Publishing type:Research paper (international conference proceedings)

  • A pulse-width-modulation mode CMOS integrated circuit implementation of threshold-coupled map Reviewed

    Uenohara Seiji, Morie Takashi, Tamukoh Hakaru, Aihara Kazuyuki

    Nonlinear Theory and Its Applications, IEICE   9 ( 2 )   268 - 280   2018.01

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    Authorship:Lead author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1587/nolta.9.268

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/130006602774

  • Hardware-oriented Algorithm for Chaotic Boltzmann Machines Reviewed

    Ichiro Kawashima, Seiji Uenohara, Takashi Kato, Masatoshi Yamaguchi, Hideyuki Suzuki, Takashi Morie, Hakaru Tamukoh

    International Workshop on Smart Info-Media Systems in Asia   2016.09

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    Language:English   Publishing type:Research paper (international conference proceedings)

  • A-2-15 A CMOS Circuit Implementation of Chaotic Boltzmann Machines

    Kato Takashi, Uenohara Seiji, Suzuki Hideyuki, Tamukoh Hakaru, Morie Takashi

    Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference ( The Institute of Electronics, Information and Communication Engineers )   2015   2015.08

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    Language:Japanese   Publishing type:Research paper (conference, symposium, etc.)

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/110009996023

  • A-2-16 Evaluation of a Device-mismatch Compensation Circuit for Large-Scale Coupled Nonlinear Dynamical Systems

    Uenohara Seiji, Morie Takashi, Tamukoh Hakaru, Aihara Kazuyuki

    Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference ( The Institute of Electronics, Information and Communication Engineers )   2015   2015.08

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    Authorship:Lead author   Language:Japanese   Publishing type:Research paper (conference, symposium, etc.)

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/110009996024

  • A CMOS circuit for PWM-mode nonlinear transformation robust to device mismatches to implement coupled map lattice models Reviewed

    Seiji Uenohara, Atuti Daisuke, Matsuzaka Kenji, Tamukoh Hakaru, Morie Takashi, Aihara Kazuyuki

    Nonlinear theory and its applications ( Institute of Electronics, Information and Communication Engineers )   6 ( 4 )   570 - 581   2015.04

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    In order to develop large-scale nonlinear dynamical systems using CMOS integrated circuits, we propose a core circuit for coupled map lattice (CML) models. The characteristics of the core circuits in the lattice on a chip are not generally equal, which is caused by CMOS device mismatches, including parasitic capacitance and wiring resistance. The proposed circuit solves this problem; it compensates for a DC offset voltage variation by holding it at a capacitor, and also for current variation by adjusting the bias voltage of a current source automatically so as to bring the current close to a target value. The proposed core circuit has been designed and fabricated using TSMC 0.25 µm CMOS technology. The measurement results using the fabricated circuit have shown that the bit precision is more than 8 bits, even if there is a DC offset voltage of 100 mV or a bias-voltage change of 100 mV in a switched current source.

    Other Link: https://ci.nii.ac.jp/naid/130005102329

  • A chaotic spiking oscillator circuit that acts as a filter of spike trains

    YAMAGUCHI Masatoshi, UENOHARA Seiji, MORIE Takashi

    IEICE technical report. Nonlinear problems ( The Institute of Electronics, Information and Communication Engineers )   114 ( 414 )   77 - 82   2015.01

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    Language:Japanese   Publishing type:Research paper (conference, symposium, etc.)

    We propose a CMOS circuit that implements a chaotic spiking oscillator model, which acts as a filter of spike trains. This model is a phase oscillator that outputs a spike pulse at the timing with a predefined phase value, and transforms its phase value with a nonlinear transformation function at the timing of spike inputs. This model uses the input-spike interval as a bifurcation parameter, and outputs various spike-train patterns including non-output states. The proposed circuit for this model expresses the phase state value by charges stored at a capacitor charged up with a constant current source. We have designed and fabricated the proposed circuit using a standard CMOS integrated circuit technology, and have evaluated the fabricated circuit as a spike-train filter. We show the measurement results for verifying the circuit operation.

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/110010002094

  • A CMOS circuit for PWM-mode nonlinear transformation robust to device mismatches to implement coupled map lattice models Reviewed

    Uenohara Seiji, Atuti Daisuke, Matsuzaka Kenji, Tamukoh Hakaru, Morie Takashi, Aihara Kazuyuki

    Nonlinear Theory and Its Applications, IEICE   6 ( 4 )   570 - 581   2015.01

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    Authorship:Lead author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1587/nolta.6.570

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/130005102329

  • Experimental distinction between chaotic and strange nonchaotic attractors on the basis of consistency Reviewed International journal

    Seiji Uenohara, Takahito Mitsui, Yoshito Hirata, Takashi Morie, Yohihiko Horio, Kazuyuki Aihara

    Chaos ( American Institute of Physics )   23   023110-9 - 023110-9   2013.05

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    e experimentally study strange nonchaotic attractors (SNAs) and chaotic attractors by using a nonlinear integrated circuit driven by a quasiperiodic input signal. An SNA is a geometrically strange attractor for which typical orbits have nonpositive Lyapunov exponents. It is a difficult problem to distinguish between SNAs and chaotic attractors experimentally. If a system has an SNA as a unique attractor, the system produces an identical response to a repeated quasiperiodic signal, regardless of the initial conditions, after a certain transient time. Such reproducibility of response outputs is called consistency. On the other hand, if the attractor is chaotic, the consistency is low owing to the sensitive dependence on initial conditions. In this paper, we analyze the experimental data for distinguishing between SNAs and chaotic attractors on the basis of the consistency.
    Strange nonchaotic attractors (SNAs) often appear in dynamical systems driven by a quasiperiodic signal. An SNA is a geometrically strange attractor for which typical orbits have nonpositive Lyapunov exponents. In fact, typical orbits are insensitive to initial conditions under a common quasiperiodic signal. Owing to their characteristics reminiscent of both quasiperiodic order and chaos, SNAs have attracted the attention of researchers from both theoretical and experimental perspectives. Conventionally, the information dimension is often employed to distinguish between SNAs and chaotic attractors in experiments. However, using the information dimension for the experimental distinction between these types of attractors is difficult as the estimation of the information dimension is highly sensitive to noise, and requires rather long time series. Recently, Ngamga et al.1 proposed a method for distinguishing between SNAs and chaotic attractors, which utilizes the consistency property of SNAs. Consistency here means that a nonlinear system shows the same response to the same input signal after some transient time, regardless of the initial conditions. In the method proposed by Ngamga et al., the determinism for a cross-recurrence plot of two response time series to the same input signal is used as a consistency measure. However, to our knowledge, there is no research paper on using their cross-recurrence method to experimentally distinguish between SNAs and chaotic attractors. In this study, we evaluated the consistency of a system by using the zero-delay normalized cross-correlation and Ngamga et al.'s cross-recurrence methods. By combining spectrum analysis and evaluation of consistency, we showed that SNAs and chaotic attractors can be distinguished more precisely as compared to conventional methods.

    DOI: 10.1063/1.4804181

    Other Link: https://aip.scitation.org/doi/10.1063/1.4804181

  • Design of a Threshold-coupled CMOS Chaos Circuit Using Voltage/Current Waveform Sampling Reviewed

    UENOHARA Seiji, ATUTI Daisuke, MATSUZAKA Kenji, MORIE Takashi, AIHARA Kazuyuki

    IEICE technical report. Neurocomputing ( The Institute of Electronics, Information and Communication Engineers )   112 ( 390 )   105 - 110   2013.01

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    In order to develop large-scale coupled nonlinear dynamical systems using CMOS integrated circuits, we propose a threshold-coupled map array circuit that is robust to CMOS device mismatch. We have already proposed a voltage- and a current-sampling mode circuits which can achieve arbitrary analog nonlinear dynamics in the time domain by using pulse width/phase modulation (PWM/PPM) signals. Both circuits have advantages of robustness to parameter mismatches of CMOS circuit elements and facilitation of weighted summation of connected states, respectively. These advantages are important for developing a large-scale coupled array circuit. In this study, we employ a circuit architecture having the advantages of these sampling mode, and propose a circuit that is robust to voltage-shift dispersion of CMOS analog buffers. We show this robustness of the proposed circuit by SPICE circuit simulation.

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/110009728129

  • Torus-doubling process via strange nonchaotic attractors Reviewed

    Takahito Mitsui, Seiji Uenohara, Takashi Morie, Yoshihiko Horio, Kazuyuki Aihara

    Physics Letters A ( Elsevier )   376 ( 24-25 )   1907 - 1917   2012.05

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    Torus-doubling bifurcations typically occur only a finite number of times. It has been assumed that torus-doubling bifurcations in quasiperiodically forced systems are interrupted by the appearance of strange nonchaotic attractors (SNAs). In the present Letter, we study a quasiperiodically forced noninvertible map and report the occurrence of a torus-doubling process via SNAs. The mechanism of this process is numerically clarified. Furthermore, this process is experimentally demonstrated in a switched-capacitor integrated circuit.

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Conference Prsentations (Oral, Poster)

  • CMOS Mixed-Signal Spiking Neural Network Circuit Using a Time-Domain Digital-To-Analog Converter

    Seiji Uenohara, Kazuyuki Aihara

    2021 IEEE International Symposium on Circuits and Systems (ISCAS) 

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    Event date: 2021.05.22 - 2021.05.28   Language:English