2021/09/17 更新

ウエノハラ セイジ
上ノ原 誠二
UENOHARA Seiji
Scopus 論文情報  
総論文数: 0  総Citation: 0  h-index: 3

Citation Countは当該年に発表した論文の被引用数

所属
大学院生命体工学研究科 人間知能システム工学専攻
職名
特任助教

取得学位

  • 九州工業大学  -  博士(工学)   2016年03月

学内職務経歴

  • 2020年08月 - 現在   九州工業大学   大学院生命体工学研究科   人間知能システム工学専攻     特任助教

論文

  • CMOS mixed-signal spiking neural network circuit using a time-domain digital-to-analog converter 査読有り

    Uenohara S., Aihara K.

    Proceedings - IEEE International Symposium on Circuits and Systems   2021-May   2021年01月

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    担当区分:責任著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    This paper proposes a high energy efficiency CMOS mixed-signal spiking neural network circuit using a time-domain digital-to-analog converter (TDAC) for realizing online and on-chip brainmorphic learning hardware. The circuit consists of a mixed-signal synapse circuit and an analog leaky integrate-and-fire neuron circuit. The TDAC converts synaptic weights held by digital memory into an analog current that realizes a biologically plausible synaptic response, which is employed as an output stage for our synapse circuit. To evaluate online and on-chip learning operation, the remote supervised method (ReSuMe) was implemented using TSMC 40-nm (1-poly, 8-metal) CMOS technology, and this circuit was evaluated by a Spectre circuit simulator. The circuit simulation results show that energy per synaptic event in our circuit was 20.1 fJ for multiply-accumulation operation and 92.1 fJ for ReSuMe.

    DOI: 10.1109/ISCAS51556.2021.9401230

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85109050626&origin=inward

  • Reconstructing bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems 査読有り 国際誌

    Yoshitaka Itoh, Seiji Uenohara, Masaharu Adachi, Takashi Morie, Kazuyuki Aihara

    Chaos ( American Institute of Physics )   30   013128-1 - 013128-11   2020年01月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)

    Bifurcation-diagram reconstruction estimates various attractors of a system without observing all of them but only from observing several attractors with different parameter values. Therefore, the bifurcation-diagram reconstruction can be used to investigate how attractors change with the parameter values, especially for real-world engineering and physical systems for which only a limited number of attractors can be observed. Although bifurcation diagrams of various systems have been reconstructed from time-series data generated in numerical experiments, the systems that have been targeted for reconstructing bifurcation diagrams from time series measured from physical phenomena so far have only been continuous-time dynamical systems. In this paper, we reconstruct bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems with different parameter values. The generated time-series datasets are perturbed by dynamical noise and contaminated by observational noise. To reconstruct the bifurcation diagrams only from the time-series datasets, we use an extreme learning machine as a time-series predictor because it has a good generalization property. Hereby, we expect that the bifurcation-diagram reconstruction with the extreme learning machine is robust against dynamical noise and observational noise. For quantitatively verifying the robustness, the Lyapunov exponents of the reconstructed bifurcation diagrams are compared with those of the bifurcation diagrams generated in numerical experiments and by the electronic circuits.

    その他リンク: https://aip.scitation.org/doi/abs/10.1063/1.5119187

  • Time-Domain Digital-to-Analog Converter for Spiking Neural Network Hardware 査読有り

    Uenohara Seiji, Aihara Kazuyuki

    Circuits, Systems, and Signal Processing   2020年01月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    © 2020, The Author(s). We propose a new digital-to-analog converter (DAC) for realizing a synapse circuit in mixed-signal spiking neural networks. We refer to this circuit as a “time-domain DAC (TDAC)”. It produces weights for converting a digital input code into voltage using one current waveform. Therefore, the TDAC is more compact than a conventional DAC consisting of many current sources and resistors. Moreover, a TDAC with leak resistance reproduces biologically plausible synaptic responses expressed as alpha functions or dual exponential equations. We also present numerical analysis results for a TDAC and circuit simulation results for a circuit designed using the TSMC 40 nm CMOS process.

    DOI: 10.1007/s00034-020-01597-2

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85097487076&origin=inward

  • Real-time implementation of ReSuMe learning in spiking neural network 査読有り

    Xia Yang, Seiji Uenohara, Kazuyuki Aihara, Takashi Kohno, Timothee Levi

    International Conference on Artificial Life and Robotics   45   2019年01月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

  • Noise-driven stochastic bistable circuits for brain-morphic systems 査読有り

    Yusuke Sakemi, Seiji Uenohara, Kazuyuki Aihara, Takashi Kohno,

    International Symposium on Nonlinear Theory and its Applications ( Institute of Electronics, Information and Communication Engineers )   666 - 669   2018年09月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

  • A pulse-width-modulation mode CMOS integrated circuit implementation of threshold-coupled map 査読有り

    Uenohara Seiji, Morie Takashi, Tamukoh Hakaru, Aihara Kazuyuki

    Nonlinear Theory and Its Applications, IEICE ( 一般社団法人 電子情報通信学会 )   9 ( 2 )   268 - 280   2018年01月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    <p>We propose a coupled-map-lattice complementary-metal-oxide-semiconductor very-large-scale-integration (CMOS VLSI) circuit based on the threshold-coupled map (TCM) that has been proposed previously as a unidirectional connected network model exhibiting different spatiotemporal patterns according to its underlying nonlinear map and update scheme. We introduce mutual connections and arbitrarily valued connection weights into the TCM to realize cellular automata. In this study, we design, fabricate, and evaluate a CMOS integrated circuit with which to implement this extended TCM (ETCM). The ETCM is a universal Turing machine as confirmed in circuit experiments using the fabricated circuit, which can achieve Rule110 of a one-dimensional cellular automaton.</p>

    DOI: 10.1587/nolta.9.268

    CiNii Article

    その他リンク: https://ci.nii.ac.jp/naid/130006602774

  • Hardware-oriented Algorithm for Chaotic Boltzmann Machines 査読有り

    Ichiro Kawashima, Seiji Uenohara, Takashi Kato, Masatoshi Yamaguchi, Hideyuki Suzuki, Takashi Morie, Hakaru Tamukoh

    International Workshop on Smart Info-Media Systems in Asia   2016年09月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

  • A-2-15 カオスボルツマンマシンのCMOS回路化(A-2.非線形問題,一般セッション)

    加藤 孝史, 上ノ原 誠二, 鈴木 秀幸, 田向 権, 森江 隆

    電子情報通信学会基礎・境界ソサイエティ/NOLTAソサイエティ大会講演論文集 ( 一般社団法人電子情報通信学会 )   2015   2015年08月

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    記述言語:日本語   掲載種別:研究論文(研究会,シンポジウム資料等)

    CiNii Article

    その他リンク: https://ci.nii.ac.jp/naid/110009996023

  • A-2-16 大規模非線形結合系のためのデバイスミスマッチ補償回路の評価(A-2.非線形問題,一般セッション)

    上ノ原 誠二, 森江 隆, 田向 権, 合原 一幸

    電子情報通信学会基礎・境界ソサイエティ/NOLTAソサイエティ大会講演論文集 ( 一般社団法人電子情報通信学会 )   2015   2015年08月

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    担当区分:筆頭著者   記述言語:日本語   掲載種別:研究論文(研究会,シンポジウム資料等)

    CiNii Article

    その他リンク: https://ci.nii.ac.jp/naid/110009996024

  • A CMOS circuit for PWM-mode nonlinear transformation robust to device mismatches to implement coupled map lattice models 査読有り

    Seiji Uenohara, Atuti Daisuke, Matsuzaka Kenji, Tamukoh Hakaru, Morie Takashi, Aihara Kazuyuki

    Nonlinear theory and its applications ( Institute of Electronics, Information and Communication Engineers )   6 ( 4 )   570 - 581   2015年04月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    In order to develop large-scale nonlinear dynamical systems using CMOS integrated circuits, we propose a core circuit for coupled map lattice (CML) models. The characteristics of the core circuits in the lattice on a chip are not generally equal, which is caused by CMOS device mismatches, including parasitic capacitance and wiring resistance. The proposed circuit solves this problem; it compensates for a DC offset voltage variation by holding it at a capacitor, and also for current variation by adjusting the bias voltage of a current source automatically so as to bring the current close to a target value. The proposed core circuit has been designed and fabricated using TSMC 0.25 µm CMOS technology. The measurement results using the fabricated circuit have shown that the bit precision is more than 8 bits, even if there is a DC offset voltage of 100 mV or a bias-voltage change of 100 mV in a switched current source.

    その他リンク: https://ci.nii.ac.jp/naid/130005102329

  • スパイク列フィルタとして動作するスパイキングカオス振動子回路 (非線形問題)

    山口 正登志, 上ノ原 誠二, 森江 隆

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 ( 一般社団法人電子情報通信学会 )   114 ( 414 )   77 - 82   2015年01月

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    記述言語:日本語   掲載種別:研究論文(研究会,シンポジウム資料等)

    スパイク列のフィルタとして動作するスパイキングカオス振動子モデルを実行するCMOS回路を提案する.このモデルは一定角周波数で振動する位相振動子で,所定の位相になったタイミングでスパイクパルスを出力するとともに,スパイク入力のタイミングで位相状態を所定の非線形関数にしたがって変換する.このモデルは,入力スパイクの周波数が分岐パラメータになっており,これを変えることでスパイク列を出力しない場合も含め,様々なスパイク列を出力することができる.特定の周波数の入力スパイク列に対してスパイクを出力しないなどの特性は,スパイク列フィルタとして機能することを意味する.このモデルを実行する提案回路は定電流源で充電するキャパシタに蓄積される電荷量により位相状態値を表現し,CMOSトランジスタの非線形特性を利用して非線形変換を実現する.提案回路を標準CMOS集積回路技術により設計・試作し,スパイク列フィルタとしての特性を試作回路の測定により評価し,動作を確認した結果を示す.

    CiNii Article

    その他リンク: https://ci.nii.ac.jp/naid/110010002094

  • A CMOS circuit for PWM-mode nonlinear transformation robust to device mismatches to implement coupled map lattice models 査読有り

    Uenohara Seiji, Atuti Daisuke, Matsuzaka Kenji, Tamukoh Hakaru, Morie Takashi, Aihara Kazuyuki

    Nonlinear Theory and Its Applications, IEICE ( 一般社団法人 電子情報通信学会 )   6 ( 4 )   570 - 581   2015年01月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    In order to develop large-scale nonlinear dynamical systems using CMOS integrated circuits, we propose a core circuit for coupled map lattice (CML) models. The characteristics of the core circuits in the lattice on a chip are not generally equal, which is caused by CMOS device mismatches, including parasitic capacitance and wiring resistance. The proposed circuit solves this problem; it compensates for a DC offset voltage variation by holding it at a capacitor, and also for current variation by adjusting the bias voltage of a current source automatically so as to bring the current close to a target value. The proposed core circuit has been designed and fabricated using TSMC 0.25 &micro;m CMOS technology. The measurement results using the fabricated circuit have shown that the bit precision is more than 8 bits, even if there is a DC offset voltage of 100 mV or a bias-voltage change of 100 mV in a switched current source.

    DOI: 10.1587/nolta.6.570

    CiNii Article

    その他リンク: https://ci.nii.ac.jp/naid/130005102329

  • Experimental distinction between chaotic and strange nonchaotic attractors on the basis of consistency 査読有り 国際誌

    Seiji Uenohara, Takahito Mitsui, Yoshito Hirata, Takashi Morie, Yohihiko Horio, Kazuyuki Aihara

    Chaos ( American Institute of Physics )   23   023110-9 - 023110-9   2013年05月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    e experimentally study strange nonchaotic attractors (SNAs) and chaotic attractors by using a nonlinear integrated circuit driven by a quasiperiodic input signal. An SNA is a geometrically strange attractor for which typical orbits have nonpositive Lyapunov exponents. It is a difficult problem to distinguish between SNAs and chaotic attractors experimentally. If a system has an SNA as a unique attractor, the system produces an identical response to a repeated quasiperiodic signal, regardless of the initial conditions, after a certain transient time. Such reproducibility of response outputs is called consistency. On the other hand, if the attractor is chaotic, the consistency is low owing to the sensitive dependence on initial conditions. In this paper, we analyze the experimental data for distinguishing between SNAs and chaotic attractors on the basis of the consistency.
    Strange nonchaotic attractors (SNAs) often appear in dynamical systems driven by a quasiperiodic signal. An SNA is a geometrically strange attractor for which typical orbits have nonpositive Lyapunov exponents. In fact, typical orbits are insensitive to initial conditions under a common quasiperiodic signal. Owing to their characteristics reminiscent of both quasiperiodic order and chaos, SNAs have attracted the attention of researchers from both theoretical and experimental perspectives. Conventionally, the information dimension is often employed to distinguish between SNAs and chaotic attractors in experiments. However, using the information dimension for the experimental distinction between these types of attractors is difficult as the estimation of the information dimension is highly sensitive to noise, and requires rather long time series. Recently, Ngamga et al.1 proposed a method for distinguishing between SNAs and chaotic attractors, which utilizes the consistency property of SNAs. Consistency here means that a nonlinear system shows the same response to the same input signal after some transient time, regardless of the initial conditions. In the method proposed by Ngamga et al., the determinism for a cross-recurrence plot of two response time series to the same input signal is used as a consistency measure. However, to our knowledge, there is no research paper on using their cross-recurrence method to experimentally distinguish between SNAs and chaotic attractors. In this study, we evaluated the consistency of a system by using the zero-delay normalized cross-correlation and Ngamga et al.'s cross-recurrence methods. By combining spectrum analysis and evaluation of consistency, we showed that SNAs and chaotic attractors can be distinguished more precisely as compared to conventional methods.

    DOI: 10.1063/1.4804181

    その他リンク: https://aip.scitation.org/doi/10.1063/1.4804181

  • 電圧・電流サンプリング方式によるしきい値結合CMOSカオス回路の設計 (ニューロコンピューティング) 査読有り

    上ノ原 誠二, 厚地 泰輔, 松坂 建治, 森江 隆, 合原 一幸

    電子情報通信学会技術研究報告 : 信学技報 ( 一般社団法人電子情報通信学会 )   112 ( 390 )   105 - 110   2013年01月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    本研究では, CMOS集積回路による大規模結合非線形ダイナミカルシステム実現のために,素子ばらつきに頑健なしきい値結合アレイ回路を提案する.我々はすでに,任意の非線形ダイナミカルシステムの実現法として,外部から与えられる非線形電圧波形をパルス幅/位相変調(PWM/PPM)信号によりキャパシタにサンプリングし,任意の非線形変換を行う電圧サンプリング方式回路と,同じく非線形電流波形をPPM信号でキャパシタにサンプリングする電流サンプリンク方式回路を提案してきた.両サンプリング方式にはそれぞれ,原理的にCMOS回路に不可避な構成素子のパラメータばらつきに頑健てあること,および結合状態の積和計算がノード結線で容易に実現できることという長所がある.これら二つの長所は大規模結合系を実装する上で非常に重要である.そこで本研究ではこれら2っの長所を生かした回路構成を採用し,大規模結合CMOS回路で問題となるアナログバッファ回路のシフト電圧ばらつきに頑健な回路を提案する.さらに,提案回路が電圧シフトに頑健であることをSPICEシミュレーションにより示す.

    CiNii Article

    その他リンク: https://ci.nii.ac.jp/naid/110009728129

  • Torus-doubling process via strange nonchaotic attractors 査読有り

    Takahito Mitsui, Seiji Uenohara, Takashi Morie, Yoshihiko Horio, Kazuyuki Aihara

    Physics Letters A ( Elsevier )   376 ( 24-25 )   1907 - 1917   2012年05月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)

    Torus-doubling bifurcations typically occur only a finite number of times. It has been assumed that torus-doubling bifurcations in quasiperiodically forced systems are interrupted by the appearance of strange nonchaotic attractors (SNAs). In the present Letter, we study a quasiperiodically forced noninvertible map and report the occurrence of a torus-doubling process via SNAs. The mechanism of this process is numerically clarified. Furthermore, this process is experimentally demonstrated in a switched-capacitor integrated circuit.

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口頭発表・ポスター発表等

  • CMOS Mixed-Signal Spiking Neural Network Circuit Using a Time-Domain Digital-To-Analog Converter

    Seiji Uenohara, Kazuyuki Aihara

    2021 IEEE International Symposium on Circuits and Systems (ISCAS) 

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    開催期間: 2021年05月22日 - 2021年05月28日   記述言語:英語   開催地:Koria