KAJIHARA Seiji

写真a

Laboratory

680-4 Kawazu, Iizuka-shi, Fukuoka

Research Fields, Keywords

Design and test of LSIs

Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 11

Citation count denotes the number of citations in papers published for a particular year.

Degree 【 display / non-display

  • Osaka University -  Doctor of Engineering  1992.03

Biography in Kyutech 【 display / non-display

  • 2020.04
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    Now

    Kyushu Institute of TechnologyExecutives  

  • 2020.04
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    Now

    Kyushu Institute of TechnologyOrganization for Information Infrastructure  

  • 2020.04
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    Now

    Kyushu Institute of TechnologyUniversity Library   Director  

  • 2019.04
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    2020.03

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Professor  

  • 2016.04
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    2020.03

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering  

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Academic Society Memberships 【 display / non-display

  • 2000.04
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    Now
     

    Journal of Electronic Testing: Theory and Applications

Specialized Field (scientific research fund) 【 display / non-display

  • Computer system

 

Publications (Article) 【 display / non-display

  • On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    IEICE Transactions on Information and Systems    E104D ( 6 ) 816 - 827   2021.01  [Refereed]

     View Summary

    Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

    DOI Scopus CiNii

  • On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test and Its Application to A Digital Sensor

    Gondo M., Miyake Y., Kato T., Kajihara S.

    Proceedings of the Asian Test Symposium    2020-November   1 - 6   2020.11  [Refereed]

     View Summary

    An aging-tolerant ring oscillator (RO) has been proposed for a digital temperature and voltage sensor. This paper discusses on the effectiveness of aging-tolerance of the ROs through accelerated life test for a test chip with 65nm CMOS technology. The progress of delay degradation of the ROs is examined, and influence of delay degradation on measurement accuracy of the sensor is investigated. Experimental results show that the aging-tolerant ROs can mitigate delay degradation, and that the measurement errors of the sensor can be reduced. Compared with a sensor consisting of an aging-intolerant RO, temperature and voltage errors are reduced 2.5°C and 32mV, respectively.

    repository DOI Scopus

  • Path Delay Measurement with Correction for Temperature and Voltage Variations

    Miyake Y., Kato T., Kajihara S.

    Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020      112 - 117   2020.09  [Refereed]

     View Summary

    Path delay measurement in field is useful for not only detection of delay-related faults but also prediction of aging-induced delay faults. In order to utilize the delay measurement results for fault detection and fault prediction, the measured delay must be corrected because the circuit delay is varied in field due to environment such as temperature or voltage variations. This paper proposes a method of BIST-based path delay measurement in which the influence of environmental variations is eliminated. An on-chip sensor measures temperature and voltage during delay measurement. Using information from the temperature and voltage sensor and pre-computed temperature and voltage sensitivities of the circuit delay, the measured delay value is corrected to a delay value that would be obtained under a fixed temperature and voltage. Evaluation for a test chip with 65nm CMOS technology implementing the proposed method shows that errors of measured delays brought by environmental variations could be reduced from 2419 to 211 ps in the range of 30 to 80 °C and 1.05 to 1.35 V. This paper also discusses application and feasibility for degradation detection of the proposed method.

    repository DOI Scopus

  • A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

    Kato T., Wang S., Sato Y., Kajihara S., Wen X.

    IEEE Transactions on Emerging Topics in Computing    8 ( 3 ) 591 - 601   2020.07  [Refereed]

     View Summary

    High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

    repository DOI Scopus

  • On-Chip Delay Measurement for Degradation Detection and Its Evaluation under Accelerated Life Test

    Miyake Y., Kato T., Kajihara S., Aso M., Futami H., Matsunaga S., Miura Y.

    Proceedings - 2020 26th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2020      2020.07  [Refereed]

     View Summary

    Periodical delay measurement in field is useful for not only detection of delay-related faults but also prediction of faults due to aging. Logic BIST with variable test clock generation enables on-chip delay measurement in field. This paper addresses a delay measurement scheme based on logic BIST and gives experiment results to observe aging phenomenon of test chips under accelerated life test. The measurement scheme consists of scan-based logic BIST, a variable test clock generator, and digital temperature and voltage sensors. The sensors are used to compensate measured delay values for temperature and voltage variations in field. Evaluation using SPICE simulation shows that the scheme can measure a circuit delay with resolution of 92 ps. The delay measurement scheme is also implemented on fabricated test chips with 180 nm CMOS technology and accelerated test is performed using ATE and burn-in equipment. Experimental results show that a circuit delay increased 552 ps when accelerated the chip for 3000 hours. It is confirmed that the on-chip delay measurement scheme has enough accuracy for detection of aging-induced delay increase.

    repository DOI Scopus

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Publications (Books) 【 display / non-display

  • はかる×わかる半導体-応用編

    浅田邦博(監修),井上智生,井上美智子,岩崎一彦,温暁青,梶原誠司,小林春夫,小松聡,佐藤康夫,志水勲,高橋寛,畠山一実 ( Joint Work ,  第1章1.1,1.2,1.4 )

    日経BPコンサルティング  2019.05 ISBN: 978-4-86443-130-9

     View Summary

    高度な半導体の設計、製造および高品質な回路設計手法、 最新の品質保証など、より実務に近く深い知識を解説しています。 本書は、半導体技術者検定 エレクトロニクス2級 「設計と製造」「応用と品質」の 公式テキストとして採用されています。

  • はかる×わかる半導体 半導体テスト技術者検定3級問題集

    浅田邦博(監修),小松聡,温暁青,梶原誠司,佐藤康夫,中村和之,井上美智子,小林春夫,畠山一実,志水勲,岩崎一彦,井上智生,高橋寛 ( Joint Work )

    日経BPコンサルティング  2014.12 ISBN: 978-4-8644-3071-5

     View Summary

    「半導体テスト技術者検定」の受検者向けに、問題と解答・解説をまとめた問題集.

  • はかる×わかる半導体-入門編

    浅田邦博(監修),温暁青,梶原誠司,小松聡,佐藤康夫,志水勲,中村和之,畠山一実 ( Joint Work ,  序章 )

    日経BPコンサルティング  2013.05 ISBN: 978-4-8644-3039-5

     View Summary

    半導体の構造から試験手法までわかりやすく解説

Conference Prsentations (Oral, Poster) 【 display / non-display

  • デジタル温度電圧センサにおける特定温度電圧領域の推定精度向上手法

    井上賢二

    電子情報通信学会DC研究会  (東京)  2018.02  -  2018.02  電子情報通信学会

  • FPGAの自己テストのためのTDCを用いたテストクロック観測手法の検討

    三宅庸資

    電子情報通信学会DC研究会  (秋田市)  2017.12  -  2017.12  電子情報通信学会

  • スキャンベース論理BISTにおけるマルチサイクルテストの中間観測FF選出手法について

    大島繁之

    電子情報通信学会DC研究会  (熊本市)  2017.11  -  2017.11  電子情報通信学会

  • On Avoiding Test Data Corruption by Optimal Scan Chain Grouping

    2017.11  -  2017.11 

  • デジタル温度電圧センサにおける温度2点補正手法の検討

    三宅庸資

    電子情報通信学会DC研究会  (秋田市)  2017.07  -  2017.07  電子情報通信学会

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Industrial Property 【 display / non-display

  • Ring Oscillator

    Industrial Property No 2011-008850  Patent No 6083586  JAPAN

    Yukiya Miura, Yasuo Sato, Seiji Kajihara

Lectures 【 display / non-display

  • A Fully Digital Temperature and Voltage Sensor for IoT Devices

    5th International Symposium on Applied Engineering and Sciences (SAES2017)   2017.11.15  Univerisiti Putra Malaysia

  • Right Power Testing for Scan-Based BIST and Its Evaluation with TEG Chips

    The 11th VLSI Test Technology Workshop   2017.07.11  Taiwann IC Design Society

  • Growth of ATS in the 21st century: Outlook of the future of ATS in Japan

    25th IEEE Asian Test Symposium   2016.11.23  IEEE Computer Society

  • VLSIテスト技術によるシステムディペンダビリティ向上への期待

    日本信頼性学会 第24回春季信頼性シンポジウム ( 東京 )  2016.05.23  日本信頼性学会

  • VLSIテスト技術によるシステムディペンダビリティ向上への期待

    電子情報通信学会デザインガイア2015 ( 長崎市 )  2015.12.01  電子情報通信学会

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Honors and Awards 【 display / non-display

  • IEICE Fellow

    2015.09.09     JAPAN

    Winner: Seiji Kajihara

  • ATS2015 Best Paper Award

    2016.11.22     JAPAN

    Winner: Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara

  • ITC2005 Most Significant Paper Award:

    2016.11.15     JAPAN

    Winner: Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara

Grants-in-Aid for Scientific Research 【 display / non-display

  • Reliability Prediction Using Manufacturing Test Results for Integrated Circuits

    Grant-in-Aid for challenging Exploratory Research

    Project Year:  2015.04  -  2018.03

    Project Number:  15K12004

  • Study on LSI testing for multiple fault models

    Grant-in-Aid for Scientific Research(C)

    Project Year:  2004.04  -  2007.03

    Project Number:  16500036

 

Activities of Academic societies and Committees 【 display / non-display

  • 2017.08
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    2017.11

    IEEE WRTLT  

  • 2017.04
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    2017.11

    Asian Test Symposium  

  • 2017.02
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    Now

    IEEE ITC-Asia  

  • 2016.08
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    2017.03

    Design Automation and Test in Europe conference and exhibition  

  • 2016.04
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    2016.11

    Asian Test Symposium   Ph.D. Thesis Contest Jury Member

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