Kyushu Institute of Technology   Organization for Information Infrastructure   University Library   Director  

Kyushu Institute of Technology   Organization for Information Infrastructure  

Kyushu Institute of Technology   Executives  

Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Professor  

Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering  

Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Creative Informatics   Professor  

High-Precision PLL Delay Matrix with Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters Reviewed

Chen P., Lan J.T., Wang R.T., My Qui N., Marquez J.C.J.S., Kajihara S., Miyake Y.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems   28 ( 4 )   904 - 913   2020.04

On-chip delay measurement for in-field test of FPGAs Reviewed International journal

Miyake Y., Sato Y., Kajihara S.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC   2019-December   130 - 137   2019.12

On-chip test clock validation using a time-to-digital converter in FPGAs Reviewed International journal

Miyake Y., Kajihara S., Chen P.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   157 - 162   2019.09

A static method for analyzing hotspot distribution on the LSI Reviewed

Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   73 - 78   2019.09

A selection method of ring oscillators for an on-chip digital temperature and voltage sensor Reviewed International journal

Miyake Y., Sato Y., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   13 - 18   2019.09

FPGA implementation of ECDSA for Blockchain Reviewed International journal

Tachibana S., Araki S., Kajihara S., Azuchi S., Nakajo Y., Shoda H.

2019 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2019   2019.05

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST Reviewed

2018-October   30 - 35   2018.12

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed

2018-October   149 - 154   2018.12

Good die prediction modelling from limited test items Reviewed International journal

115 - 120   2018.09

Scan chain grouping for mitigating ir-drop-induced test data corruption Reviewed

140 - 145   2018.01

Analysis and mitigation or IR-Drop induced scan shift-errors Reviewed

2017-December   1 - 8   2017.12

On the effects of real time and contiguous measurement with a digital temperature and voltage sensor Reviewed

125 - 130   2017.11

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST Reviewed

203 - 208   2016.12

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed

19 - 24   2016.12

Logic-path-and-clock-path-aware at-speed scan test generation Reviewed

E99A ( 12 )   2310 - 2319   2016.12

Temperature and voltage measurement for field test using an Aging-Tolerant monitor Reviewed

24 ( 11 )   3282 - 3295   2016.11

Physical Power Evaluation of Low Power Logic-BIST Scheme using TEG Chip Reviewed

Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi

ASP Journal of Low Power Electronics   11 ( 4 )   1 - 13   2015.12

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretcht Reviewed

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

IEEE Asian Test Symposium   103 - 108   2015.11

Identification of High Power Consuming Areas with Gate Type and Logic Level Information Reviewed

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

IEEE European Test Symposium   Paper9.1-1 (6 pages)   2015.05

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA Reviewed

Yasuo Sato,Masafumi Monden, Yousuke Miyake, Seiji Kajihara

IEEE Pacific Rim International Symposium on Dependable Computing   59 - 67   2014.11

Power Evaluation of a Low Power Logic BIST Scheme Using TEG Chip Reviewed

Senling Wang, Toshiya Nishida, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi

IEEE Workshop on RTL and High Level Testing   1 - 6   2014.11

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test Reviewed

Yousuke Miyake,Yasuo Sato,Seiji Kajihara,Yukiya Miura

IEEE Asian Test Symposium   156 - 161   2014.11

An On-Chip Digital Environment Monitor for Field Test Invited Reviewed

Seiji Kajihara,Yousuke Miyake,Yasuo Sato,Yukiya Miura

IEEE Asian Test Symposium   254 - 257   2014.11

Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories Reviewed

Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara

IEEE Asian Test Symposium   16 - 19   2014.11

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed

Akihiro Tomita,Xiaoqing Wen,Yasuo Sato,Seiji Kajihara,Kohei Miyase,Stefan Holst,Patrick Girard,Mohammad Tehranipoor,Laung-Terng Wan

IEICE Transactions on Information and Systems   E97-D ( 10 )   2706 - 2718   2014.10

Highly Accurate Delay Time Measurement by an On-Chip Circuit

Yukiya Miura,Yasuo Sato,Seiji Kajihara

Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   451 - 451   2013.12

Logging and Using Field Test Data for Improved Dependability

Seiji Kajihara, Satoshi Ohtake

Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   518 - 518   2013.12

Field Test Role for Danger of Physical Degradation

Yasuo Sato,Seiji Kajihara

Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   461 - 461   2013.12

A Flexible Temperature and Voltage Monitor for Field Test Reviewed

Yousuke Miyake,Yasuo Sato,Seiji Kajihara,Yukiya Miura

IEEE Workshop on RTL and High Level Testing   Paper Ⅲ.3.F   2013.11

A Stochastic Model for NBTI-Induced LSI Degradation in Field Reviewed

Yasuo Sato,Seiji Kajihara

IEEE Asian Test Symposium   183 - 188   2013.11

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed

Akihiro TOMITA, Xiaoqing WEN, Yasuo SATO, Seiji KAJIHARA, Patrick GIRARD, Mohammad TEHRANIPOOR, Laung-Terng WANG

IEEE Asian Test Symposium   19 - 24   2013.11

Search Space Reduction for Low-Power Test Generation Reviewed

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

IEEE Asian Test Symposium   171 - 176   2013.11

Scan-Out Power Reduction for Logic BIST Reviewed

Senling Wang,Yasuo Sato,Seiji Kajihara,Kohei Miyase

IEICE Transactions on Information and Systems   E96-D ( 9 )   2012 - 2020   2013.09

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Reviewed

Kohei Miyase,Ryouta Sakai,Xiaoqing Wen,Masao Aso,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara

IEICE Transactions on Information and Systems   E96-D ( 9 )   2003 - 2011   2013.09

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing Reviewed

Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang

IEEE Design & Test of Computers   30 ( 4 )   60 - 70   2013.08

Controllability Analysis of Local Switching Activity for Layout Design Reviewed

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Workshop on Design and Test Methodologies for Emerging Technologies   Paper 1   2013.05

On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression Reviewed

Kazunari Enokimoto,Xiaoqing Wen,Kohei Miyase,J.-L. Huang,Seiji Kajihara, Laung-Terng Wang

International Conference on VLSI Design   279 - 284   2013.01

5.4 Field Test Role for Danger of Physical Degradation(5. Time-Dependent Degradation in Device Characteristics,<Special Survey>Dependable VLSI System)

SATO Yasuo, KAJIHARA Seiji

The Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   2013.01

4.6 Highly Accurate Delay Time Measurement by an On-Chip Circuit(4. Variations in Device Characteristics,<Special Survey>Dependable VLSI System)

MIURA Yukiya, SATO Yasuo, KAJIHARA Seiji

The Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   2013.01

10.4 Logging and Using Field Test Data for Improved Dependability(10. Future and / or Un-Identified Problems,<Special Survey>Dependable VLSI System)

KAJIHARA Seiji, OHTAKE Satoshi

The Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   2013.01

Estimation of the Amount of Don't-Care Bits in Test Vectors Reviewed

Kohei Miyase, Xiaoqing Wen, Seiji Kajihara

IEEE Workshop on RTL and High Level Testing   Paper 2.3   2012.11

A Scan-Out Power Reduction Method for Multi-Cycle BIST Reviewed

Senling Wang,Yasuo Sato,Kohei Miyase,Seiji Kajihara

IEEE Asian Test Symposium   272 - 277   2012.11

Low Power BIST for Scan-Shift and Capture Power Reviewed

Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara

IEEE Asian Test Symposium   173 - 178   2012.11

DART: Dependable VLSI Test Architecture and Its Implementation Reviewed

Yasuo Sato,Seiji Kajihara,Tomokazu Yoneda,Kazumi Hatayama,Michiko Inoue,Yukiya Miura,Satoshi Ohtake,Takumi Hasegawa,Motoyuki Sato,Kotaro Shimamura

IEEE International Test Conference   Paper 15.2   2012.11

On Pinpoint Capture Power Management in At-Speed Scan Test Generation Reviewed

Xiaoqing Wen, Yuichiro Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

IEEE International Test Conference   2012.11

A Failure Prediction Strategy for Transistor Aging Reviewed

Hyunbean Yi,Tomokazu Yoneda,Michiko Inoue,Yasuo Sato,Seiji Kajihara,Hideo Fujiwara

IEEE Transactions on VLSI Systems   20 ( 11 )   1951 - 1959   2012.11

On-chip Temperature and Voltage measurement for Field Testing Reviewed

Yukiya Miura,Yasuo Sato,Yousuke Miyake,Seiji Kajihara

IEEE European Test Symposium   Paper 15.2   2012.05

A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits Reviewed

Kohei Miyase,Masao Aso,Ryou Ootsuka,Xiaoqing Wen,Hiroshi Furukawa,Yuta Yamato,Kazunari Enokimoto,Seiji Kajihara

IEEE VLSI Test Symposium   197 - 202   2012.04

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling Reviewed

K. Miyase, Y. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard, A. Virazel

IEEE 20th Asian Test Symposium   90 - 95   2011.11

Multi-Cycle Test with Partial Observation on Scan-Based BIST Structure, "jointly worked" Reviewed

Yasuo Sato, Seiji Kajihara, Hiaso Yamaguchi, Makoto Matsuzono

IEEE 20th Asian Test Symposium   54 - 59   2011.11

A novel scan segmentation design method for avoiding shift timing failures in scan testing Reviewed

Yuta Yamato,Xiaoqing Wen, Michael A. Kochte, Seiji Kajihara, Kohei Miyase, Laung-Terng Wang

IEEE International Test Conference   Paper 12.1   2011.09

SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures Reviewed

Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato,Kazunari Enokimoto, H.-J. Wunderlich

IEEE Intl. Symp. on Low Power Electronics and Design   33 - 38   2011.08

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing Reviewed

51. Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

IEICE Transactions on Information and Systems   E94-D ( 6 )   1216 - 1226   2011.06

Transition-time-relation based capture-safety checking for at-speed scan test generation Reviewed

895 - 898   2011.05

Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing Reviewed

Xiaoqing Wen,Kazunari Enokimoto,Kohei Miyase, Yuta Yamato, Michael A. Kochte,Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor

IEEE VLSI Test Symposium   166 - 171   2011.05

A GA-based x-filling for reducing launch switching activity toward specific objectives in at-speed scan testing Reviewed

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

IEICE Transactions on Information and Systems   E94-D ( 4 )   833 - 840   2011.04

Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation Reviewed

Kohei Miyase,Xiaoqing Wen,Masao Aso,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara

Design Automation and Test in Europe   895 - 898   2011.03

A Pattern Partitioning Algorithm for Field Test Reviewed

Senling Wang,Seiji Kajihara,Yasuo Sato,Xiaoxin Fan,Sudhakar M Reddy

IEEE International Workshop on Reliability Aware System Design and Test   31 - 36   2011.01

CAT (Critical-Area-Targeted): A new paradigm for reducing yield loss risk in at-speed scan testing Reviewed

27 ( 1 )   197 - 202   2010.12

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme Reviewed

Kohei Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara

IEEE Workshop on RTL and High Level Testing   125 - 129   2010.12

Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver Reviewed

Kohei Miyase,Michael A. Kochte,Xiaoqing Wen,Seiji Kajihara,Hans-Joachim Wunderlich

International Workshop on Defect and Data Driven Testing   2010.11

On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test Reviewed

Seiji Kajihara,Makoto Matsuzono,Hisato Yamaguchi,Yasuo Sato,Kohei Miyase,Xiaoqing Wen

International Symposium on Communications and Information Technologies   723 - 726   2010.10

On Delay Test Quality for Test Cubes Reviewed

S. Oku,S. Kajihara,Y. Sato,K. Miyase,X. Wen

IPSJ Transactions on System LSI Design Methodology   3   283 - 291   2010.08

A Study of Capture-Safe Test Generation Flow for At-Speed Testing Reviewed

Kohei Miyase,Xiaoqing Wen,Seiji Kajihara,Yuta Yamato,Atsushi Takashima,Hiroshi Furukawa,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Kewal K. Saluja

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E93-A ( 7 )   1309 - 1318   2010.07

Aging test strategy and adaptive test scheduling for soc failure prediction Reviewed

Hyunbean Yi,Tomokazu Yoneda,Michiko Inoue,Yasuo Sato,Seiji Kajihara,Hideo Fujiwara

IEEE International On-Line Testing Symposium   21 - 26   2010.07

On Estimation of NBTI-Induced Delay Degradation Reviewed

M. Noda,S. Kajihara,Y. Sato,K. Miyase,X. Wen,Y. Miura

IEEE European Test Symposium   107 - 111   2010.05

High Launch Switching Activity Reduction in At- Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Reviewed

Kohei Miyase,Xiaoqing Wen,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara,Patrick Girard,Laung-Terng Wang,Mohammad Tehranipoor

IEICE Transactions on Information and Systems   E93-D ( 1 )   2 - 9   2010.01

On Calculation of Delay Range in Fault Simulation for Test Cubes Reviewed

Seiji KAJIHARA,Shinji OKU,Kohei MIYASE,Xiaoqing WEN,Yasuo SATO

International Symposium on VLSI Design, Automation, and Test   64 - 67   2009.04

On Delay Calculation in 3-valued Fault Simulation Reviewed

Shinji OKU,Seiji KAJIHARA,Kohei MIYASE,Xiaoqing WEN,Yasuo SATO

IEEE Workshop on RTL and High Level Testing   2008.11

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing Reviewed

H. Furukawa,X. Wen,K. Miyase,Y. Yamato,S. Kajihara,P. Girard,L. -T. Wang,M. Tehranipoor

Asian Test Symposium   397 - 402   2008.11

Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification Reviewed

Kohei Miyase,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Yuta Yamato,Hiroshi Furukawa,Xiaoqing Wen,Seiji Kajihara

IEEE/ACM International Conference on Computer-Aided Design   52 - 58   2008.11

GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing Reviewed

Yuta Yamato,Xiaoqing Wen,Kohei Miyase,Hiroshi Furukawa,Seiji Kajihara

IEEE International Workshop on Defect and Data Driven Testing   2008.10

Estimation of Delay Test Quality and Its Application to Test Generation Reviewed

Seiji Kajihara,Shohei Morishima,Masahiro Yamamoto,Xiaoqing Wen,Masayasu Fukunaga,Kazumi Hatayama,Takashi Aikyo

IPSJ Transactions on System LSI Design Methodology   2008.08

Diagnosis of Realistic Defects Based on the X-Fault Model Reviewed

Ilia Polian,Yusuke Nakamura,Piet Engelke,Stefan Spinner,Kohei Miyase,Seiji Kajihara,Bernd Becker,Xiaoqing Wen

IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems   2008.04

Low-Capture-Switching- Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing Reviewed

Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja

Journal of Electronic Testing:Theory and Applications   2008.04

Aging test strategy and adaptive test scheduling for soc failure prediction Reviewed

Hyunbean Yi,Tomokazu Yoneda,Michiko Inoue,Yasuo Sato,Seiji Kajihara,Hideo Fujiwara

IEEE International On-Line Testing Symposium   21 - 26   2008.04

A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Reviewed

Yuta Yamato,Yusuke Nakamura,Kohei Miyase,Xiaoqing Wen,Seiji Kajihara

IEICE Transactions on Information and Systems   E91-D   667 - 674   2008.03

On Detection of Bridge Defects with Stuck-at Tests Reviewed

Kohei Miyase,Kenta Terashima,Xiaoqing Wen,Seiji Kajihara,Sudhakar M. Reddy

IEICE Transactions on Information and Systems   E91-D ( 3 )   683 - 689   2008.03

Estimation of Delay Test Quality and Its Application to Test Generation Reviewed

Seiji Kajihara,Shohei Morishima,Masahiro Yamamoto,Xiaoqing Wen,Masayasu Fukunaga,Kazumi Hatayama,Takashi Aikyo

IEEE/ACM International Conference on Computer-Aided Design   413 - 417   2007.11

A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing Reviewed

Xiaoqing Wen,Kohei Miyase,Seiji Kajihara,Tatsuya Suzuki,Yuta Yamato,Patrick Girard,Yuji Ohsumi,Laung-Terng Wang

International Test Conference   10 - 10   2007.10

A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set Reviewed

Kohei Miyase,Xiaoqing. Wen,Seiji. Kajihara,Masahiro Yamamoto,Hiroshi Furukawa

2007 IEEE International Workshop on Current & Defect Based Testing   51 - 56   2007.10

A Novel ATPG Method for Capture Power Reduction during Scan Testing Reviewed

Xiaoqing Wen,Seiji Kajihara,Kohei Miyase,Tatsuya Suzuki,Kewal K. Saluja,Laung-Terng Wang,Kozo Kinoshita

IEICE Transactions on Information and Systems   E90-D ( 9 )   1398 - 1405   2007.09

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing Reviewed

Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,Seiji Kajihara,Yuji Ohsumi,Kewal. K. Saluja

ACM/IEEE Design Automation Conference   527 - 532   2007.06

On Finding Don't Cares in Test Sequences for Sequential Circuits Reviewed

Yoshinobu Higami,Seiji Kajihara,Irith Pomeranz,Shin-ya Kobayashi,Yuzo Takamatsu

IEICE Trans. Info. & Syst.   E89-D ( 11 )   2748 - 2755   2006.11

An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits Reviewed

Xiaoqing Wen ,Yuta Yamato,Kohei Miyase,Seiji Kajihara,Hiroshi Furukawa,Laung-Terng Wang ,Kewal K. Saluja,Kozo Kinoshita

6th IEEE Workshop on RTL and High Level Testing   55 - 60   2006.11

A Framework of High-quality Transition Fault ATPG for Scan Circuits Reviewed

Seiji Kajihara,Shohei Morishima,Akane Takuma,Xiaoqing Wen,Toshiyuki Maeda,Shuji Hamada,Yasuo Sato

International Test Conference   2006.10

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation Reviewed

Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,Yuta Yamato,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja

International Conference on Computer Design   251 - 258   2006.10

Hybrid fault simulation with compiled and event-driven methods Reviewed

Kenjiro Taniguchi,Hideo Fujii,Seiji Kajihara,Xiaoqing Wen

IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology   240 - 243   2006.09

統計的遅延品質モデル（SDQM）のフィージビリティ評価 Reviewed

佐藤康夫,浜田周治,前田敏行,高取厚夫,野津山泰行,梶原誠司

電子情報通信学会論文誌 D-I   J89-D-I ( 8 )   1717 - 1728   2006.08

a Reviewed

47 ( 6 )   1648 - 1657   2006.06

A New Method for Low-Capture-Power Test Generation for Scan Testing Reviewed

Xiaoqing Wen,Yoshiyuki Yamashita,Shohei Morishima,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

IEICE Trans. Info. & Syst.   E89-D ( 5 )   1679 - 1686   2006.05

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing Reviewed

Xiaoqing Wen,Seiji Kajihara,Kohei Miyase,Tatsuya Suzuki,Kewal K. Saluja,Laung-Terng Wang,Khader S. Abdel-Hafez,Kozo Kinoshita

IEEE VLSI Test Symposium   58 - 63   2006.05

A statistical quality model for delay testing Reviewed

Yasuo Sato,Shuji Hamada,Toshiyuki Maeda,Atsuo Takatori,Seiji Kajihara

IEICE Trans. ELECTRONICS   E89-C ( 3 )   349 - 355   2006.03

A dynamic test compaction procedure for high-quality path delay testing Reviewed

Masayasu Fukunaga,Seiji Kajihara,Xiaoqing Wen,Toshiyuki Maeda,Shuji Hamada,Yasuo Sato

Asia and South Pacific Design Automation Conference   348 - 353   2006.01

On Improving Defect Coverage of Stuck-at Fault Tests Reviewed

K. Miyase,K. Terashima,S. Kajihara,X. Wen,S.M. Reddy

Asian Test Symposium   216 - 221   2005.12

Low-Capture-Power Test Generation for At-Speed Scan Testing Reviewed

Xiaoqing Wen,Yoshiyuki Yamashita,Shohei Morishima,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

International Test Conference   2005.11

Invisible delay quality - SDQM model lights up what could not be seen Reviewed

Yasuo Sato,Shuji Hamada,Toshiyuki Maeda,Atsuo Takatori,Yasuyuki Nozuyama,Seiji Kajihara

International Test Conference   2005.11

Three-Stage Compression Approach to Reduce Test Data Volume and Testing Time for IP Cores in SOCs Reviewed

Lei Li,Krishnendu Chakrabarty,Seiji Kajihara,Shivakumar Swaminathan

IEE Proc. Computers & Digital Technique   152 ( 6 )   704 - 712   2005.11

On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis Reviewed

Masayasu Fukunaga,Seiji Kajihara,Sadami Takeoka

IEICE Trans. Info. and Syst.   E88-D ( 7 )   1671 - 1677   2005.07

On Quantifying Observability for Fault Diagnosis of VLSI Circuits Reviewed

Naoya Toyota,Seiji Kajihara,Xiaoqing Wen,Masaru Sanada

5th IEEE Workshop on RTL and High Level Testing   192 - 197   2005.07

A Method for Low-Capture-Power At-Speed Scan Test Generation Reviewed

Xiaoqing Wen,Yoshiyuki Yamashita,Shohei Morishima,Seiji Kajihara,L.-T. Wang,Kewal. K. Saluja,Kozo Kinoshita

5th IEEE Workshop on RTL and High Level Testing,   40 - 49   2005.07

Path Delay Test Compaction with Process Variation Tolerance Reviewed

Seiji Kajihara,Masayasu Fukunaga,Xiaoqing Wen,Toshiyuki Maeda,Shuji Hamada,Yasuo Sato

Design Automation Conference   845 - 850   2005.06

On the Extraction of a Minimum Cube to Justify Signal Line Values Reviewed

Kohei Miyase,Shinobu Nagayama,Seiji Kajihara,Xiaoqing Wen,Sudhakar M. Reddy

European Test Symposium   79 - 84   2005.05

On Low-Capture-Power Test Generation for Scan Testing Reviewed

Xiaoqing Wen,Yoshiyuki Yamashita,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

VLSI Test Symposium   265 - 270   2005.05

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Reviewed

Xiaoqing WEN,Seiji KAJIHARA,Hideo TAMAMOTO,Kewal K. SALUJA,and Kozo KINOSHITA

IEICE Trans. Info. and Syst   E88-D ( 4 )   703 - 710   2005.04

中間故障電圧値を扱う故障シミュレーションの高速化について Reviewed

温暁青,梶原誠司,玉本英夫,Kewal K. Saluja,樹下行三

電子情報通信学会論文誌 D-I   J88-D-I ( 4 )   906 - 907   2005.04

Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores Reviewed

Lei Li,Krishnendu Chakrabarty,Seiji Kajihara,Shivakumar Swaminathan

International Conference on VLSI Design   53 - 58   2005.01

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation Reviewed

Yasumi Doi,Seiji Kajihara,Xiaoqing Wen,Lei Li,Krishnendu Chakrabarty

Asia and South Pacific Design Automation Conference   59 - 64   2005.01

Evaluation of Statistical Delay Quality Model Reviewed

Yasuo Sato,Shuji Hamada,Toshiyuki Maeda,Atsuo Takatori,Seiji Kajihara

Asia and South Pacific Design Automation Conference   305 - 310   2005.01

Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction Reviewed

Yoshinobu Higami,Seiji Kajihara,Shin-ya Kobayashi,Yuzo Takamatsu

Asian Test Symposium   46 - 49   2004.11

On Per-Test Fault Diagnosis Using the X-Fault Model Reviewed

Xiaoqing Wen,Tokiharu Miyoshi,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

International Conference on Computer-Aided Design   633 - 640   2004.11

On extraction of a cube with the minimum number of literals from a given input vector Reviewed

Kohei Miyase,Shinobu Nagayama,Seiji Kajihara,Xiaoqing Wen,Sudhakar M. Reddy

Workshop on RTL and High Level Testing   71 - 76   2004.11

On Estimation of Fault Efficiency for Path Delay Faults Reviewed

Masayasu Fukunaga,Seiji Kajihara,Sadami Takeoka

Asian Test Symposium   64 - 67   2004.11

Multiple Scan Tree Design with Test Vector Modification Reviewed

Kohei Miyase,Seiji Kajihara,Sudhakar M. Reddy

Asian Test Symposium   76 - 81   2004.11

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits Reviewed

Yoshinobu Higami,Seiji Kajihara,Shinya Kobayashi,Yuzo Takamatsu,Irith Pomeranz

International Conference on Computer Design   397 - 399   2004.10

Scan Tree Design: Test compression with Test Vector Modification Reviewed

Kohei Miyase,Seiji Kajiahra

44 ( 5 )   1270 - 1278   2004.05

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values Reviewed

Seiji Kajihara,Kewal K. Saluja,Sudhakar M. Reddy

European Test Symposium(Formal proceedings)   108 - 113   2004.05

Efficient Space/Time Compression of Test Data for Multiple Scan Chain Designs Reviewed

Lei Li,Krishnendu Chakrabarty,Seiji Kajihara,Shivakumar Swaminathan

European Test Symposium(Informal Digest of Papers)   265 - 266   2004.05

論理回路に対するテストコスト削減法　－テストデータ量およびテスト実行時間の削減－ Reviewed

樋上喜信,梶原誠司,市原英行,高松雄三

電子情報通信学会論文誌D-I   J87-D-I ( 3 )   291 - 307   2004.03

Test Data Compression Using Don't-Care Identification and Statistical Encoding Reviewed

Seiji Kajihara,Kenjiro Taniguchi,Kohei Miyase,Irith Pomeranz,Sudhakar M. Reddy

IEICE Trans. Info. and Syst.,   E87-D ( 3 )   544 - 550   2004.03

XID: Don't Care Identification of Test Patterns for Combinational Circuits Reviewed

Kohei Miyase,Seiji Kajihara

IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems   23 ( 2 )   321 - 326   2004.02

Random Access Scan: A Solution to test power, test data volume and test time Reviewed

Dong Hyun Baik,Seiji Kajihara,Kewal K. Saluja

International Conference on VLSI Design   883 - 888   2004.01

Evaluation of Delay Testing based on Path Selection Reviewed

Masayasu Fukunaga,Seiji Kajihara,Sadami Takeoka,Shinichi Yoshimura

IEICE Trans. Fundamentals.   E86-A ( 12 )   3208 - 3210   2003.12

Optimal Scan Tree Construction with Test Vector Modification for Test Compression Reviewed

Kohei Miyase,Seiji Kajihara

Asian Test Symposium   136 - 141   2003.11

On Test Data Volume Reduction for Multiple Scan Chain Designs Reviewed

Sudhakar M. Reddy,Kohei Miyase,Seiji Kajihara,Irith Pomeranz

ACM Transactions on Design Automation of Electronic Systems   8 ( 4 )   460 - 469   2003.10

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume Reviewed

Seiji Kajihara,Yasumi Doi,Lei Li,Krishnendu Chakrabarty

International Conference on Computer Design   387 - 392   2003.10

On Selecting Testable Paths in Scan Designs Reviewed

Yun Shao,Sudhakar M.Reddy,Irith Pomeranz,Seiji Kajihara

Journal of Electronic Testing Theory and Applications   19 ( 4 )   447 - 456   2003.08

On Effective Criterion of Path Selection for Delay Testing Reviewed

Asia and South Pacific Design Automation Conference   757 - 762   2003.01

Test data volume reduction using statistical encoding for multiple scan chain designs Reviewed

Kenjiro TANIGUCHI,Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ of Iowa)

3rd IEEE Workshop on RTL ATPG & DFT   106 - 109   2002.11

Test Data Compression Using Don't Care Identification and Statistical Encoding Reviewed

Seiji KAJIHARA,Kenjiro TANIGUCHI,Kohei MIYASE,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

11th IEEE Asian Test Symposium   67 - 72   2002.11

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout Reviewed

Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Purdue Univ.),Huaxing TANG,Seiji KAJIHARA,Kozo KINOSHITA(Osaka Gakuin Univ.)

International Test Conference   83 - 89   2002.10

Average Power Reduction in Scan Testing by Test Vector Modification Reviewed

Seiji KAJIHARA,Koji ISHIDA,Kohei MIYASE

IEICE Trans. Information and Systems   E85-D ( 10 )   1483 - 1489   2002.10

Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan Reviewed

IEICE Trans. Information and Systems   E85-D ( 10 )   1490 - 1497   2002.10

Don't Care Identification on Specific Bits of Test Patterns Reviewed

Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

International Conference on Computer Design   194 - 199   2002.09

テストパターン中の特定ビットにおけるドントケア判定法について Reviewed

宮瀬紘平,梶原誠司,イリス ポメランツ(Purdue Univ.),スダーカ レディ(Univ. of Iowa)

情報科学技術フォーラム 情報技術レターズ   1 ( LC-3 )   47 - 48   2002.09

On Selecting Paths to Test in Scan Designs Reviewed

Yun SHAO(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Purdue Univ.),Seiji KAJIHARA

European Test Workshop   233 - 238   2002.05

On Testing of Interconnect Open Faults in Combinational Logic Circuits with Stems of Large Fanout Reviewed

Huaxing TANG(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Purdue Univ.),Seiji KAJIHARA,Kozo KINOSHITA(Osaka Gakuin Univ.)

European Test Workshop   127 - 128   2002.05

On Test Data Volume Reduction for Multiple Scan Chain Designs Reviewed

Sudhakar M. REDDY(Univ. of Iowa),Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.)

IEEE VLSI Test Symposium   103 - 108   2002.05

A Method of Static Test Compaction Based on Don't Care Identification Reviewed

Kohei MIYASE,Seiji KAJIHARA,Sudhakar M. REDDY(Univ. of Iowa)

43 ( 5 )   1290 - 1293   2002.05

Test Vector Modification for Power Reduction during Scan Testing Reviewed

Seiji KAJIHARA,Koji ISHIDA,Kohei MIYASE

IEEE VLSI Test Symposium   160 - 165   2002.04

Test Data Compression Using Don't Care Identification and Statistical Encoding Reviewed

Seiji KAJIHARA,Kenjiro Taniguchi,Irith POMERANZ(Purdue Univ.),and Sudhakar M. REDDY(Univ. of Iowa)

IEEE International Workshop on Electronic Design, Test & Applications   413 - 416   2002.01

A Method of Static Test Compaction Based on Don't Care Identification Reviewed

Kohei MIYASE,Seiji KAJIHARA,Sudhakar M. REDDY(Univ. of Iowa)

IEEE International Workshop on Electronic Design, Test & Applications   392 - 395   2002.01

Test Power Reduction for Full Scan Sequential Circuits by Test Vector Modification Reviewed

Seiji KAJIHARA,Koji ISHIDA,Kohei MIYASE

IEEE Workshop on RTL ATPG & DFT   140 - 145   2001.11

An Efficient Method to Identify Untestable Path Delay Faults Reviewed

Yun SHAO(Univ. of Iowa),Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

10th IEEE Asian Test Symposium   233 - 238   2001.11

Hybrid BIST Using Partially Rotational Scan Reviewed

Kenichi ICHINO(Tokyo Metoropolitan Univ.),Takeshi ASAKAWA(Tokyo Metoropolitan Univ.),Satoshi FUKUMOTO(Tokyo Metoropolitan Univ.),Kazuhiko IWASAKI(Tokyo Metoropolitan Univ.),Seiji KAJIHARA

10th IEEE Asian Test Symposium   379 - 384   2001.11

On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits Reviewed

Seiji KAJIHARA,Kohei MIYASE

IEEE/ACM International Conference on Computer-Aided Design   364 - 369   2001.11

Test volume reduction for multiple scan chain designs by modifyingand encoding scan vectors Reviewed

Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

2nd IEEE International Workshop on Test Resource Partitioning   2001.11

Selection of Potentially Testable Path Delay Faults for Test Generation Reviewed

Atsushi MURAKAMI,Seiji KAJIHARA,Tsutomu SASAO,Irith POMERANZ(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa)

Proceedings of IEEE International Test Conference   376 - 384   2001.10

トランジション故障を検出するBIST指向テストパターン発生回路 Reviewed

浅川毅(都立大),岩崎一彦(都立大),梶原誠司

電子情報通信学会論文誌D-I   J84-D-I ( 2 )   165 - 172   2001.04

最小テスト集合でテスト可能な加算器について Reviewed

梶原誠司,笹尾勤

情報処理学会論文誌   42 ( 4 )   1045 - 1053   2001.04

Enhanced Untestable Path Analysis Using Edge Graphs Reviewed

Seiji KAJIHARA,Takashi SHIMONO,Irith POMERANZ(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa)

Proceedings of 9th IEEE Asian Test Symposium   139 - 144   2000.12

On Validating Data Hold Times for Flip-flops in Sequential Circuits Reviewed

Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Univ. of Iowa),Seiji KAJIHARA,Atsushi MURAKAMI,Sadami TAKEOKA(Matsushita),Mitsuyasu OHTA(Matsushita)

Proceedings of IEEE International Test Conference   317 - 324   2000.10

On Processing Order for Obtaining Implication Relations in Static Learning Reviewed

Hideyuki Ichihara(Hiroshima City Univ.),Seiji Kajihara,Kozo Kinoshita(Osaka Univ.)

IEICE Trans. Information and Systems   E83-D ( 10 )   1908 - 1911   2000.04

論理回路における遅延テスト不要パスの高速導出法 Reviewed

梶原誠司,樹下行三（大阪大）,イリス ポメランツ(Univ. of Iowa),スダーカ M. レディ(Univ. of Iowa)

電子情報通信学会論文誌D-I   J82-D-I ( 7 )   888 - 896   2000.04

テスト数制限下でのテスト生成手法について Reviewed

市原英行（大阪大）,梶原誠司,樹下行三（大阪大）

電子情報通信学会論文誌 D-I   J82-D-I ( 7 )   861 - 868   2000.04

On Compact Test Sets for Multiple Stuck-at Faults in Large Circuits Reviewed

Seiji Kajihara,Atsushi Murakami,Tomohisa Kaneko

8th IEEE Asian Test Symposium   20 - 24   1999.11

On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits Reviewed

Hideyuki Ichihara(Osaka Univ.),Seiji Kajihara,Kozo Kinoshita(Osaka Univ.)

8th IEEE Asian Test Symposium   147 - 152   1999.11

論理BISTにおけるスキャンイン電力 制御手法とTEG評価

加藤隆明

情報処理学会DAシンポジウム  情報処理学会

論理パスとクロックパスを考慮した実速度スキャンテスト生成手法について

李富強

電子情報通信学会DC研究会  電子情報通信学会

デジタルモニタを用いたチップ内温度電圧変動の測定について

三宅庸資

電子情報通信学会DC研究会  電子情報通信学会

FPGAのオンチップ遅延測定における温度影響補正の検討

三宅庸資

電子情報通信学会DC研究会  電子情報通信学会

リングオシレータを用いたFPGA上の完全デジタル温度モニタ

三宅庸資

情報処理学会DAシンポジウム  情報処理学会

FPGAのリングオシレータを利用した温度モニタ

三宅庸資

電子情報通信学会DC研究会  電子情報通信学会

FPGAのリングオシレータにおけるNBTI劣化量の低減と制御に関する検討

佐藤康夫

電子情報通信学会DC研究会  電子情報通信学会

FPGAにおけるオンチップ遅延測定について

安部賢太朗

電子情報通信学会DC研究会  電子情報通信学会

低電力BIST手法におけるキャプチャ電力のTEG評価

西田敏也

電子情報通信学会DC研究会  電子情報通信学会

FPGAの自己テストのための可変タイミングクロック生成

佐藤康夫

電子情報通信学会DC研究会  電子情報通信学会

データマイニング手法によるバーンインテスト結果予測の検討

野々山聡

電子情報通信学会DC研究会  電子情報通信学会

論理BISTにおけるスキャンイン電力制御回路のTEG評価について

加藤隆明

電子情報通信学会DC研究会  電子情報通信学会

FPGAにおける複数の周波数特性を実現するためのリングオシレータ構成法の検討

三宅庸資

電子情報通信学会DC研究会  電子情報通信学会

フィールドテストのための温度・電圧モニタ回路構成の検討

津森渉

電子情報通信学会DC研究会 

マルチサイクルBISTにおけるスキャン出力の電力低減手法

王森レイ

電子情報通信学会DC研究会  電子情報通信学会

フィールド高信頼化のための回路・システム機構

本人

電子情報通信学会2009年総合大会講演論文集 

論理回路の経時変化の発生箇所について

情報創成工学専攻

第60回FTC研究会 

実速度スキャンテストにおけるキャプチャセーフテスト生成手法について

情報創成工学専攻

電子情報通信学会技術研究報告 

3値論理シミュレーションにおける遅延計算について

情報システム専攻

第59回FTC研究会 

論理回路の動作環境とトランジスタの劣化特性について

情報システム工学専攻

電子情報通信学会技術研究報告 

実速度スキャンテストにおけるキャプチャ時消費電力削減手法

情報システム専攻

第58回FTC研究会 

実速度スキャンテストにおけるキャプチャ時の低消費電力テスト生成手法について

情報創成工学専攻

電子情報通信学会技術研究報告 

Per-Test X故障診断手法の診断分解能向上について

情報創成工学専攻

LSIテスティングシンポジウム2007 

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

Microelectronics Assembling and Packaging & Reverse Trade Show 2007 

LSI回路のX故障による Per-Test 故障診断手法の拡張について

情報創成工学専攻

電子情報通信学会技術研究報告　信頼性研究会 

順序回路用故障シミュレーションにおけるコンパイル方式の適用と効果について

情報システム専攻

電子情報通信学会技術研究報告 

低消費電力テストのための制約付テスト生成手法について

情報創成工学専攻

電子情報通信学会技術研究報告 

遅延テスト品質の正確な評価法とテスト生成への応用

情報創成工学専攻

第56回ＦＴＣ研究会 

LSI回路の新しいX故障によるPer-Test故障診断手法について

情報システム専攻

LSIテスティングシンポジウム 

ブロードサイドテストにおけるN回検出用テストパターンに対するX判定

情報システム専攻

電子情報通信学会技術研究報告 

コンパイル方式とイベント駆動方式を用いた故障シミュレーションの高速化について

情報システム専攻

第55回ＦＴＣ研究会 

フルスキャン順序回路用2パターンテストに対するドントケア判定

情報システム専攻

情報処理学会 ＤＡシンポジウム 2006 

テスト生成における間接含意の効率的な生成方法

電子情報通信学会VLD研究会技術研究報告 

ブロードサイド方式におけるパス長を考慮した遷移故障用テストパターン生成について

情報創成工学専攻

電子情報通信学会技術研究報告 

ブロードサイドテストにおける高品質テストパターンの生成について

電子情報工学科

第54回ＦＴＣ研究会 

スキャンテストにおけるキャプチャ時の低消費電力化に効果的なテスト集合変更について

情報創成工学専攻

電子情報通信学会技術研究報告 

故障診断のための観測性の定量化について

情報システム専攻

LSIテスティングシンポジウム2005 

X故障モデルに対する故障シミュレーションの効率化について

情報創成工学専攻

第53回ＦＴＣ研究会 

縮退故障用テストパターンのブリッジ故障検出率向上手法について

情報システム専攻

情報処理学会 ＤＡシンポジウム 2005 

SoCにおけるブロードキャストスキャンテスト効率化手法について

情報システム専攻

第53回ＦＴＣ研究会 

ディレイ品質を予測する統計的品質モデル

半導体露光学研究センター　浜田周治

電子情報通信学会技術研究報告 

超微細ＬＳＩのパス遅延故障に対するテスト圧縮法について

本人

電子情報通信学会技術研究報告 

順序回路に対するテスト系列中のドントケア値発見とテスト圧縮・消費電力削減への応用について

愛媛大　樋上喜信

電子情報通信学会技術研究報告 

スキャンテストにおけるキャプチャ時の消費電力削減を考慮したテスト生成

第52回ＦＴＣ研究会 

タイミングを考慮した統計的遅延品質評価方法

半導体理工学研究センター　浜田周治

第52回ＦＴＣ研究会 

故障診断のための観測性の定量化について

情報システム専攻　豊田直哉

電子情報通信学会技術研究報告 

入力ベクトルからの信号値を正当化する最小キューブ抽出

本人

電子情報通信学会技術研究報告 

スキャン極性調節とピンポイントテスト変換によるテスト圧縮

情報システム専攻　土井康稔

電子情報通信学会技術研究報告 

X故障モデルを用いたPer-Test故障診断手法について

本人

LSIテスティングシンポジウム2004 

X故障モデルを用いたSLAT故障診断手法について

情報システム専攻　三好勅元

情報処理学会 ＤＡシンポジウム 

トランジスタの動作領域を考慮したデジタル回路のテストと解析

情報システム専攻　山下善之

第51回ＦＴＣ研究会 

Random Access Scan: A Solution to test power, test data volume and test time

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values

ランレングス符号とピンポイントテストパターン変換によるテストデータ量削減

情報システム専攻　土井康稔

電子情報通信学会技術研究報告 

多重スキャンツリー設計によるテスト圧縮手法

情報システム専攻　宮瀬紘平

電子情報通信学会技術研究報告 

順序回路のテスト系列中のドントケア値発見法

愛媛大学　樋上喜信

平成１５年電気学会電子・情報・システム部門大会講演論文集 

テスト不能パス解析に基づくパス遅延故障検出効率の統計的推定について

情報システム専攻　福永昌勉

第49回ＦＴＣ研究会資料 

パス遅延故障テストにおける故障検出率の推定法

情報システム専攻　福永昌勉

電子情報通信学会 技術研究報告，DC2002-85 

スキャンツリーを用いたテストデータ量削減について

第48回ＦＴＣ研究会資料 

静的学習における効率的な間接含意の発見と保存について

電子情報通信学会 技術研究報告 VLD2002-86 

符号化技術を用いた多重スキャン回路のテストデータ量削減について

情報処理学会 研究報告 2002-SLDM-107 

ディレイテストにおけるパス選択基準とテストクオリティの評価

電子情報通信学会 FTS研究会 技術研究報告 

パス遅延故障のテストに有効なパスの選択について

第46回ＦＴＣ研究会 

BIST指向n検出TPGの提案

電子情報通信学会 技術研究報告（FTS研究会） 

論理回路のテストパターンに含まれるドントケアの判定法について

情報処理学会 システムＬＳＩ設計技術研究会 

二重検出法に基づく故障シミュレーションの高速化について

電子情報通信学会FTS研究会技術報告 

ドントケア判定と符号化によるテストデータ圧縮について

電子情報通信学会FTS研究会技術報告 

テストパターン中のドントケアの検出とその応用

第45回ＦＴＣ研究会 

部分ローテート型スキャンを用いたハイブリッドＢＩＳＴ

第45回ＦＴＣ研究会 

テストベクトル変換によるテスト時の消費電力低減手法について

情報処理学会 ＤＡシンポジウム2001 

テスト不能なパス遅延故障判定の高精度化手法について

情報処理学会 ＤＡシンポジウム2000 論文集 

ショーパスディレイ：故障モデルとテスト生成

電子情報通信学会 技術研究報告（FTS研究会） 

ショートパスディレイテスト手法

第44回ＦＴＣ研究会 

BIST指向n検出テストパターンの圧縮法

電子情報通信学会情報・システムソサイエティ大会論文講演集，情報・システム 1 

遺伝的アルゴリズムを用いたテスト圧縮について

2000年電子情報通信学会総合大会論文講演集，情報・システム 1, D-10-6 

テストパターン中のドントケアの発見手法について

2000年電子情報通信学会総合大会論文講演集, 情報・システム 1, D-10-5 

ディレイ故障を検出するBIST用テストパターン発生回路

情報処理学会 研究報告(システムＬＳＩ設計技術研究会) 

トランジション故障に対するコンパクトテストについて

第42回ＦＴＣ研究会資料 

パス遅延故障におけるパス選択とテスト生成について

電子情報通信学会 技術研究報告（フォールトトレラントシステム研究会） 

On maximizing multiple bridging fault coverage with limited number of measurement vectors for sequential circuits

第41回ＦＴＣ研究会資料 

テスト不能パス解析を用いたパス遅延故障のテスト生成について

第41回ＦＴＣ研究会資料 

含意に基づいたテスト不能パス解析の効率化について

第41回ＦＴＣ研究会資料 

ベクトルペア解析による多重縮退故障のテスト圧縮について

情報処理学会 ＤＡシンポジウム'99 論文集 

On Test Generation with a Limited Number of Tests

9th Great Lakes Symposium on VLSI 

パス遅延故障のテストにおけるパス選択手法について

電子情報通信学会 技術研究報告（フォールトトレラントシステム研究会） 

トランジション故障に対するテストパターンの極小化手法について

電子情報通信学会 技術研究報告（フォールトトレラントシステム研究会） 

An Efficient Procedure for Obtaining Indirect Implications and Its Application to Redundancy Identification

7th IEEE Asian Test Symposium 

IDDQテストにおける故障検出率の最大化について

第39回ＦＴＣ研究会資料 

故障検出システム、生産回路及びプログラム

佐藤　康夫,王森レイ,宮瀬紘平,梶原誠司

故障検出システム、取出装置、故障検出方法、プログラム及び記録媒体

佐藤康夫、梶原誠司

半導体装置、検知方法及びプログラム

佐藤康夫,梶原誠司,井上美智子,米田友和,李賢彬,三浦幸也

半導体装置、検知方法及びプログラム

佐藤康夫,梶原誠司,井上美智子,米田友和,李賢彬,三浦幸也

半導体装置、検知方法及びプログラム

佐藤康夫,梶原誠司,井上美智子,米田友和,李賢彬,三浦幸也

リング発振器

佐藤康夫,三浦幸也,梶原誠司

Ring Oscillator

Yukiya Miura, Yasuo Sato, Seiji Kajihara

生成装置、生成方法、及び、プログラム

Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato

Failure Prediction of Logic Circuits for High Field Reliability

16th IEEE Workshop on RTL and High Level Testing  2015.11  IEEE Computer Society

VLSI design and testing for enhanced systems dependability

International Workshop on Reliability Aware System Design and Test  2013.01  IEEE Computer Society

組込み自己テストによるフィールド高信頼化について

電子情報通信学会デザインガイア2012  2012.11  電子情報通信学会

Failure Prediction of Logic Circuits for High Field Reliability

International Workshop on Reliability Aware System Design and Test  2012.01  IEEE Computer Society

Asian Test Symposium  

2016.04 - 2016.11

日本信頼性学会   評議員  

2015.06

The institue of electronics, information and communication engineers (IEICE)  

2014.06 - 2018.05

The Institute of Electrical and Electronics Engineers, Inc.   Regional Liaisons  

2014.06 - 2015.05

パワーデバイス・イネーブリング協会検定委員会   検定問題審議委員  

2013.10

VLSI Design and CAD Algorithm小特集号（英文論文誌A）   編集委員  

2013.01 - 2014.01

パワーデバイス・イネーブリング協会検定委員会   検定用教科書編集委員  

2012.08 - 2013.01

The institue of electronics, information and communication engineers (IEICE)  

2012.05 - 2014.05

Euromicro Conference on Digital System Design   Program Committee Member  

2012.04

VLSI Design and CAD Algorithm小特集号（英文論文誌A）   編集委員  

2012.01 - 2013.01

The Institute of Electrical and Electronics Engineers, Inc.   Steering Committee Member  

2011.04

VLSI Design and CAD Algorithm小特集号（英文論文誌A）   編集委員  

2011.01 - 2012.01

The institue of electronics, information and communication engineers (IEICE)  

2009.05 - 2012.05

The Institute of Electrical and Electronics Engineers, Inc.   Regional Liaisons  

2008.06 - 2012.05

Journal of Electronic Testing: Theory and Applications  

2001.01