Updated on 2022/04/06

写真a

 
KAJIHARA Seiji
 
Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 11

Citation count denotes the number of citations in papers published for a particular year.

Affiliation
Executives
Laboratory
680-4 Kawazu, Iizuka-shi, Fukuoka
External link

Research Interests

  • Design and test of LSIs

Research Areas

  • Informatics / Computer system

Degree

  • Osaka University  -  Doctor of Engineering   1992.03

Biography in Kyutech

  • 2022.04
     

    Kyushu Institute of Technology   Executives  

  • 2020.04
     

    Kyushu Institute of Technology   Organization for Information Infrastructure   University Library   Director  

  • 2020.04
     

    Kyushu Institute of Technology   Organization for Information Infrastructure  

  • 2020.04
    -
    2022.03
     

    Kyushu Institute of Technology   Executives  

  • 2019.04
    -
    2020.03
     

    Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Professor  

  • 2016.04
    -
    2020.03
     

    Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering  

  • 2013.04
    -
    2019.03
     

    Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Creative Informatics   Professor  

▼display all

Academic Society Memberships

  • 2013.09   日本信頼性学会   Japan

  • 2000.04   Journal of Electronic Testing: Theory and Applications   Others

Papers

  • On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption Reviewed

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    IEICE Transactions on Information and Systems   E104D ( 6 )   816 - 827   2021.01

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  • On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test and Its Application to A Digital Sensor Reviewed International journal

    Gondo M., Miyake Y., Kato T., Kajihara S.

    Proceedings of the Asian Test Symposium   2020-November   1 - 6   2020.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS49688.2020.9301588

    Kyutacar

    Scopus

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  • Path Delay Measurement with Correction for Temperature and Voltage Variations Reviewed International journal

    Miyake Y., Kato T., Kajihara S.

    Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020   112 - 117   2020.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC-Asia51099.2020.00031

    Kyutacar

    Scopus

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  • A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips Reviewed International journal

    Kato T., Wang S., Sato Y., Kajihara S., Wen X.

    IEEE Transactions on Emerging Topics in Computing   8 ( 3 )   591 - 601   2020.07

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TETC.2017.2767070

    Kyutacar

    Scopus

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  • On-Chip Delay Measurement for Degradation Detection and Its Evaluation under Accelerated Life Test Reviewed International journal

    Miyake Y., Kato T., Kajihara S., Aso M., Futami H., Matsunaga S., Miura Y.

    Proceedings - 2020 26th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2020   2020.07

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/IOLTS50870.2020.9159717

    Kyutacar

    Scopus

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  • High-Precision PLL Delay Matrix with Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters Reviewed

    Chen P., Lan J.T., Wang R.T., My Qui N., Marquez J.C.J.S., Kajihara S., Miyake Y.

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems   28 ( 4 )   904 - 913   2020.04

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TVLSI.2019.2962606

    Scopus

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  • On-chip delay measurement for in-field test of FPGAs Reviewed International journal

    Miyake Y., Sato Y., Kajihara S.

    Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC   2019-December   130 - 137   2019.12

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/PRDC47002.2019.00043

    Kyutacar

    Scopus

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  • On-chip test clock validation using a time-to-digital converter in FPGAs Reviewed International journal

    Miyake Y., Kajihara S., Chen P.

    Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   157 - 162   2019.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Tokyo   2019.09.03  -  2019.09.05

    DOI: 10.1109/ITC-Asia.2019.00040

    Kyutacar

    Scopus

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  • A static method for analyzing hotspot distribution on the LSI Reviewed

    Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

    Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   73 - 78   2019.09

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Tokyo   2019.09.03  -  2019.09.05

    DOI: 10.1109/ITC-Asia.2019.00026

    Scopus

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  • A selection method of ring oscillators for an on-chip digital temperature and voltage sensor Reviewed International journal

    Miyake Y., Sato Y., Kajihara S.

    Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   13 - 18   2019.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Tokyo  

    DOI: 10.1109/ITC-Asia.2019.00016

    Kyutacar

    Scopus

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  • FPGA implementation of ECDSA for Blockchain Reviewed International journal

    Tachibana S., Araki S., Kajihara S., Azuchi S., Nakajo Y., Shoda H.

    2019 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2019   2019.05

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ICCE-TW46550.2019.8991918

    Kyutacar

    Scopus

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  • On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST Reviewed

    2018-October   30 - 35   2018.12

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    China   Hefei   2018.10.15  -  2018.10.17

    DOI: 10.1109/ATS.2018.00017

    Kyutacar

    Scopus

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  • Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed

    2018-October   149 - 154   2018.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS.2018.00037

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  • Good die prediction modelling from limited test items Reviewed International journal

    115 - 120   2018.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    China   Harbin   2018.08.15  -  2018.08.17

    DOI: 10.1109/ITC-Asia.2018.00030

    Scopus

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  • Scan chain grouping for mitigating ir-drop-induced test data corruption Reviewed

    140 - 145   2018.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS.2017.37

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  • Analysis and mitigation or IR-Drop induced scan shift-errors Reviewed

    2017-December   1 - 8   2017.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/TEST.2017.8242055

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  • On the effects of real time and contiguous measurement with a digital temperature and voltage sensor Reviewed

    125 - 130   2017.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC-ASIA.2017.8097126

    Kyutacar

    Scopus

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  • A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST Reviewed

    203 - 208   2016.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS.2016.59

    Kyutacar

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  • Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed

    19 - 24   2016.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS.2016.49

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  • Logic-path-and-clock-path-aware at-speed scan test generation Reviewed

    E99A ( 12 )   2310 - 2319   2016.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1587/transfun.E99.A.2310

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  • Temperature and voltage measurement for field test using an Aging-Tolerant monitor Reviewed

    24 ( 11 )   3282 - 3295   2016.11

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TVLSI.2016.2540654

    Kyutacar

    Scopus

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  • Physical Power Evaluation of Low Power Logic-BIST Scheme using TEG Chip Reviewed

    Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi

    ASP Journal of Low Power Electronics   11 ( 4 )   1 - 13   2015.12

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1166/jolpe.2015.1410

    Scopus

  • Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretcht Reviewed

    Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

    IEEE Asian Test Symposium   103 - 108   2015.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    India   Mumbai   2015.11.22  -  2015.11.25

    DOI: 10.1109/ATS.2015.25

    Scopus

  • Identification of High Power Consuming Areas with Gate Type and Logic Level Information Reviewed

    Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

    IEEE European Test Symposium   Paper9.1-1 (6 pages)   2015.05

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Romania   Cluj-Napoca   2015.05.25  -  2015.05.29

    DOI: 10.1109/ETS.2015.7138773

    Scopus

  • Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA Reviewed

    Yasuo Sato,Masafumi Monden, Yousuke Miyake, Seiji Kajihara

    IEEE Pacific Rim International Symposium on Dependable Computing   59 - 67   2014.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Singapore   Singapore   2014.11.19  -  2014.11.21

    DOI: 10.1109/PRDC.2014.16

    Kyutacar

    Scopus

  • Power Evaluation of a Low Power Logic BIST Scheme Using TEG Chip Reviewed

    Senling Wang, Toshiya Nishida, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi

    IEEE Workshop on RTL and High Level Testing   1 - 6   2014.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    China   Hangzhou   2014.11.19  -  2014.11.20

  • Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test Reviewed

    Yousuke Miyake,Yasuo Sato,Seiji Kajihara,Yukiya Miura

    IEEE Asian Test Symposium   156 - 161   2014.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    China   Hangzhou   2014.11.16  -  2014.11.19

    DOI: 10.1109/ATS.2014.38

    Kyutacar

    Scopus

  • An On-Chip Digital Environment Monitor for Field Test Invited Reviewed

    Seiji Kajihara,Yousuke Miyake,Yasuo Sato,Yukiya Miura

    IEEE Asian Test Symposium   254 - 257   2014.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    China   Hangzhou   2014.11.16  -  2014.11.19

    DOI: 10.1109/ATS.2014.54

    Scopus

  • Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories Reviewed

    Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara

    IEEE Asian Test Symposium   16 - 19   2014.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    China   Hangzhou   2014.11.16  -  2014.11.19

    DOI: 10.1109/ATS.2014.41

    Scopus

  • On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed

    Akihiro Tomita,Xiaoqing Wen,Yasuo Sato,Seiji Kajihara,Kohei Miyase,Stefan Holst,Patrick Girard,Mohammad Tehranipoor,Laung-Terng Wan

    IEICE Transactions on Information and Systems   E97-D ( 10 )   2706 - 2718   2014.10

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1587/transinf.2014EDP7039

    Scopus

    CiNii Article

  • Highly Accurate Delay Time Measurement by an On-Chip Circuit

    Yukiya Miura,Yasuo Sato,Seiji Kajihara

    Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   451 - 451   2013.12

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    Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (other)

  • Logging and Using Field Test Data for Improved Dependability

    Seiji Kajihara, Satoshi Ohtake

    Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   518 - 518   2013.12

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (other)

  • Field Test Role for Danger of Physical Degradation

    Yasuo Sato,Seiji Kajihara

    Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   461 - 461   2013.12

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    Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (other)

  • A Flexible Temperature and Voltage Monitor for Field Test Reviewed

    Yousuke Miyake,Yasuo Sato,Seiji Kajihara,Yukiya Miura

    IEEE Workshop on RTL and High Level Testing   Paper Ⅲ.3.F   2013.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Yi-Lan   2013.11.21  -  2013.11.22

  • A Stochastic Model for NBTI-Induced LSI Degradation in Field Reviewed

    Yasuo Sato,Seiji Kajihara

    IEEE Asian Test Symposium   183 - 188   2013.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Yi-Lan   2013.11.18  -  2013.11.21

    DOI: 10.1109/ATS.2013.42

    Scopus

  • On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed

    Akihiro TOMITA, Xiaoqing WEN, Yasuo SATO, Seiji KAJIHARA, Patrick GIRARD, Mohammad TEHRANIPOOR, Laung-Terng WANG

    IEEE Asian Test Symposium   19 - 24   2013.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Yi-Lan   2013.11.18  -  2013.11.21

    DOI: 10.1109/ATS.2013.14

    Scopus

  • Search Space Reduction for Low-Power Test Generation Reviewed

    Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

    IEEE Asian Test Symposium   171 - 176   2013.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Yi-Lan   2013.11.18  -  2013.11.21

    DOI: 10.1109/ATS.2013.40

    Scopus

  • A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Reviewed

    Kohei Miyase,Ryouta Sakai,Xiaoqing Wen,Masao Aso,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara

    IEICE Transactions on Information and Systems   E96-D ( 9 )   2003 - 2011   2013.09

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1587/transinf.E96.D.2003

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    CiNii Article

  • Scan-Out Power Reduction for Logic BIST Reviewed

    Senling Wang,Yasuo Sato,Seiji Kajihara,Kohei Miyase

    IEICE Transactions on Information and Systems   E96-D ( 9 )   2012 - 2020   2013.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1587/transinf.E96.D.2012

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    CiNii Article

  • LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing Reviewed

    Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang

    IEEE Design & Test of Computers   30 ( 4 )   60 - 70   2013.08

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/MDT.2012.2221152

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  • Controllability Analysis of Local Switching Activity for Layout Design Reviewed

    Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

    Workshop on Design and Test Methodologies for Emerging Technologies   Paper 1   2013.05

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    Language:English   Publishing type:Research paper (other academic)

    France   Avignon   2013.05.31  -  2013.06.01

  • On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression Reviewed

    Kazunari Enokimoto,Xiaoqing Wen,Kohei Miyase,J.-L. Huang,Seiji Kajihara, Laung-Terng Wang

    International Conference on VLSI Design   279 - 284   2013.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    インド   プネー   2013.01.05  -  2013.01.10

    DOI: 10.1109/VLSID.2013.201

    Scopus

  • 5.4 Field Test Role for Danger of Physical Degradation(5. Time-Dependent Degradation in Device Characteristics,<Special Survey>Dependable VLSI System)

    SATO Yasuo, KAJIHARA Seiji

    The Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   2013.01

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    Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (scientific journal)

    DOI: 10.11348/reajshinrai.35.8_461

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/110009688252

  • 4.6 Highly Accurate Delay Time Measurement by an On-Chip Circuit(4. Variations in Device Characteristics,<Special Survey>Dependable VLSI System)

    MIURA Yukiya, SATO Yasuo, KAJIHARA Seiji

    The Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   2013.01

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    Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (scientific journal)

    DOI: 10.11348/reajshinrai.35.8_451

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/110009688247

  • 10.4 Logging and Using Field Test Data for Improved Dependability(10. Future and / or Un-Identified Problems,<Special Survey>Dependable VLSI System)

    KAJIHARA Seiji, OHTAKE Satoshi

    The Journal of Reliability Engineering Association of Japan ( Reliability Engineering Association of Japan )   35 ( 8 )   2013.01

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    Authorship:Lead author   Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (scientific journal)

    DOI: 10.11348/reajshinrai.35.8_513

    CiNii Article

    Other Link: https://ci.nii.ac.jp/naid/110009688280

  • Estimation of the Amount of Don't-Care Bits in Test Vectors Reviewed

    Kohei Miyase, Xiaoqing Wen, Seiji Kajihara

    IEEE Workshop on RTL and High Level Testing   Paper 2.3   2012.11

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    Language:English   Publishing type:Research paper (other academic)

    日本   新潟   2012.11.22  -  2012.11.23

  • A Scan-Out Power Reduction Method for Multi-Cycle BIST Reviewed

    Senling Wang,Yasuo Sato,Kohei Miyase,Seiji Kajihara

    IEEE Asian Test Symposium   272 - 277   2012.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    日本   新潟   2012.11.19  -  2012.11.22

    DOI: 10.1109/ATS.2012.50

    Kyutacar

    Scopus

  • Low Power BIST for Scan-Shift and Capture Power Reviewed

    Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara

    IEEE Asian Test Symposium   173 - 178   2012.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    日本   新潟   2012.11.19  -  2012.11.22

    DOI: 10.1109/ATS.2012.27

    Kyutacar

    Scopus

  • DART: Dependable VLSI Test Architecture and Its Implementation Reviewed

    Yasuo Sato,Seiji Kajihara,Tomokazu Yoneda,Kazumi Hatayama,Michiko Inoue,Yukiya Miura,Satoshi Ohtake,Takumi Hasegawa,Motoyuki Sato,Kotaro Shimamura

    IEEE International Test Conference   Paper 15.2   2012.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    アメリカ   アナハイム   2012.11.05  -  2012.11.08

    DOI: 10.1109/TEST.2012.6401581

    Kyutacar

    Scopus

  • On Pinpoint Capture Power Management in At-Speed Scan Test Generation Reviewed

    Xiaoqing Wen, Yuichiro Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

    IEEE International Test Conference   2012.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    アメリカ   アナハイム   2012.11.05  -  2012.11.08

    DOI: 10.1109/TEST.2012.6401548

    Scopus

  • A Failure Prediction Strategy for Transistor Aging Reviewed

    Hyunbean Yi,Tomokazu Yoneda,Michiko Inoue,Yasuo Sato,Seiji Kajihara,Hideo Fujiwara

    IEEE Transactions on VLSI Systems   20 ( 11 )   1951 - 1959   2012.11

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TVLSI.2011.2165304

    Scopus

  • On-chip Temperature and Voltage measurement for Field Testing Reviewed

    Yukiya Miura,Yasuo Sato,Yousuke Miyake,Seiji Kajihara

    IEEE European Test Symposium   Paper 15.2   2012.05

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    Language:English   Publishing type:Research paper (scientific journal)

    France   Annecy   2012.05.28  -  2015.06.01

    DOI: 10.1109/ETS.2012.6233035

    Scopus

  • A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits Reviewed

    Kohei Miyase,Masao Aso,Ryou Ootsuka,Xiaoqing Wen,Hiroshi Furukawa,Yuta Yamato,Kazunari Enokimoto,Seiji Kajihara

    IEEE VLSI Test Symposium   197 - 202   2012.04

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    Language:English   Publishing type:Research paper (international conference proceedings)

    アメリカ   Hawaii   2012.04.23  -  2012.04.26

    DOI: 10.1109/VTS.2012.6231102

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  • Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling Reviewed

    K. Miyase, Y. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard, A. Virazel

    IEEE 20th Asian Test Symposium   90 - 95   2011.11

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    India   Dehli   2011.11.20  -  2011.11.23

    DOI: 10.1109/ATS.2011.35

    Kyutacar

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  • Multi-Cycle Test with Partial Observation on Scan-Based BIST Structure, "jointly worked" Reviewed

    Yasuo Sato, Seiji Kajihara, Hiaso Yamaguchi, Makoto Matsuzono

    IEEE 20th Asian Test Symposium   54 - 59   2011.11

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    India   Dehli   2011.11  -  2011.11

    DOI: 10.1109/ATS.2011.34

    Kyutacar

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  • A novel scan segmentation design method for avoiding shift timing failures in scan testing Reviewed

    Yuta Yamato,Xiaoqing Wen, Michael A. Kochte, Seiji Kajihara, Kohei Miyase, Laung-Terng Wang

    IEEE International Test Conference   Paper 12.1   2011.09

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    アメリカ   Anaheim   2011.09.20  -  2011.09.22

    DOI: 10.1109/TEST.2011.6139162

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  • SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures Reviewed

    Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato,Kazunari Enokimoto, H.-J. Wunderlich

    IEEE Intl. Symp. on Low Power Electronics and Design   33 - 38   2011.08

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    日本   福岡   2011.08.01  -  2011.08.03

    DOI: 10.1109/ISLPED.2011.5993600

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  • Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing Reviewed

    51. Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

    IEICE Transactions on Information and Systems   E94-D ( 6 )   1216 - 1226   2011.06

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    DOI: 10.1587/transinf.E94.D.1216

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  • Transition-time-relation based capture-safety checking for at-speed scan test generation Reviewed

    895 - 898   2011.05

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    Other Link: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79957551358&origin=inward

  • Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing Reviewed

    Xiaoqing Wen,Kazunari Enokimoto,Kohei Miyase, Yuta Yamato, Michael A. Kochte,Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor

    IEEE VLSI Test Symposium   166 - 171   2011.05

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    アメリカ   Dana Point   2011.05.02  -  2011.05.04

    DOI: 10.1109/VTS.2011.5783778

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  • A GA-based x-filling for reducing launch switching activity toward specific objectives in at-speed scan testing Reviewed

    Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

    IEICE Transactions on Information and Systems   E94-D ( 4 )   833 - 840   2011.04

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    DOI: 10.1587/transinf.E94.D.833

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  • Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation Reviewed

    Kohei Miyase,Xiaoqing Wen,Masao Aso,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara

    Design Automation and Test in Europe   895 - 898   2011.03

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    France   2011.03  -  2011.03

  • A Pattern Partitioning Algorithm for Field Test Reviewed

    Senling Wang,Seiji Kajihara,Yasuo Sato,Xiaoxin Fan,Sudhakar M Reddy

    IEEE International Workshop on Reliability Aware System Design and Test   31 - 36   2011.01

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    India   Chennai   2011.01.07  -  2011.01.08

  • CAT (Critical-Area-Targeted): A new paradigm for reducing yield loss risk in at-speed scan testing Reviewed

    27 ( 1 )   197 - 202   2010.12

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    DOI: 10.1149/1.3360619

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  • X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme Reviewed

    Kohei Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara

    IEEE Workshop on RTL and High Level Testing   125 - 129   2010.12

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    China   上海   2010.12  -  2010.12

  • Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver Reviewed

    Kohei Miyase,Michael A. Kochte,Xiaoqing Wen,Seiji Kajihara,Hans-Joachim Wunderlich

    International Workshop on Defect and Data Driven Testing   2010.11

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    2010.11  -  2010.11

  • On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test Reviewed

    Seiji Kajihara,Makoto Matsuzono,Hisato Yamaguchi,Yasuo Sato,Kohei Miyase,Xiaoqing Wen

    International Symposium on Communications and Information Technologies   723 - 726   2010.10

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    東京   2010.10.26  -  2010.10.29

    DOI: 10.1109/ISCIT.2010.5665084

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  • On Delay Test Quality for Test Cubes Reviewed

    S. Oku,S. Kajihara,Y. Sato,K. Miyase,X. Wen

    IPSJ Transactions on System LSI Design Methodology   3   283 - 291   2010.08

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    DOI: 10.2197/ipsjtsldm.3.283

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  • A Study of Capture-Safe Test Generation Flow for At-Speed Testing Reviewed

    Kohei Miyase,Xiaoqing Wen,Seiji Kajihara,Yuta Yamato,Atsushi Takashima,Hiroshi Furukawa,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Kewal K. Saluja

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E93-A ( 7 )   1309 - 1318   2010.07

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    DOI: 10.1587/transfun.E93.A.1309

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  • Aging test strategy and adaptive test scheduling for soc failure prediction Reviewed

    Hyunbean Yi,Tomokazu Yoneda,Michiko Inoue,Yasuo Sato,Seiji Kajihara,Hideo Fujiwara

    IEEE International On-Line Testing Symposium   21 - 26   2010.07

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    Greece   Corfu Island   2010.07.05  -  2010.07.07

    DOI: 10.1109/IOLTS.2010.5560239

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  • On Estimation of NBTI-Induced Delay Degradation Reviewed

    M. Noda,S. Kajihara,Y. Sato,K. Miyase,X. Wen,Y. Miura

    IEEE European Test Symposium   107 - 111   2010.05

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    Czech Republic   Prague   2010.05  -  2010.05

    DOI: 10.1109/ETSYM.2010.5512772

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  • High Launch Switching Activity Reduction in At- Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Reviewed

    Kohei Miyase,Xiaoqing Wen,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara,Patrick Girard,Laung-Terng Wang,Mohammad Tehranipoor

    IEICE Transactions on Information and Systems   E93-D ( 1 )   2 - 9   2010.01

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  • On Calculation of Delay Range in Fault Simulation for Test Cubes Reviewed

    Seiji KAJIHARA,Shinji OKU,Kohei MIYASE,Xiaoqing WEN,Yasuo SATO

    International Symposium on VLSI Design, Automation, and Test   64 - 67   2009.04

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    Taiwan   新竹   2009.04  -  2009.04

  • On Delay Calculation in 3-valued Fault Simulation Reviewed

    Shinji OKU,Seiji KAJIHARA,Kohei MIYASE,Xiaoqing WEN,Yasuo SATO

    IEEE Workshop on RTL and High Level Testing   2008.11

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    札幌市   2008.11.27  -  2008.11.28

  • CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing Reviewed

    H. Furukawa,X. Wen,K. Miyase,Y. Yamato,S. Kajihara,P. Girard,L. -T. Wang,M. Tehranipoor

    Asian Test Symposium   397 - 402   2008.11

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    札幌市   2008.11.24  -  2008.11.27

  • Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification Reviewed

    Kohei Miyase,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Yuta Yamato,Hiroshi Furukawa,Xiaoqing Wen,Seiji Kajihara

    IEEE/ACM International Conference on Computer-Aided Design   52 - 58   2008.11

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    USA   San Jose, CA   2008.11.10  -  2008.11.13

  • GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing Reviewed

    Yuta Yamato,Xiaoqing Wen,Kohei Miyase,Hiroshi Furukawa,Seiji Kajihara

    IEEE International Workshop on Defect and Data Driven Testing   2008.10

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    USA   Santa Clara, CA   2008.10.30  -  2008.10.31

  • Estimation of Delay Test Quality and Its Application to Test Generation Reviewed

    Seiji Kajihara,Shohei Morishima,Masahiro Yamamoto,Xiaoqing Wen,Masayasu Fukunaga,Kazumi Hatayama,Takashi Aikyo

    IPSJ Transactions on System LSI Design Methodology   2008.08

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  • Diagnosis of Realistic Defects Based on the X-Fault Model Reviewed

    Ilia Polian,Yusuke Nakamura,Piet Engelke,Stefan Spinner,Kohei Miyase,Seiji Kajihara,Bernd Becker,Xiaoqing Wen

    IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems   2008.04

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    Slovakia   Bratislava   2008.04.16  -  2008.04.18

  • Low-Capture-Switching- Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing Reviewed

    Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja

    Journal of Electronic Testing:Theory and Applications   2008.04

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  • Aging test strategy and adaptive test scheduling for soc failure prediction Reviewed

    Hyunbean Yi,Tomokazu Yoneda,Michiko Inoue,Yasuo Sato,Seiji Kajihara,Hideo Fujiwara

    IEEE International On-Line Testing Symposium   21 - 26   2008.04

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    2008.04  -  2008.04

  • A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Reviewed

    Yuta Yamato,Yusuke Nakamura,Kohei Miyase,Xiaoqing Wen,Seiji Kajihara

    IEICE Transactions on Information and Systems   E91-D   667 - 674   2008.03

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  • On Detection of Bridge Defects with Stuck-at Tests Reviewed

    Kohei Miyase,Kenta Terashima,Xiaoqing Wen,Seiji Kajihara,Sudhakar M. Reddy

    IEICE Transactions on Information and Systems   E91-D ( 3 )   683 - 689   2008.03

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  • Estimation of Delay Test Quality and Its Application to Test Generation Reviewed

    Seiji Kajihara,Shohei Morishima,Masahiro Yamamoto,Xiaoqing Wen,Masayasu Fukunaga,Kazumi Hatayama,Takashi Aikyo

    IEEE/ACM International Conference on Computer-Aided Design   413 - 417   2007.11

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    USA   San Jose, CA   2007.11.05  -  2007.11.08

  • A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing Reviewed

    Xiaoqing Wen,Kohei Miyase,Seiji Kajihara,Tatsuya Suzuki,Yuta Yamato,Patrick Girard,Yuji Ohsumi,Laung-Terng Wang

    International Test Conference   10 - 10   2007.10

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    USA   Santa Clara, CA   2007.10.23  -  2007.10.25

  • A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set Reviewed

    Kohei Miyase,Xiaoqing. Wen,Seiji. Kajihara,Masahiro Yamamoto,Hiroshi Furukawa

    2007 IEEE International Workshop on Current & Defect Based Testing   51 - 56   2007.10

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    USA   Santa Clara, CA   2007.10  -  2007.10

  • A Novel ATPG Method for Capture Power Reduction during Scan Testing Reviewed

    Xiaoqing Wen,Seiji Kajihara,Kohei Miyase,Tatsuya Suzuki,Kewal K. Saluja,Laung-Terng Wang,Kozo Kinoshita

    IEICE Transactions on Information and Systems   E90-D ( 9 )   1398 - 1405   2007.09

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  • Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing Reviewed

    Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,Seiji Kajihara,Yuji Ohsumi,Kewal. K. Saluja

    ACM/IEEE Design Automation Conference   527 - 532   2007.06

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    USA   San Diego   2007.06.04  -  2007.06.08

  • On Finding Don't Cares in Test Sequences for Sequential Circuits Reviewed

    Yoshinobu Higami,Seiji Kajihara,Irith Pomeranz,Shin-ya Kobayashi,Yuzo Takamatsu

    IEICE Trans. Info. & Syst.   E89-D ( 11 )   2748 - 2755   2006.11

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  • An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits Reviewed

    Xiaoqing Wen ,Yuta Yamato,Kohei Miyase,Seiji Kajihara,Hiroshi Furukawa,Laung-Terng Wang ,Kewal K. Saluja,Kozo Kinoshita

    6th IEEE Workshop on RTL and High Level Testing   55 - 60   2006.11

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    福岡市   2006.11  -  2006.11

  • A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation Reviewed

    Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,Yuta Yamato,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja

    International Conference on Computer Design   251 - 258   2006.10

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    America   San Jose, CA   2006.10  -  2006.10

  • A Framework of High-quality Transition Fault ATPG for Scan Circuits Reviewed

    Seiji Kajihara,Shohei Morishima,Akane Takuma,Xiaoqing Wen,Toshiyuki Maeda,Shuji Hamada,Yasuo Sato

    International Test Conference   2006.10

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    America   Santa Clara, CA   2006.10  -  2006.10

  • Hybrid fault simulation with compiled and event-driven methods Reviewed

    Kenjiro Taniguchi,Hideo Fujii,Seiji Kajihara,Xiaoqing Wen

    IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology   240 - 243   2006.09

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    Tunisia   Tunis   2006.09  -  2006.09

  • 統計的遅延品質モデル(SDQM)のフィージビリティ評価 Reviewed

    佐藤康夫,浜田周治,前田敏行,高取厚夫,野津山泰行,梶原誠司

    電子情報通信学会論文誌 D-I   J89-D-I ( 8 )   1717 - 1728   2006.08

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  • a Reviewed

    47 ( 6 )   1648 - 1657   2006.06

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  • A New Method for Low-Capture-Power Test Generation for Scan Testing Reviewed

    Xiaoqing Wen,Yoshiyuki Yamashita,Shohei Morishima,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

    IEICE Trans. Info. & Syst.   E89-D ( 5 )   1679 - 1686   2006.05

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  • A New ATPG Method for Efficient Capture Power Reduction During Scan Testing Reviewed

    Xiaoqing Wen,Seiji Kajihara,Kohei Miyase,Tatsuya Suzuki,Kewal K. Saluja,Laung-Terng Wang,Khader S. Abdel-Hafez,Kozo Kinoshita

    IEEE VLSI Test Symposium   58 - 63   2006.05

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    America   Berkley, CA   2006.05  -  2006.05

  • A statistical quality model for delay testing Reviewed

    Yasuo Sato,Shuji Hamada,Toshiyuki Maeda,Atsuo Takatori,Seiji Kajihara

    IEICE Trans. ELECTRONICS   E89-C ( 3 )   349 - 355   2006.03

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  • A dynamic test compaction procedure for high-quality path delay testing Reviewed

    Masayasu Fukunaga,Seiji Kajihara,Xiaoqing Wen,Toshiyuki Maeda,Shuji Hamada,Yasuo Sato

    Asia and South Pacific Design Automation Conference   348 - 353   2006.01

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    横浜市   2006.01.24  -  2006.01.27

  • On Improving Defect Coverage of Stuck-at Fault Tests Reviewed

    K. Miyase,K. Terashima,S. Kajihara,X. Wen,S.M. Reddy

    Asian Test Symposium   216 - 221   2005.12

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    India   Kolkata   2005.12.18  -  2005.12.21

  • Low-Capture-Power Test Generation for At-Speed Scan Testing Reviewed

    Xiaoqing Wen,Yoshiyuki Yamashita,Shohei Morishima,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

    International Test Conference   2005.11

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    America   Austin   2005.11.06  -  2005.11.11

  • Invisible delay quality - SDQM model lights up what could not be seen Reviewed

    Yasuo Sato,Shuji Hamada,Toshiyuki Maeda,Atsuo Takatori,Yasuyuki Nozuyama,Seiji Kajihara

    International Test Conference   2005.11

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    America   Austin   2005.11.06  -  2005.11.11

  • Three-Stage Compression Approach to Reduce Test Data Volume and Testing Time for IP Cores in SOCs Reviewed

    Lei Li,Krishnendu Chakrabarty,Seiji Kajihara,Shivakumar Swaminathan

    IEE Proc. Computers & Digital Technique   152 ( 6 )   704 - 712   2005.11

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  • On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis Reviewed

    Masayasu Fukunaga,Seiji Kajihara,Sadami Takeoka

    IEICE Trans. Info. and Syst.   E88-D ( 7 )   1671 - 1677   2005.07

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  • On Quantifying Observability for Fault Diagnosis of VLSI Circuits Reviewed

    Naoya Toyota,Seiji Kajihara,Xiaoqing Wen,Masaru Sanada

    5th IEEE Workshop on RTL and High Level Testing   192 - 197   2005.07

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    China   ハルピン   2005.07  -  2005.07

  • A Method for Low-Capture-Power At-Speed Scan Test Generation Reviewed

    Xiaoqing Wen,Yoshiyuki Yamashita,Shohei Morishima,Seiji Kajihara,L.-T. Wang,Kewal. K. Saluja,Kozo Kinoshita

    5th IEEE Workshop on RTL and High Level Testing,   40 - 49   2005.07

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    China   ハルピン   2005.07  -  2005.07

  • Path Delay Test Compaction with Process Variation Tolerance Reviewed

    Seiji Kajihara,Masayasu Fukunaga,Xiaoqing Wen,Toshiyuki Maeda,Shuji Hamada,Yasuo Sato

    Design Automation Conference   845 - 850   2005.06

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    America   Anaheim   2005.06.13  -  2005.06.17

  • On the Extraction of a Minimum Cube to Justify Signal Line Values Reviewed

    Kohei Miyase,Shinobu Nagayama,Seiji Kajihara,Xiaoqing Wen,Sudhakar M. Reddy

    European Test Symposium   79 - 84   2005.05

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    Estonia   Tallinn   2005.05.22  -  2005.05.25

  • On Low-Capture-Power Test Generation for Scan Testing Reviewed

    Xiaoqing Wen,Yoshiyuki Yamashita,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

    VLSI Test Symposium   265 - 270   2005.05

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    America   Palm Springs   2005.05.01  -  2005.05.05

  • 中間故障電圧値を扱う故障シミュレーションの高速化について Reviewed

    温暁青,梶原誠司,玉本英夫,Kewal K. Saluja,樹下行三

    電子情報通信学会論文誌 D-I   J88-D-I ( 4 )   906 - 907   2005.04

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  • On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Reviewed

    Xiaoqing WEN,Seiji KAJIHARA,Hideo TAMAMOTO,Kewal K. SALUJA,and Kozo KINOSHITA

    IEICE Trans. Info. and Syst   E88-D ( 4 )   703 - 710   2005.04

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  • Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation Reviewed

    Yasumi Doi,Seiji Kajihara,Xiaoqing Wen,Lei Li,Krishnendu Chakrabarty

    Asia and South Pacific Design Automation Conference   59 - 64   2005.01

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    China   上海   2005.01  -  2005.01

  • Evaluation of Statistical Delay Quality Model Reviewed

    Yasuo Sato,Shuji Hamada,Toshiyuki Maeda,Atsuo Takatori,Seiji Kajihara

    Asia and South Pacific Design Automation Conference   305 - 310   2005.01

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    China   上海   2005.01  -  2005.01

  • Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores Reviewed

    Lei Li,Krishnendu Chakrabarty,Seiji Kajihara,Shivakumar Swaminathan

    International Conference on VLSI Design   53 - 58   2005.01

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    インド   2005.01  -  2005.01

  • Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction Reviewed

    Yoshinobu Higami,Seiji Kajihara,Shin-ya Kobayashi,Yuzo Takamatsu

    Asian Test Symposium   46 - 49   2004.11

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    台湾   2004.11  -  2004.11

  • On Per-Test Fault Diagnosis Using the X-Fault Model Reviewed

    Xiaoqing Wen,Tokiharu Miyoshi,Seiji Kajihara,Laung-Terng Wang,Kewal K. Saluja,Kozo Kinoshita

    International Conference on Computer-Aided Design   633 - 640   2004.11

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    アメリカ   San Jose   2004.11  -  2004.11

  • On extraction of a cube with the minimum number of literals from a given input vector Reviewed

    Kohei Miyase,Shinobu Nagayama,Seiji Kajihara,Xiaoqing Wen,Sudhakar M. Reddy

    Workshop on RTL and High Level Testing   71 - 76   2004.11

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    2004.11  -  2004.11

  • On Estimation of Fault Efficiency for Path Delay Faults Reviewed

    Masayasu Fukunaga,Seiji Kajihara,Sadami Takeoka

    Asian Test Symposium   64 - 67   2004.11

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    China   西安   2004.11  -  2004.11

  • Multiple Scan Tree Design with Test Vector Modification Reviewed

    Kohei Miyase,Seiji Kajihara,Sudhakar M. Reddy

    Asian Test Symposium   76 - 81   2004.11

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    台湾   2004.11  -  2004.11

  • A Method to Find Don't Care Values in Test Sequences for Sequential Circuits Reviewed

    Yoshinobu Higami,Seiji Kajihara,Shinya Kobayashi,Yuzo Takamatsu,Irith Pomeranz

    International Conference on Computer Design   397 - 399   2004.10

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    アメリカ   2004.10  -  2004.10

  • Scan Tree Design: Test compression with Test Vector Modification Reviewed

    Kohei Miyase,Seiji Kajiahra

    44 ( 5 )   1270 - 1278   2004.05

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  • Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values Reviewed

    Seiji Kajihara,Kewal K. Saluja,Sudhakar M. Reddy

    European Test Symposium(Formal proceedings)   108 - 113   2004.05

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    フランス   2004.05  -  2004.05

  • Efficient Space/Time Compression of Test Data for Multiple Scan Chain Designs Reviewed

    Lei Li,Krishnendu Chakrabarty,Seiji Kajihara,Shivakumar Swaminathan

    European Test Symposium(Informal Digest of Papers)   265 - 266   2004.05

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    フランス   2004.05  -  2004.05

  • Test Data Compression Using Don't-Care Identification and Statistical Encoding Reviewed

    Seiji Kajihara,Kenjiro Taniguchi,Kohei Miyase,Irith Pomeranz,Sudhakar M. Reddy

    IEICE Trans. Info. and Syst.,   E87-D ( 3 )   544 - 550   2004.03

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  • 論理回路に対するテストコスト削減法 -テストデータ量およびテスト実行時間の削減- Reviewed

    樋上喜信,梶原誠司,市原英行,高松雄三

    電子情報通信学会論文誌D-I   J87-D-I ( 3 )   291 - 307   2004.03

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    主要雑誌 代表的研究業績

  • XID: Don't Care Identification of Test Patterns for Combinational Circuits Reviewed

    Kohei Miyase,Seiji Kajihara

    IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems   23 ( 2 )   321 - 326   2004.02

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  • Random Access Scan: A Solution to test power, test data volume and test time Reviewed

    Dong Hyun Baik,Seiji Kajihara,Kewal K. Saluja

    International Conference on VLSI Design   883 - 888   2004.01

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    インド   2004.01  -  2004.01

  • Evaluation of Delay Testing based on Path Selection Reviewed

    Masayasu Fukunaga,Seiji Kajihara,Sadami Takeoka,Shinichi Yoshimura

    IEICE Trans. Fundamentals.   E86-A ( 12 )   3208 - 3210   2003.12

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  • Optimal Scan Tree Construction with Test Vector Modification for Test Compression Reviewed

    Kohei Miyase,Seiji Kajihara

    Asian Test Symposium   136 - 141   2003.11

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    China   西安   2003.11  -  2003.11

  • On Test Data Volume Reduction for Multiple Scan Chain Designs Reviewed

    Sudhakar M. Reddy,Kohei Miyase,Seiji Kajihara,Irith Pomeranz

    ACM Transactions on Design Automation of Electronic Systems   8 ( 4 )   460 - 469   2003.10

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  • On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume Reviewed

    Seiji Kajihara,Yasumi Doi,Lei Li,Krishnendu Chakrabarty

    International Conference on Computer Design   387 - 392   2003.10

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    アメリカ   San Jose   2003.10  -  2003.10

  • On Selecting Testable Paths in Scan Designs Reviewed

    Yun Shao,Sudhakar M.Reddy,Irith Pomeranz,Seiji Kajihara

    Journal of Electronic Testing Theory and Applications   19 ( 4 )   447 - 456   2003.08

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  • On Effective Criterion of Path Selection for Delay Testing Reviewed

    Asia and South Pacific Design Automation Conference   757 - 762   2003.01

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    北九州市   2003.01.21  -  2003.01.24

  • Test data volume reduction using statistical encoding for multiple scan chain designs Reviewed

    Kenjiro TANIGUCHI,Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ of Iowa)

    3rd IEEE Workshop on RTL ATPG & DFT   106 - 109   2002.11

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    Guam, USA   2002.11.21  -  2002.11.22

  • Test Data Compression Using Don't Care Identification and Statistical Encoding Reviewed

    Seiji KAJIHARA,Kenjiro TANIGUCHI,Kohei MIYASE,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

    11th IEEE Asian Test Symposium   67 - 72   2002.11

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    Guam, USA   2002.11.18  -  2002.11.20

  • On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout Reviewed

    Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Purdue Univ.),Huaxing TANG,Seiji KAJIHARA,Kozo KINOSHITA(Osaka Gakuin Univ.)

    International Test Conference   83 - 89   2002.10

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    Baltimore, MD, USA   2002.10.07  -  2002.10.10

  • Average Power Reduction in Scan Testing by Test Vector Modification Reviewed

    Seiji KAJIHARA,Koji ISHIDA,Kohei MIYASE

    IEICE Trans. Information and Systems   E85-D ( 10 )   1483 - 1489   2002.10

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  • Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan Reviewed

    IEICE Trans. Information and Systems   E85-D ( 10 )   1490 - 1497   2002.10

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  • Don't Care Identification on Specific Bits of Test Patterns Reviewed

    Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

    International Conference on Computer Design   194 - 199   2002.09

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    Freiburg, Germany   2002.09.16  -  2002.09.18

  • テストパターン中の特定ビットにおけるドントケア判定法について Reviewed

    宮瀬紘平,梶原誠司,イリス ポメランツ(Purdue Univ.),スダーカ レディ(Univ. of Iowa)

    情報科学技術フォーラム 情報技術レターズ   1 ( LC-3 )   47 - 48   2002.09

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  • On Selecting Paths to Test in Scan Designs Reviewed

    Yun SHAO(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Purdue Univ.),Seiji KAJIHARA

    European Test Workshop   233 - 238   2002.05

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    Corfu, Greece   2002.05.26  -  2002.05.29

  • On Testing of Interconnect Open Faults in Combinational Logic Circuits with Stems of Large Fanout Reviewed

    Huaxing TANG(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Purdue Univ.),Seiji KAJIHARA,Kozo KINOSHITA(Osaka Gakuin Univ.)

    European Test Workshop   127 - 128   2002.05

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    Corfu, Greece   2002.05.26  -  2002.05.29

  • On Test Data Volume Reduction for Multiple Scan Chain Designs Reviewed

    Sudhakar M. REDDY(Univ. of Iowa),Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.)

    IEEE VLSI Test Symposium   103 - 108   2002.05

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    Monterey, CA, USA   2002.04.28  -  2002.05.02

  • A Method of Static Test Compaction Based on Don't Care Identification Reviewed

    Kohei MIYASE,Seiji KAJIHARA,Sudhakar M. REDDY(Univ. of Iowa)

    43 ( 5 )   1290 - 1293   2002.05

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  • Test Vector Modification for Power Reduction during Scan Testing Reviewed

    Seiji KAJIHARA,Koji ISHIDA,Kohei MIYASE

    IEEE VLSI Test Symposium   160 - 165   2002.04

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    Monterey, CA, USA   2002.04.28  -  2002.04.28

  • Test Data Compression Using Don't Care Identification and Statistical Encoding Reviewed

    Seiji KAJIHARA,Kenjiro Taniguchi,Irith POMERANZ(Purdue Univ.),and Sudhakar M. REDDY(Univ. of Iowa)

    IEEE International Workshop on Electronic Design, Test & Applications   413 - 416   2002.01

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    Christchur, New Zealand   2002.01.29  -  2002.01.31

  • A Method of Static Test Compaction Based on Don't Care Identification Reviewed

    Kohei MIYASE,Seiji KAJIHARA,Sudhakar M. REDDY(Univ. of Iowa)

    IEEE International Workshop on Electronic Design, Test & Applications   392 - 395   2002.01

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    Christchurch, New Zealand   2002.01.29  -  2002.01.31

  • Test Power Reduction for Full Scan Sequential Circuits by Test Vector Modification Reviewed

    Seiji KAJIHARA,Koji ISHIDA,Kohei MIYASE

    IEEE Workshop on RTL ATPG & DFT   140 - 145   2001.11

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    Nara, Japan   2001.11.22  -  2001.11.23

  • An Efficient Method to Identify Untestable Path Delay Faults Reviewed

    Yun SHAO(Univ. of Iowa),Seiji KAJIHARA,Irith POMERANZ(Purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

    10th IEEE Asian Test Symposium   233 - 238   2001.11

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    Kyoto, Japan   2001.11.19  -  2001.11.21

  • Hybrid BIST Using Partially Rotational Scan Reviewed

    Kenichi ICHINO(Tokyo Metoropolitan Univ.),Takeshi ASAKAWA(Tokyo Metoropolitan Univ.),Satoshi FUKUMOTO(Tokyo Metoropolitan Univ.),Kazuhiko IWASAKI(Tokyo Metoropolitan Univ.),Seiji KAJIHARA

    10th IEEE Asian Test Symposium   379 - 384   2001.11

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    Kyoto, Japan   2001.11.19  -  2001.11.21

  • On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits Reviewed

    Seiji KAJIHARA,Kohei MIYASE

    IEEE/ACM International Conference on Computer-Aided Design   364 - 369   2001.11

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    Sun Jose, CA, USA   2001.11.04  -  2001.11.08

  • Test volume reduction for multiple scan chain designs by modifyingand encoding scan vectors Reviewed

    Kohei MIYASE,Seiji KAJIHARA,Irith POMERANZ(purdue Univ.),Sudhakar M. REDDY(Univ. of Iowa)

    2nd IEEE International Workshop on Test Resource Partitioning   2001.11

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    Baltimore, MD, USA   2001.11.01  -  2001.11.02

  • Selection of Potentially Testable Path Delay Faults for Test Generation Reviewed

    Atsushi MURAKAMI,Seiji KAJIHARA,Tsutomu SASAO,Irith POMERANZ(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa)

    Proceedings of IEEE International Test Conference   376 - 384   2001.10

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    Atlantic City, NJ, USA   2001.10.01  -  2001.10.06

  • 最小テスト集合でテスト可能な加算器について Reviewed

    梶原誠司,笹尾勤

    情報処理学会論文誌   42 ( 4 )   1045 - 1053   2001.04

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  • トランジション故障を検出するBIST指向テストパターン発生回路 Reviewed

    浅川毅(都立大),岩崎一彦(都立大),梶原誠司

    電子情報通信学会論文誌D-I   J84-D-I ( 2 )   165 - 172   2001.04

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  • Enhanced Untestable Path Analysis Using Edge Graphs Reviewed

    Seiji KAJIHARA,Takashi SHIMONO,Irith POMERANZ(Univ. of Iowa),Sudhakar M. REDDY(Univ. of Iowa)

    Proceedings of 9th IEEE Asian Test Symposium   139 - 144   2000.12

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    Taipei, Taiwan   2000.12.04  -  2000.12.06

  • On Validating Data Hold Times for Flip-flops in Sequential Circuits Reviewed

    Sudhakar M. REDDY(Univ. of Iowa),Irith POMERANZ(Univ. of Iowa),Seiji KAJIHARA,Atsushi MURAKAMI,Sadami TAKEOKA(Matsushita),Mitsuyasu OHTA(Matsushita)

    Proceedings of IEEE International Test Conference   317 - 324   2000.10

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    Atlantic City, NJ, USA   2000.10.01  -  2000.10.06

  • テスト数制限下でのテスト生成手法について Reviewed

    市原英行(大阪大),梶原誠司,樹下行三(大阪大)

    電子情報通信学会論文誌 D-I   J82-D-I ( 7 )   861 - 868   2000.04

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  • On Processing Order for Obtaining Implication Relations in Static Learning Reviewed

    Hideyuki Ichihara(Hiroshima City Univ.),Seiji Kajihara,Kozo Kinoshita(Osaka Univ.)

    IEICE Trans. Information and Systems   E83-D ( 10 )   1908 - 1911   2000.04

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  • 論理回路における遅延テスト不要パスの高速導出法 Reviewed

    梶原誠司,樹下行三(大阪大),イリス ポメランツ(Univ. of Iowa),スダーカ M. レディ(Univ. of Iowa)

    電子情報通信学会論文誌D-I   J82-D-I ( 7 )   888 - 896   2000.04

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  • On Compact Test Sets for Multiple Stuck-at Faults in Large Circuits Reviewed

    Seiji Kajihara,Atsushi Murakami,Tomohisa Kaneko

    8th IEEE Asian Test Symposium   20 - 24   1999.11

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    Shanghai, China   1999.11.16  -  1999.11.18

  • On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits Reviewed

    Hideyuki Ichihara(Osaka Univ.),Seiji Kajihara,Kozo Kinoshita(Osaka Univ.)

    8th IEEE Asian Test Symposium   147 - 152   1999.11

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    Shanghai, China   1999.11.16  -  1999.11.18

▼display all

Publications (Books)

  • はかる×わかる半導体-応用編

    浅田邦博(監修),井上智生,井上美智子,岩崎一彦,温暁青,梶原誠司,小林春夫,小松聡,佐藤康夫,志水勲,高橋寛,畠山一実(Joint author ,  第1章1.1,1.2,1.4)

    日経BPコンサルティング  2019.05  ( ISBN:978-4-86443-130-9

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    Language:Japanese

    高度な半導体の設計、製造および高品質な回路設計手法、 最新の品質保証など、より実務に近く深い知識を解説しています。 本書は、半導体技術者検定 エレクトロニクス2級 「設計と製造」「応用と品質」の 公式テキストとして採用されています。

  • はかる×わかる半導体 半導体テスト技術者検定3級問題集

    浅田邦博(監修),小松聡,温暁青,梶原誠司,佐藤康夫,中村和之,井上美智子,小林春夫,畠山一実,志水勲,岩崎一彦,井上智生,高橋寛(Joint author)

    日経BPコンサルティング  2014.12  ( ISBN:978-4-8644-3071-5

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    Language:Japanese

    「半導体テスト技術者検定」の受検者向けに、問題と解答・解説をまとめた問題集.

  • はかる×わかる半導体-入門編

    浅田邦博(監修),温暁青,梶原誠司,小松聡,佐藤康夫,志水勲,中村和之,畠山一実(Joint author ,  序章)

    日経BPコンサルティング  2013.05  ( ISBN:978-4-8644-3039-5

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    半導体の構造から試験手法までわかりやすく解説

Conference Prsentations (Oral, Poster)

  • デジタル温度電圧センサにおける特定温度電圧領域の推定精度向上手法

    井上賢二

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2018.02.20   Language:Japanese  

  • FPGAの自己テストのためのTDCを用いたテストクロック観測手法の検討

    三宅庸資

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2017.12.25   Language:Japanese  

  • スキャンベース論理BISTにおけるマルチサイクルテストの中間観測FF選出手法について

    大島繁之

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2017.11.06 - 2017.11.08   Language:Japanese  

  • On Avoiding Test Data Corruption by Optimal Scan Chain Grouping

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    Event date: 2017.11.06 - 2017.11.08   Language:English  

  • デジタル温度電圧センサにおける温度2点補正手法の検討

    三宅庸資

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2017.07.26 - 2017.07.28   Language:Japanese  

  • 論理BISTにおけるスキャンイン電力 制御手法とTEG評価

    加藤隆明

    情報処理学会DAシンポジウム  情報処理学会

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    Event date: 2016.09.14 - 2016.09.16   Language:Japanese  

  • 論理パスとクロックパスを考慮した実速度スキャンテスト生成手法について

    李富強

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2016.02.17   Language:Japanese  

  • デジタルモニタを用いたチップ内温度電圧変動の測定について

    三宅庸資

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2015.12.18   Language:Japanese  

  • FPGAのオンチップ遅延測定における温度影響補正の検討

    三宅庸資

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2015.12.01 - 2015.12.03   Language:Japanese  

  • リングオシレータを用いたFPGA上の完全デジタル温度モニタ

    三宅庸資

    情報処理学会DAシンポジウム  情報処理学会

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    Event date: 2015.08.26 - 2015.08.28   Language:Japanese  

  • FPGAのリングオシレータを利用した温度モニタ

    三宅庸資

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2014.12.19   Language:Japanese  

  • FPGAのリングオシレータにおけるNBTI劣化量の低減と制御に関する検討

    佐藤康夫

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2014.12.19   Language:Japanese  

  • FPGAにおけるオンチップ遅延測定について

    安部賢太朗

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2014.11.28   Language:Japanese  

  • 低電力BIST手法におけるキャプチャ電力のTEG評価

    西田敏也

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2014.06.20   Language:Japanese  

  • FPGAの自己テストのための可変タイミングクロック生成

    佐藤康夫

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2013.12.13   Language:Japanese  

  • データマイニング手法によるバーンインテスト結果予測の検討

    野々山聡

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2013.11.29   Language:Japanese  

  • 論理BISTにおけるスキャンイン電力制御回路のTEG評価について

    加藤隆明

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2013.11.29   Language:Japanese  

  • FPGAにおける複数の周波数特性を実現するためのリングオシレータ構成法の検討

    三宅庸資

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2013.11.28   Language:Japanese  

  • フィールドテストのための温度・電圧モニタ回路構成の検討

    津森渉

    電子情報通信学会DC研究会 

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    Event date: 2012.11.28   Language:Japanese  

  • マルチサイクルBISTにおけるスキャン出力の電力低減手法

    王森レイ

    電子情報通信学会DC研究会  電子情報通信学会

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    Event date: 2012.11.28   Language:Japanese  

  • フィールド高信頼化のための回路・システム機構

    本人

    電子情報通信学会2009年総合大会講演論文集 

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    Event date: 2009.03.17 - 2009.03.20   Language:Japanese  

  • 論理回路の経時変化の発生箇所について

    情報創成工学専攻

    第60回FTC研究会 

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    Event date: 2009.01.29 - 2009.01.31   Language:Japanese  

  • 実速度スキャンテストにおけるキャプチャセーフテスト生成手法について

    情報創成工学専攻

    電子情報通信学会技術研究報告 

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    Event date: 2008.11.17 - 2008.11.19   Language:Japanese  

  • 3値論理シミュレーションにおける遅延計算について

    情報システム専攻

    第59回FTC研究会 

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    Event date: 2008.07.17 - 2008.07.19   Language:Japanese  

  • 論理回路の動作環境とトランジスタの劣化特性について

    情報システム工学専攻

    電子情報通信学会技術研究報告 

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    Event date: 2008.06.20   Language:Japanese  

  • 実速度スキャンテストにおけるキャプチャ時消費電力削減手法

    情報システム専攻

    第58回FTC研究会 

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    Event date: 2008.01.10 - 2008.01.12   Language:Japanese  

  • 実速度スキャンテストにおけるキャプチャ時の低消費電力テスト生成手法について

    情報創成工学専攻

    電子情報通信学会技術研究報告 

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    Event date: 2007.11.20   Language:Japanese  

  • Per-Test X故障診断手法の診断分解能向上について

    情報創成工学専攻

    LSIテスティングシンポジウム2007 

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    Event date: 2007.11.07 - 2007.11.09   Language:Japanese  

  • A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

    Microelectronics Assembling and Packaging & Reverse Trade Show 2007 

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    Event date: 2007.10   Language:English  

  • LSI回路のX故障による Per-Test 故障診断手法の拡張について

    情報創成工学専攻

    電子情報通信学会技術研究報告 信頼性研究会 

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    Event date: 2007.09.14   Language:Japanese  

  • 順序回路用故障シミュレーションにおけるコンパイル方式の適用と効果について

    情報システム専攻

    電子情報通信学会技術研究報告 

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    Event date: 2007.02   Language:Japanese  

  • 低消費電力テストのための制約付テスト生成手法について

    情報創成工学専攻

    電子情報通信学会技術研究報告 

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    Event date: 2007.01.18 - 2007.01.19   Language:Japanese  

  • 遅延テスト品質の正確な評価法とテスト生成への応用

    情報創成工学専攻

    第56回FTC研究会 

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    Event date: 2007.01.11 - 2007.01.13   Language:Japanese  

  • LSI回路の新しいX故障によるPer-Test故障診断手法について

    情報システム専攻

    LSIテスティングシンポジウム 

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    Event date: 2006.11   Language:Japanese  

  • ブロードサイドテストにおけるN回検出用テストパターンに対するX判定

    情報システム専攻

    電子情報通信学会技術研究報告 

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    Event date: 2006.11   Language:Japanese  

  • コンパイル方式とイベント駆動方式を用いた故障シミュレーションの高速化について

    情報システム専攻

    第55回FTC研究会 

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    Event date: 2006.07.20 - 2006.07.22   Language:Japanese  

  • フルスキャン順序回路用2パターンテストに対するドントケア判定

    情報システム専攻

    情報処理学会 DAシンポジウム 2006 

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    Event date: 2006.07   Language:Japanese  

  • テスト生成における間接含意の効率的な生成方法

    電子情報通信学会VLD研究会技術研究報告 

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    Event date: 2006.05.11   Language:Japanese  

  • ブロードサイド方式におけるパス長を考慮した遷移故障用テストパターン生成について

    情報創成工学専攻

    電子情報通信学会技術研究報告 

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    Event date: 2006.02   Language:Japanese  

  • ブロードサイドテストにおける高品質テストパターンの生成について

    電子情報工学科

    第54回FTC研究会 

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    Event date: 2006.01   Language:Japanese  

  • スキャンテストにおけるキャプチャ時の低消費電力化に効果的なテスト集合変更について

    情報創成工学専攻

    電子情報通信学会技術研究報告 

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    Event date: 2005.11.30 - 2005.12.02   Language:Japanese  

  • 故障診断のための観測性の定量化について

    情報システム専攻

    LSIテスティングシンポジウム2005 

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    Event date: 2005.11   Language:Japanese  

  • X故障モデルに対する故障シミュレーションの効率化について

    情報創成工学専攻

    第53回FTC研究会 

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    Event date: 2005.07   Language:Japanese  

  • 縮退故障用テストパターンのブリッジ故障検出率向上手法について

    情報システム専攻

    情報処理学会 DAシンポジウム 2005 

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    Event date: 2005.07   Language:Japanese  

  • SoCにおけるブロードキャストスキャンテスト効率化手法について

    情報システム専攻

    第53回FTC研究会 

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    Event date: 2005.07   Language:Japanese  

  • ディレイ品質を予測する統計的品質モデル

    半導体露光学研究センター 浜田周治

    電子情報通信学会技術研究報告 

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    Event date: 2005.02   Language:Japanese  

  • 超微細LSIのパス遅延故障に対するテスト圧縮法について

    本人

    電子情報通信学会技術研究報告 

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    Event date: 2005.02   Language:Japanese  

  • 順序回路に対するテスト系列中のドントケア値発見とテスト圧縮・消費電力削減への応用について

    愛媛大 樋上喜信

    電子情報通信学会技術研究報告 

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    Event date: 2005.01   Language:Japanese  

  • スキャンテストにおけるキャプチャ時の消費電力削減を考慮したテスト生成

    第52回FTC研究会 

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    Event date: 2005.01   Language:Japanese  

  • タイミングを考慮した統計的遅延品質評価方法

    半導体理工学研究センター 浜田周治

    第52回FTC研究会 

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    Event date: 2005.01   Language:Japanese  

  • 故障診断のための観測性の定量化について

    情報システム専攻 豊田直哉

    電子情報通信学会技術研究報告 

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    Event date: 2005.01   Language:Japanese  

  • 入力ベクトルからの信号値を正当化する最小キューブ抽出

    本人

    電子情報通信学会技術研究報告 

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    Event date: 2004.12   Language:Japanese  

  • スキャン極性調節とピンポイントテスト変換によるテスト圧縮

    情報システム専攻 土井康稔

    電子情報通信学会技術研究報告 

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    Event date: 2004.12   Language:Japanese  

  • X故障モデルを用いたPer-Test故障診断手法について

    本人

    LSIテスティングシンポジウム2004 

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    Event date: 2004.11   Language:Japanese  

  • X故障モデルを用いたSLAT故障診断手法について

    情報システム専攻 三好勅元

    情報処理学会 DAシンポジウム 

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    Event date: 2004.07   Language:Japanese  

  • トランジスタの動作領域を考慮したデジタル回路のテストと解析

    情報システム専攻 山下善之

    第51回FTC研究会 

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    Event date: 2004.07   Language:Japanese  

  • Random Access Scan: A Solution to test power, test data volume and test time

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    Event date: 2004.02   Language:English  

  • Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values

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    Event date: 2004.01   Language:English  

  • ランレングス符号とピンポイントテストパターン変換によるテストデータ量削減

    情報システム専攻 土井康稔

    電子情報通信学会技術研究報告 

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    Event date: 2003.11   Language:Japanese  

  • 多重スキャンツリー設計によるテスト圧縮手法

    情報システム専攻 宮瀬紘平

    電子情報通信学会技術研究報告 

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    Event date: 2003.11   Language:Japanese  

  • 順序回路のテスト系列中のドントケア値発見法

    愛媛大学 樋上喜信

    平成15年電気学会電子・情報・システム部門大会講演論文集 

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    Event date: 2003.08   Language:Japanese  

  • テスト不能パス解析に基づくパス遅延故障検出効率の統計的推定について

    情報システム専攻 福永昌勉

    第49回FTC研究会資料 

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    Event date: 2003.07   Language:Japanese  

  • パス遅延故障テストにおける故障検出率の推定法

    情報システム専攻 福永昌勉

    電子情報通信学会 技術研究報告,DC2002-85 

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    Event date: 2003.02.21   Language:Japanese  

  • スキャンツリーを用いたテストデータ量削減について

    第48回FTC研究会資料 

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    Event date: 2003.01.09 - 2003.01.11   Language:Japanese  

  • 静的学習における効率的な間接含意の発見と保存について

    電子情報通信学会 技術研究報告 VLD2002-86 

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    Event date: 2002.11.27 - 2002.11.28   Language:Japanese  

  • 符号化技術を用いた多重スキャン回路のテストデータ量削減について

    情報処理学会 研究報告 2002-SLDM-107 

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    Event date: 2002.11.27 - 2002.11.28   Language:Japanese  

  • ディレイテストにおけるパス選択基準とテストクオリティの評価

    電子情報通信学会 FTS研究会 技術研究報告 

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    Event date: 2002.02.22   Language:Japanese  

  • パス遅延故障のテストに有効なパスの選択について

    第46回FTC研究会 

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    Event date: 2002.01.10 - 2002.01.12   Language:Japanese  

  • BIST指向n検出TPGの提案

    電子情報通信学会 技術研究報告(FTS研究会) 

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    Event date: 2001.11.29 - 2001.11.30   Language:Japanese  

  • 論理回路のテストパターンに含まれるドントケアの判定法について

    情報処理学会 システムLSI設計技術研究会 

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    Event date: 2001.11.28 - 2001.11.29   Language:Japanese  

  • 二重検出法に基づく故障シミュレーションの高速化について

    電子情報通信学会FTS研究会技術報告 

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    Event date: 2001.11.28 - 2001.11.29   Language:Japanese  

  • ドントケア判定と符号化によるテストデータ圧縮について

    電子情報通信学会FTS研究会技術報告 

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    Event date: 2001.11.28 - 2001.11.29   Language:Japanese  

  • テストパターン中のドントケアの検出とその応用

    第45回FTC研究会 

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    Event date: 2001.07.30 - 2001.07.31   Language:Japanese  

  • 部分ローテート型スキャンを用いたハイブリッドBIST

    第45回FTC研究会 

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    Event date: 2001.07.30 - 2001.07.31   Language:Japanese  

  • テストベクトル変換によるテスト時の消費電力低減手法について

    情報処理学会 DAシンポジウム2001 

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    Event date: 2001.07.23 - 2001.07.25   Language:Japanese  

  • テスト不能なパス遅延故障判定の高精度化手法について

    情報処理学会 DAシンポジウム2000 論文集 

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    Event date: 2001.07.17 - 2001.07.19   Language:Japanese  

  • ショーパスディレイ:故障モデルとテスト生成

    電子情報通信学会 技術研究報告(FTS研究会) 

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    Event date: 2001.02.08 - 2001.02.09   Language:Japanese  

  • ショートパスディレイテスト手法

    第44回FTC研究会 

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    Event date: 2001.01.25 - 2001.01.27   Language:Japanese  

  • BIST指向n検出テストパターンの圧縮法

    電子情報通信学会情報・システムソサイエティ大会論文講演集,情報・システム 1 

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    Event date: 2000.09.30 - 2000.10.03   Language:Japanese  

  • 遺伝的アルゴリズムを用いたテスト圧縮について

    2000年電子情報通信学会総合大会論文講演集,情報・システム 1, D-10-6 

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    Event date: 2000.03.28 - 2000.03.31   Language:Japanese  

  • テストパターン中のドントケアの発見手法について

    2000年電子情報通信学会総合大会論文講演集, 情報・システム 1, D-10-5 

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    Event date: 2000.03.28 - 2000.03.31   Language:Japanese  

  • ディレイ故障を検出するBIST用テストパターン発生回路

    情報処理学会 研究報告(システムLSI設計技術研究会) 

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    Event date: 2000.02.02 - 2000.02.03   Language:Japanese  

  • トランジション故障に対するコンパクトテストについて

    第42回FTC研究会資料 

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    Event date: 2000.01.20 - 2000.01.22   Language:Japanese  

  • パス遅延故障におけるパス選択とテスト生成について

    電子情報通信学会 技術研究報告(フォールトトレラントシステム研究会) 

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    Event date: 1999.11.26 - 1999.11.27   Language:Japanese  

  • On maximizing multiple bridging fault coverage with limited number of measurement vectors for sequential circuits

    第41回FTC研究会資料 

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    Event date: 1999.07.29 - 1999.07.31   Language:Japanese  

  • テスト不能パス解析を用いたパス遅延故障のテスト生成について

    第41回FTC研究会資料 

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    Event date: 1999.07.29 - 1999.07.31   Language:Japanese  

  • 含意に基づいたテスト不能パス解析の効率化について

    第41回FTC研究会資料 

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    Event date: 1999.07.29 - 1999.07.31   Language:Japanese  

  • ベクトルペア解析による多重縮退故障のテスト圧縮について

    情報処理学会 DAシンポジウム'99 論文集 

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    Event date: 1999.07.15 - 1999.07.17   Language:Japanese  

  • On Test Generation with a Limited Number of Tests

    9th Great Lakes Symposium on VLSI 

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    Event date: 1999.03.04 - 1999.03.06   Language:English  

  • パス遅延故障のテストにおけるパス選択手法について

    電子情報通信学会 技術研究報告(フォールトトレラントシステム研究会) 

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    Event date: 1999.02.04 - 1999.02.05   Language:Japanese  

  • トランジション故障に対するテストパターンの極小化手法について

    電子情報通信学会 技術研究報告(フォールトトレラントシステム研究会) 

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    Event date: 1999.02.04 - 1999.02.05   Language:Japanese  

  • An Efficient Procedure for Obtaining Indirect Implications and Its Application to Redundancy Identification

    7th IEEE Asian Test Symposium 

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    Event date: 1998.12.02 - 1998.12.04   Language:English  

  • IDDQテストにおける故障検出率の最大化について

    第39回FTC研究会資料 

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    Event date: 1998.07.16 - 1998.07.18   Language:Japanese  

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Industrial Property

  • 故障検出システム、生産回路及びプログラム

    佐藤 康夫,王森レイ,宮瀬紘平,梶原誠司

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    Application no:10-2014-7034398  Date applied:2014.12.08

  • 故障検出システム、生産回路及びプログラム

    佐藤 康夫,王森レイ,宮瀬紘平,梶原誠司

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    Application no:14/402,732  Date applied:2014.11.21

  • 故障検出システム、生成回路及びプログラム

    佐藤康夫、王森レイ、宮瀬紘平、梶原誠司

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    Application no:特願2014-516759  Date applied:2013.05.14

    Patent/Registration no:6223967  Date registered:2017.10.13 

  • テストパターン生産装置、故障検出システム、テストパターン生産方法、プログラム及び記憶媒体

    佐藤康夫、梶原誠司

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    Application no:特願2013-553292  Date applied:2013.01.09

    Patent/Registration no:5988443  Date registered:2016.08.19 

  • テストパターン生産装置、故障検出システム、テストパターン生産方法、プログラム及び記録媒体

    佐藤康夫、梶原誠司

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    Application no:特願2013-553292  Date applied:2013.01.09

    Announcement no:WO2013/105564  Date announced:2013.07.18

  • 故障検出システム、生産回路及びプログラム

    佐藤 康夫,王森レイ,宮瀬紘平,梶原誠司

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    Application no:'特願2012-117842  Date applied:2012.05.23

  • 故障検出システム、取出装置、故障検出方法、プログラム及び記録媒体

    佐藤康夫、梶原誠司

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    Application no:2012-537651  Date applied:2011.09.28

    Patent/Registration no:5845187  Date registered:2015.11.27 

  • 半導体装置、検知方法及びプログラム

    佐藤康夫,梶原誠司,井上美智子,米田友和,李賢彬,三浦幸也

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    Application no:2012-505659  Date applied:2011.03.14

    Patent/Registration no:5737524  Date registered:2015.05.01 

  • 半導体装置、検知方法及びプログラム

    佐藤康夫,梶原誠司,井上美智子,米田友和,李賢彬,三浦幸也

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    Application no:13/635,057  Date applied:2011.03.14

    Patent/Registration no:9316684  Date registered:2016.04.19 

  • 半導体装置、検知方法及びプログラム

    佐藤康夫,梶原誠司,井上美智子,米田友和,李賢彬,三浦幸也

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    Application no:201180014113.1  Date applied:2011.03.14

    Patent/Registration no:ZL201180014113.1  Date registered:2014.12.10 

  • リング発振器

    佐藤康夫,三浦幸也,梶原誠司

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    Application no:2011-008850  Date applied:2011.01.19

  • Ring Oscillator

    Yukiya Miura, Yasuo Sato, Seiji Kajihara

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    Application no:2011-008850  Date applied:2011.01.19

    Patent/Registration no:6083586  Date registered:2017.02.03 

  • 生成装置、生成方法、及び、プログラム

    Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato

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    Application no:200980134361.2  Date applied:2009.07.30

    Patent/Registration no:10-1555736  Date registered:2015.09.18 

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Lectures

  • A Fully Digital Temperature and Voltage Sensor for IoT Devices

    5th International Symposium on Applied Engineering and Sciences (SAES2017)  2017.11  Univerisiti Putra Malaysia

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    Presentation type:Keynote lecture  

  • Right Power Testing for Scan-Based BIST and Its Evaluation with TEG Chips

    The 11th VLSI Test Technology Workshop  2017.07  Taiwann IC Design Society

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    Presentation type:Keynote lecture  

  • Growth of ATS in the 21st century: Outlook of the future of ATS in Japan

    25th IEEE Asian Test Symposium  2016.11  IEEE Computer Society

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    Presentation type:Panel discussion  

  • VLSIテスト技術によるシステムディペンダビリティ向上への期待

    日本信頼性学会 第24回春季信頼性シンポジウム  2016.05  日本信頼性学会

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    Presentation type:Special lecture   Venue:東京  

  • VLSIテスト技術によるシステムディペンダビリティ向上への期待

    電子情報通信学会デザインガイア2015  2015.12  電子情報通信学会

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    Presentation type:Invited lecture   Venue:長崎市  

  • Failure Prediction of Logic Circuits for High Field Reliability

    16th IEEE Workshop on RTL and High Level Testing  2015.11  IEEE Computer Society

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    Presentation type:Invited lecture  

  • VLSI design and testing for enhanced systems dependability

    International Workshop on Reliability Aware System Design and Test  2013.01  IEEE Computer Society

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    Presentation type:Invited lecture  

  • 組込み自己テストによるフィールド高信頼化について

    電子情報通信学会デザインガイア2012  2012.11  電子情報通信学会

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    Presentation type:Invited lecture   Venue:福岡市  

  • Failure Prediction of Logic Circuits for High Field Reliability

    International Workshop on Reliability Aware System Design and Test  2012.01  IEEE Computer Society

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    Presentation type:Invited lecture  

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Press

  • NIKKEI ELECTRONICS WIRE SERVICE:NEWS

    梶原誠司

    日経BP社 日経エレクトロニクス編集部  2005.11.17

  • NIKKEI ELECTRONICS WIRE SERVICE:NEWS

    梶原誠司

    日経BP社 日経エレクトロニクス編集部  2005.11.16

  • NIKKEI ELECTRONICS WIRE SERVICE:NEWS NO.1762

    梶原誠司

    日経BP社 日経エレクトロニクス編集部  2004.11.02

Honors and Awards

  • IEICE Fellow

    2015.09.09

    Seiji Kajihara

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    Country:Japan

  • ATS2015 Best Paper Award

    2016.11.22

    Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara

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    Country:Japan

  • ITC2005 Most Significant Paper Award:

    2016.11.15

    Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara

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    Country:Japan

  • 電子情報通信学会情報・システムソサイエティ 論文賞

    電子情報通信学会   2011.06.02

    佐藤 康夫,浜田 周治,前田 敏行,高取 厚夫,野津山 泰幸,梶原 誠司

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    Country:Japan

  • 電子情報通信学会情報・システムソサイエティ 論文賞

    電子情報通信学会   2008.11

    Xiaoqing WEN, Seiji KAJIHARA, Laung-Terng WANG, Kewal K. SALUJA, Kozo KINOSHITA, Yoshiyuki YAMASHITA, Kohei MIYASE, Tatsuya SUZUKI

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    Country:Japan

Grants-in-Aid for Scientific Research

  • Reliability Prediction Using Manufacturing Test Results for Integrated Circuits

    Grant number:15K12004  2015.04 - 2018.03   Grant-in-Aid for challenging Exploratory Research

  • VLSIの高品質フィールドテストに関する研究

    Grant number:21300015  2009.04 - 2013.03   基盤研究(B)

  • 次世代LSIのための信号劣化回避型テスト方式に関する研究

    Grant number:19500047  2007.04 - 2010.03   基盤研究(C)

  • Study on LSI testing for multiple fault models

    Grant number:16500036  2004.04 - 2007.03   Grant-in-Aid for Scientific Research(C)

  • システムLSIに対するテスト効率化手法に関する研究

    Grant number:14780228  2002.04 - 2004.03   若手研究(B)

Other Research Activities

  • JST特許群支援

    2013.04
    -
    2016.03

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    JST特許群支援に採択された.
    ・特許群テーマ名: 高信頼VLSIテスト技術
    ・代表申請機関名: 国立大学法人 九州工業大学
    ・代表発明者氏名: 梶原誠司
    ・期間: 平成25~27年度
    これにより、(1) JSTの特許主任調査員などが特許群全体の出願戦略の助言、個別特許出願について国内出願段階から助言、および、(2) 外国特許出願支援制度を通じた、外国特許出願経費の支援を受けている。

Award for Educational Activities

  • 優秀若手講演賞

    電子情報通信学会ディペンダブルコンピューティング研究会   2015.12.01

     詳細を見る

    「低電力BIST手法におけるキャプチャ電力のTEG評価」の発表による

  • 研究会優秀発表学生賞

    情報処理学会SLDM研究会   2013.08

     詳細を見る

    「フィールドテストのための温度・電圧モニタ回路構成の検討」の発表による

Activities of Academic societies and Committees

  • IEEE WRTLT  

    2017.08 - 2017.11

  • Asian Test Symposium  

    2017.04 - 2017.11

  • IEEE ITC-Asia  

    2017.02

  • Design Automation and Test in Europe conference and exhibition  

    2016.08 - 2017.03

  • Asian Test Symposium   Ph.D. Thesis Contest Jury Member  

    2016.04 - 2016.11

  • Asian Test Symposium  

    2016.04 - 2016.11

  • 日本信頼性学会   評議員  

    2015.06

  • The institue of electronics, information and communication engineers (IEICE)  

    2014.06 - 2018.05

  • The Institute of Electrical and Electronics Engineers, Inc.   Regional Liaisons  

    2014.06 - 2015.05

  • パワーデバイス・イネーブリング協会検定委員会   検定問題審議委員  

    2013.10

  • VLSI Design and CAD Algorithm小特集号(英文論文誌A)   編集委員  

    2013.01 - 2014.01

  • パワーデバイス・イネーブリング協会検定委員会   検定用教科書編集委員  

    2012.08 - 2013.01

  • The institue of electronics, information and communication engineers (IEICE)  

    2012.05 - 2014.05

  • Euromicro Conference on Digital System Design   Program Committee Member  

    2012.04

  • VLSI Design and CAD Algorithm小特集号(英文論文誌A)   編集委員  

    2012.01 - 2013.01

  • The Institute of Electrical and Electronics Engineers, Inc.   Steering Committee Member  

    2011.04

  • VLSI Design and CAD Algorithm小特集号(英文論文誌A)   編集委員  

    2011.01 - 2012.01

  • The institue of electronics, information and communication engineers (IEICE)  

    2009.05 - 2012.05

  • The Institute of Electrical and Electronics Engineers, Inc.   Regional Liaisons  

    2008.06 - 2012.05

  • Journal of Electronic Testing: Theory and Applications  

    2001.01

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