YOSHIDA Takaichi





680-4 Kawazu, Iizuka-shi, Fukuoka

Research Fields, Keywords

object-oriented computing, distributed computing, adaptability

Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 1

Citation count denotes the number of citations in papers published for a particular year.

Undergraduate Education 【 display / non-display

  • 1982.03   Keio University   Faculty of Engineering   Department of Electrical Engineering   Graduated   JAPAN

Post Graduate Education 【 display / non-display

  • 1987.03  Keio University  Graduate School, Division of Engineering  Electrical Engineering  Doctoral Program  Completed  JAPAN

Degree 【 display / non-display

  • Keio University -  Doctor of Engineering  1987.03

Biography in Kyutech 【 display / non-display

  • 2019.04

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Professor  

  • 2008.04

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Creative Informatics   Professor  

Academic Society Memberships 【 display / non-display

  • 1998.04

    Information Processing Society of Japan (IPSJ)  JAPAN

  • 2000.04

    The Institute of Electrical and Electronics Engineers, Inc.  UNITED STATES

Specialized Field (scientific research fund) 【 display / non-display

  • Computer system


Publications (Article) 【 display / non-display

  • Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network "jointly worked"

    Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida

    Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020      235 - 241   2020.11  [Refereed]

    Japan  Naha  2020.11  -  2020.11

     View Summary

    Three-dimensional (3D) FPGAs can implement much higher logic density than present 2D FPGAs by stacking multiple FPGA device layers with 3D IC technology. However, routing architectures of 3D FPGAs are very different from those of conventional FPGAs with a regular 2D array structure, so a new universal architecture-aware placement method is required. In this work, we propose a convolutional neural network (CNN)-based pre-routing wirelength prediction cost function for 3D FPGA placement. By training an optimized CNN with a dataset made from actual routing results, the CNN can learn 3D FPGA architecture features and predict net wirelength accurately. Dataset generation, CNN structure exploration, and training processes are universal and automated, so the proposed method can be easily applied to different 3D FPGAs. The evaluation results show that post-routing total wirelength can be significantly reduced with a 3D FPGA placer that uses the CNN-based cost function for global placement phase and then uses the conventional half-perimeter wirelength (HPWL)-based cost function for detailed placement phase.

    DOI Scopus

  • A microcode-based control unit for deep learning processors "jointly worked"

    Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida

    Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020      139 - 142   2020.05  [Refereed]

     View Summary

    © 2020 IEEE. Heterogeneous computing systems that integrate general-purpose processors with various types of application-specific accelerators are becoming mainstream. However, designing an efficient and flexible instruction set architecture (ISA) for a new accelerator is challenging. In this paper, we design a deep learning processing unit (DPU) as an example in order to explore a microcode-based control unit approach for application-specific accelerators. By removing the conventional ISA-based control logic and directly exposing the necessary control signals of the hardware blocks through a sequencer-based microprogrammed control unit, the functional capability of the accelerator is no longer limited by the ISA. Moreover, the design cycle can be shortened because the control logics are moved from hardware to firmware.

    DOI Scopus

  • A pre-routing net wirelength prediction method using an optimized convolutional neural network "jointly worked"

    Ryota Watanabe, Yuki Katsuda, Qian Zhao, Takaichi Yoshida

    Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019      115 - 120   2019.11  [Refereed]

    Japan  Nagasaki  2019.11  -  2019.11

     View Summary

    © 2019 IEEE. The total wirelength of a circuit implementation is an important metric to evaluate the quality of an FPGA design flow. The wirelengths of all nets of a circuit are determined by routing, but pre-routing stages like placement can use a wirelength prediction model to direct the generation of a placement solution with a shorter total wirelength for routing. The conventional VPR employs a wirelength prediction model based on the bounding box size and the number of sinks of a net, which works well for an FPGA of a regular 2D array structure. However, new FPGA architectures like 3D-FPGA and hierarchical routing cannot use such a simple model. In this work, we propose a method to build an optimized net wirelength prediction model using a convolutional neural network, which can learn routing features from routed nets without manual tunings. The evaluation results show an optimized CNN model also has higher accuracy than the VPR model.

    DOI Scopus

  • Implementation of FPGA building platform as a cloud service "jointly worked"

    Ryota Watanabe, Saika Ura, Qian Zhao, Takaichi Yoshida

    International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies      6 pages   2019.06  [Refereed]

    Japan  Nagasaki  2019.06  -  2019.06

     View Summary

    © 2019 Association for Computing Machinery. The building environment for field-programmable gate array (FPGA) development has a number of requirements such as using high-end computers for faster hardware compilation and installing the various versions of FPGA computer-aided design (CAD) tools specified by different projects while at the same avoiding conflicts between these tools. These requirements make it difficult to enable FPGA development on a wide range of devices, which is critical for developers from different application domains if they are to leverage FPGAs to their full extent. In this work, we propose an FPGA project building platform that reduces hardware costs by sharing high-performance servers between developers and enables a variety of FPGA CAD tools to be available in one platform by using container technology. The evaluation of the proposed platform showed that it provides shared and clean building environments without having significant performance overhead.

    DOI Scopus

  • A Platform-as-a-Service System for FPGA Education and Development "jointly worked"

    Qian Zhao, Takaichi Yoshida

    CompEd 2019 - Proceedings of the ACM Conference on Global Computing Education      2019.05  [Refereed]

    China  Chengdu,Sichuan  2019.05  -  2019.05

     View Summary

    © 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM. As a promising technology for the post-Moore era, FPGAs (Field- Programmable Gate Arrays) have been employed in a variety of cloud and edge applications to provide hardware acceleration capability. However, with the introduction of FPGAs, the system architecture and development flow are becoming more complicated. In this work, we propose a PaaS (Platform-as-a-Service) approach to simplify the education and development of an FPGA accelerated system, which allows the FPGA development can be completed with only a browser, and then the PaaS system can automatically perform FPGA compilation and deployment.

    DOI Scopus

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Conference Prsentations (Oral, Poster) 【 display / non-display

  • Privacy-Preserving Neural Network Training and Inference with Homomorphic Encryption

    Sunarto Jonathan Hans, Zhao Qian, Yoshida Takaichi

    2020年度電気・情報関係学会九州支部連合大会  (オンライン開催(大会本部:九州産業大学))  2020.09  -  2020.09  電気・情報関係学会九州支部連合大会委員会

     View Summary

    Using the high-performance cloud computing infrastructure to accelerate training and inference of deep learning neural networks is becoming mainstream. However, privacy leakage risk also increases because user data for training and inference must be plaintext in the cloud. To achieve a privacy-preserving neural network processing on a public cloud, we propose Homomorphic Encryption Neural Network (HE-NN), which can perform training and inference with encrypted data. For evaluation, we show the inference accuracy and processing time profiling of the proposed HE-NN.

  • ディープラーニングを用いた3次元FPGAでのネット配線長予測

    森田 晴道, 趙 謙, 吉田 隆一

    2020年度電気・情報関係学会九州支部連合大会  (オンライン開催(大会本部:九州産業大学))  2020.09  -  2020.09  電気・情報関係学会九州支部連合大会委員会

     View Summary

    従来の2次元FPGA(Field-programmable Gate Array)の配置段階において一般的に使われる配線長予測モデルHPWL(Half-perimeter Wirelength)は、複雑な配線構造を持った3次元FPGAに適用した場合、ネットの配線長の予測精度が低い問題がある。本研究では、ディープラーニングを用いた3次元FPGAでのネット配線長予測手法を提案する。実際のルーティング結果を用いて畳み込みニューラルネットワーク(CNN)を訓練することで、個々の3次元FPGA構造に特化した高精度なネット配線長予測モデルを容易に作成することができた。

  • ハードウェアとソフトウェアの融合による高性能な適応型分散システム

    野田 竜平, 趙 謙, 吉田 隆一

    2020年度電気・情報関係学会九州支部連合大会  (オンライン開催(大会本部:九州産業大学))  2020.09  -  2020.09  電気・情報関係学会九州支部連合大会委員会

     View Summary

    分散システムにおいて通信量の変動やデバイスの故障などの環境変化が絶えず発生している。それらの環境変化に対して情報システムの機能を変更して適応する必要がある。そこで我々の先行研究ではソフトウェアの機能モジュールを自律的に入れ替えることによって適応型分散システムJuiceを提案している。本研究ではFPGA(Field Programmable Gate Array)をハードウェアアクセラレータとして用いて、ハードウェア機能も変更出来る、高性能な適応型分散システムを提案する。FPGAの再構成を利用し、ハードウェアとソフトウェアの融合による環境適応の実現を目指す。

  • CNN を用いた FPGA ネット配線時間の予測モデルの一検討

    勝田 祐基, 渡邉 凌太, 趙 謙, 吉田 隆一

    若手の会セミナー 2019  (唐津市)  2019.12  -  2019.12  情報処理学会 九州支部

  • Fusing Software and Hardware for High Adaptability in Dynamic Reconfigurable Distributed System

    Shinya Nakayama, Qian Zhao, Takaichi Yoshida

    7th International Symposium on Applied Engineering and Sciences (SAES2019)  (Serdang, Selangor, Malaysia)  2019.11  -  2019.11  Universiti Putra Malaysia, Kyushu Institute of Technoligy

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Activities of Academic societies and Committees 【 display / non-display

  • 2015.04

    Information Processing Society of Japan (IPSJ)  

  • 2013.04

    Information Processing Society of Japan (IPSJ)