Faculty Profiles - MORIE Takashi

Papers - MORIE Takashi

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Robustness of Spiking Neural Networks based on Time-To-First-Spike Encoding against Adversarial Attacks Reviewed International journal

Nomura O., Sakemi Y., Hosomi T., Morie T.

IEEE Transactions on Circuits and Systems II: Express Briefs 2022.06

A Memory-Based Entorhinal-Hippocampal Model and its FPGA Implementation by On-Chip RAMs Reviewed International journal

I. Kawashima, K. Tateno, T. Morie, H. Tamukoh

Int. Symp. on Circuits and Systems (ISCAS 2022) ( IEEE ) 2022.05

A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing Reviewed International journal

Y. Sakemi, K. Morino, T. Morie, T. Hosomi, K. Aihara

Int. Symp. on Circuits and Systems (ISCAS 2022) ( IEEE ) 2022.05

A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing Reviewed International journal

Nakagawa H., Tateno K., Takada K., Morie T.

IEEE Access 10 43003 - 43012 2022.04

An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing Reviewed International journal

Kawashima I., Katori Y., Morie T., Tamukoh H.

International Conference on Field-Programmable Technology (ICFPT 2021) 2021.12

Brain-inspired neural network navigation system with hippocampus, prefrontal cortex, and amygdala functions Reviewed International journal

Mizutani A., Tanaka Y., Tamukoh H., Katori Y., Tateno K., Morie T.

International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2021) 2021.11

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design Reviewed International journal

Sakemi Y., Morino K., Morie T., Aihara K.

IEEE Transactions on Neural Networks and Learning Systems ( IEEE ) 2021.07

An Energy-efficient Time-domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-width Modulation Approach Reviewed International journal

Yamaguchi M., Iwamoto G., Nishimura Y., Tamukoh H., Morie T.

IEEE Access 2020.12

An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots Reviewed International journal

Tanaka Y., Morie T., Tamukoh H.

IEEE Access 8 212066 - 212078 2020.11

FPGA implementation of hardware-oriented chaotic Boltzmann machines Reviewed International journal

Kawashima I., Morie T., Tamukoh H.

IEEE Access 8 204360 - 204377 2020.11

A Time-domain Analog Weighted-sum Calculation Circuit Using Ferroelectric-gate Field-effect Transistors for Artificial Intelligence Processors Invited Reviewed International journal

M, Harada, M, Takahashi, S. Sakai, T. Morie

Japanese Journal of Applied Physics 59 ( 4 ) 040604-1 - 040604-12 2020.04

A Chaotic Boltzmann Machine Working as a Reservoir and Its Analog VLSI Implementation Reviewed

Yamaguchi M., Katori Y., Kamimura D., Tamukoh H., Morie T.

Proceedings of the International Joint Conference on Neural Networks 2019-July 2019.07

Neuromorphic systems and physical devices Invited Reviewed

Takashi Morie

Oyo Buturi ( The Japan Society of Applied Physics ) 88 ( 7 ) 481 - 485 2019.07

Authorship：Lead author,　Corresponding author Language：Japanese Publishing type：Article, review, commentary, editorial, etc. (scientific journal)

This article describes the significance, history, and current positioning of neuromorphic systems and spiking neuron models, which are closely related to artificial intelligence (AI). This article also describes what processing models are being proposed and what devices are required to realize them. We hope that it will give a hint as to how materials and devices in the field of applied physics can contribute to AI.

DOI： 10.11470/oubutsu.88.7_481

CiNii Article

Other Link： https://ci.nii.ac.jp/naid/130007709468

Reservoir Computing Based on Dynamics of Pseudo-Billiard System in Hypercube Reviewed

Katori Y., Tamukoh H., Morie T.

Proceedings of the International Joint Conference on Neural Networks 2019-July 2019.07

Live demonstration: A VLSI implementation of time-domain analog weighted-sum calculation model for intelligent processing on robots Reviewed International journal

Yamaguchi M., Iwamoto G., Abe Y., Tanaka Y., Ishida Y., Tamukoh H., Morie T.

IEEE International Symposium on Circuits and Systems (ISCAS 2019) 2019-May 2019.05

A CMOS Chaotic Boltzmann Machine Circuit and Three-neuron Network Operation Reviewed International journal

M. Yamaguchi, H. Tamukoh, H. Suzuki, T. Morie

Proc. Int. Joint Conf. on Neural Networks (IJCNN 2017) 1218 - 1224 2017.06

Silicon Nanodisk Array with a Fin Field-effect Transistor for Time-domain Weighted Sum Calculation toward Massively Parallel Spiking Neural Networks,, Reviewed International journal

T. Tohara, H. Liang, H. Tanaka, M. Igarashi, S. Samukawa, K. Endo, Y. Takahashi, T. Morie

Applied Physics Express Vol. 9 ( No. 3 ) 034201 2016.02

Parameterized Digital Hardware Design of Pulse-coupled Phase Oscillator Networks Reviewed International journal

Y. Suedomi, H. Tamukoh, K. Matsuzaka, M. Tanaka, T. Morie

Neurocomputing 165 54 - 62 2015.10

A PWM-mode Pixel-parallel Image Processing Circuit Performing Directional State-propagation and Its Application to Subjective Contour Generation Reviewed International journal

Y. Kim, T. Morie

Circuits, Systems & Signal Processing 34 ( 2 ) 605 - 623 2015.02

VLSI Implementation of a Coupled MRF Model Using Pulse-coupled Phase Oscillators Reviewed International journal

K. Matsuzaka, H. Tanaka, S. Ohkubo, T. Morie

Electronics Letters 51 ( 1 ) 46 - 48 2015.01

Single-electron Devices and Circuits Utilizing Stochastic Operation for Intelligent Information Processing Invited Reviewed International journal

T. Morie

Int. J. of Nanotechnology and Molecular Computation 1 ( 2 ) 1 - 28 2009.04

A Subjective-Contour Generation LSI System with Expandable Pixel-Parallel Architecture for Vision Systems, Reviewed International journal

T. Morie,Y. Kim

IEEE Int. Solid-State Circuits Conf. (ISSCC2009) 478 - 479 2009.02

An efficient hardware-oriented dropout algorithm Reviewed International journal

Neurocomputing 427 191 - 200 2021.02

Performance Evaluation of Reservoir Computing Using Pseudo-Billiard Dynamics in Hypercube Reviewed

D. Kamimura, Y. Katori, H. Tamukoh, and T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 135 - 135 2020.11

A Reservoir Based Q-learning Model for Autonomous Mobile Robots Reviewed

M. Inada, Y. Tanaka, H. Tamukoh, K. Tateno, T. Morie, Y. Katori

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 213 - 216 2020.11

FPGA Implementation and Verification of Reservoir Computing Based on Pseudo-Billiard Dynamics in Hypercube Reviewed

D. Yamamoto, I. Kawashima, H. Tamukoh, T. Morie, Y. Katori

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 264 - 264 2020.11

A Brain-inspired Artificial Intelligence Model of Hippocampus, Amygdala, and Prefrontal Cortex on Home Service Robots Reviewed

Y. Tanaka, H. Tamukoh, K. Tateno, Y. Katori, T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 138 - 141 2020.11

A Reservoir Computing System Using a CMOS Chaotic Boltzmann Machine Chip Controlled by SoC FPGA Reviewed

Y. Nishimura, M. Yamaguchi, D. Kamimura, H. Tamukoh, T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 137 - 137 2020.11

A Hippocampus Model for Episodic Memory Processing Using Associative Memory Reviewed

H. Nakagawa, K. Tateno, K. Takada, T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 136 - 136 2020.11

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design International journal

Y. Sakemi, K. Morino, T. Morie, K. Aihara

arXiv.org 2020.01

An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach International journal

M. Yamaguchi, G. Iwamoto, H. Tamukoh, T. Morie

arXiv.org 1810.06819 2019.02

A Time-domain Analog Weighted-sum Calculation Model for Extremely Low Power VLSI Implementation of Multi-layer Neural Networks International journal

Q. Wang, H. Tamukoh, T. Morie

arXiv.org 1810.06819 2018.10

Spike-based Time-domain Weighted-sum Calculation Using Nanodevices for Low Power Operation Invited Reviewed

T. Morie, H. Liang, T. Tohara, H. Tanaka, M. Igarashi, S. Samukawa, K. Endo, Y. Takahashi

16th Int. Conf. on Nanotechnology (IEEE NANO) 390 - 392 2016.08

Measurement and Analysis of a CMOS Chaotic Spiking Oscillator Circuit That Acts as a Filter of Spike Trains Reviewed

M. Yamaguchi, S. Uenohara, T. Morie, H. Tamukoh, K. Aihara,

Proc. of the 2015 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2015) 515 - 518 2015.12

A CMOS Circuit for PWM-mode Nonlinear Transformation Robust to Device Mismatches to Implement Coupled Map Lattice Models Reviewed

Nonlinear Theory and Its Applications, IEICE 6 ( 4 ) 570 - 581 2015.10

VLSI Pulse-Coupled Phase Oscillator Networks and Their Emulator toward Spike-based Computation for Intelligent Processing Invited Reviewed

H. Tamukoh, Y. Suedomi, K. Matsuzaka, T. Morie

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM 2015) 806 - 807 2015.09

Shadow Detection and Elimination Using a Light-source Color Vector and Its Application to In-vehicle Camera Images Reviewed

M. Tanaka, T. Morie

International Journal of Innovative Computing, Information and Control 11 ( 3 ) 865 - 879 2015.06

A Silicon Nanodisk Array Structure Realizing Synaptic Response of Spiking Neuron Models with Noise Invited Reviewed

T. Morie, H. Liang, Y. Sun, T. Tohara, M. Igarashi, S. Samukawa

The 19th Asia and South Pacific Design Automation Conference 185 - 190 2014.01

Three-terminal Ferroelectric Synapse Device with Concurrent Learning Function for Artificial Neural Networks Reviewed

Y. Nishitani, Y. Kaneko, M. Ueda, T. Morie, E. Fujii

Journal of Applied Physics 111 124108 2012.06

Analog CMOS Circuit Implementation of a Pulse-coupled Phase Oscillator System and Observation of Synchronization Phenomena, Reviewed

3 ( 2 ) 180 - 190 2012.04

A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation Reviewed

F. Maldonado H., H. Tanaka, T. Matsuo, T. Morie, K. Aihara

18th Int. Conf. on Neural Information Processing (ICONIP2011) III ( 7064 ) 381 - 388 2011.11

知的画像認識技術と脳型LSI実装 Invited Reviewed

森江隆, 石川聖二

電子情報通信学会誌 94 ( 6 ) 459 - 463 2011.06

アナログ・デジタル融合方式LSI技術による脳型視覚システム Invited Reviewed

森江隆

IEICE Fundamentals Review 1 ( 1 ) 19 - 29 2007.07

A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information Reviewed International journal

Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024.06

CMOS Digital-Analog Mixed Signal VLSI Implementation of a Hippocampus-Inspired Model Reviewed International journal

Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024.06

Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers Reviewed International journal

Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh

International Symposium on Circuits and Systems (ISCAS 2024) 2024.05

Learning reservoir dynamics with temporal self-modulation Reviewed International journal

Sakemi Y., Nobukawa S., Matsuki T., Morie T., Aihara K.

Communications Physics 7 ( 29 ) 1 - 11 2024.01

Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory Reviewed International journal

Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024.06

FPGA Implementation of a Chaotic Boltzmann Machine Annealer Reviewed International journal

K. Yoshioka, Y. Katori, Y. Tanaka, O. Nomura, T. Morie

International Joint Conference on Neural Networks (IJCNN 2023) 2023.06

Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-volatile Memory with Write-errors Reviewed International journal

N. Fuengfusin, H. Tamukoh, Y. Tanaka, O. Nomura, T. Morie

International Joint Conference on Neural Networks (IJCNN 2023) 2023.06

Random Network Structure of Materials Developing Next Generation AI Devices for Autonomous Robotics Invited International journal

H. Tanaka, H. Tamukoh, T. Morie

239th ECS Meeting with the 18th International Meeting on Chemical Sensors (IMCS) 2021.06

A hardware intelligent processing accelerator for domestic service robots Reviewed

Y. Ishida, T. Morie, H. Tamukoh

Advanced Robotics 2020.07

Initial states and analog switching behaviors of two major tantalum oxide resistive memories Reviewed International journal

Li Y., Tsurumaki-Fukuchi A., Arita M., Morie T., Takahashi Y.

Japanese Journal of Applied Physics 59 ( 4 ) 2020.04

Reconstructing bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems Reviewed

Itoh Y., Uenohara S., Adachi M., Morie T., Aihara K.

Chaos 30 ( 1 ) 2020.01

FPGA Implementation of Reservoir Computing Based on Pseudo-Billiard Dynamics in Hypercube

YAMAMOTO Daichi, KATORI Yuichi, TAMUKOH Hakaru, MORIE Takashi, KATORI Yuichi

Proceedings of the Annual Conference of JSAI ( The Japanese Society for Artificial Intelligence ) 2020 ( 0 ) 3Rin422 - 3Rin422 2020.01

Language：Japanese Publishing type：Research paper (other academic)

Reservoir computing (RC) is one of the frameworks of the recurrent neural network (RNN) and is applied to processing of time series data. The implementation of machine learning and neural networks generally demands large computational resources (or circuit resource) and power. Katori et al. proposed a reservoir computing model based on pseudo-billiard dynamics on a hypercube. This hypercube-based reservoir computing (HRC) can be implemented with less circuit resource and with low power consumption. In this study, we improve the HRC model based on the hardware-oriented algorithm that reduces the circuit resource consumption in digital circuit implementation with Field Programmable Gate Array (FPGA). We evaluate the proposed model with time series generation tasks and confirm that the accuracy of the time-series generation is comparable with the previously proposed model. This research may enhance the ability of RC and contribute to establish a new platform for artificial intelligence.

DOI： 10.11517/pjsai.JSAI2020.0_3Rin422

CiNii Article

Other Link： https://ci.nii.ac.jp/naid/130007857093

Hippocampus Model for Episodic Memory Processing Using Associative Memory Reviewed

立野勝巳, 森江隆

The proceedings of NOLTA2020 - 138 2020.01

Prediction of Sensory Information and Generation of Motor Commands for Autonomous Mobile Robots Using Reservoir Computing Reviewed International journal

M. Inada, Y. Tanaka, H. Tamukoh, K. Tateno, T. Morie, Y. Katori

Proc. of the 2019 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2015) 2019.12

脳型人工知能技術の開発 Invited

2019.11

Switching current of Ta<inf>2</inf>O<inf>5</inf>-based resistive analog memories Reviewed

Li Y., Tsurumaki-Fukuchi A., Arita M., Morie T., Takahashi Y.

2019 Silicon Nanoelectronics Workshop, SNW 2019 2019.06

Research and Development of Home Service Robots Aiming for Social Implementation

ONO Tomohiro, SAKATA Takuma, YOSHII Takumi, KAMIMURA Daichi, KANAMARU Kazuki, NAKAMURA Kentaro, NISHIMURA Yuta, MORIE Takashi, TAMUKOH Hakaru, HORI Sansei, ISHIDA Yutaro, TANAKA Yuichiro, YOSHIMOTO Yuma, ABE Yushi, MUTO Fuyuki, KABASHIMA Kohei, FUKUYADO Masashi

The Proceedings of JSME annual Conference on Robotics and Mechatronics (Robomec) ( The Japan Society of Mechanical Engineers ) 2019 ( 0 ) 1P2 - I02 2019.01

Language：Japanese Publishing type：Research paper (other academic)

Home service robots have begun attracting attention due to decreasing birthrate and increasing aging population. We,"Hibikino-Musashi@Home"team, develop home service robots, and participate international competitions; RoboCup@Home and World Robot Challenge (WRC), which are established to realize that robots will work and live with people in domestic environments. In this paper, we introduce our robots and technologies, especially an object recognition and manipulation system. We use You Only Look Once (YOLO) for object recognition. To train YOLO, a big dataset which is difficult to prepare in a short term is required. For this, we develop an automatic annotation system for YOLO which can generate 1.7 million training data, and we can complete training of YOLO in a day. To grasp objects, estimation of object orientations is required. Our system can detect the orientations by processing point clouds of objects. By using the system, we obtained about 30% of scores in Tidy Up Task in the WRC.

DOI： 10.1299/jsmermd.2019.1P2-I02

CiNii Article

Other Link： https://ci.nii.ac.jp/naid/130007774525

Investigation for Multilevel Memory Capability of ReRAM using Ta2O5-δ Insulator Reviewed

Y. Li, R. Katsumura, M. K. Gronroos, A. Tsurumaki-Fukuchi, M. Arita, H. Andoh, T. Morie, Y. Takahashi

IEEE Silicon Nanoelectronics Workshop (SNW) 78 - 79 2018.06

Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots Reviewed

Ishida Y., Morie T., Tamukoh H.

Proceedings - IEEE International Symposium on Circuits and Systems 2018.05

A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots Reviewed

Ishida Y., Morie T., Tamukoh H.

Proceedings - IEEE International Symposium on Circuits and Systems 2018-May 2018.04

A pulse-width-modulation mode CMOS integrated circuit implementation of threshold-coupled map Reviewed

Uenohara Seiji, Morie Takashi, Tamukoh Hakaru, Aihara Kazuyuki

Nonlinear Theory and Its Applications, IEICE 9 ( 2 ) 268 - 280 2018.04

A shared synapse architecture for efficient FPGA implementation of autoencoders Reviewed

13 ( 3 ) e0194049 2018.03

Brain-like analog computing and its dedicated integrated circuit Invited Reviewed

Takashi Morie

Artificial Intelligence 33 ( 1 ) 39 - 44 2018.01

A hardware-oriented dropout algorithm for efficient FPGA implementation Reviewed

10639 LNCS 821 - 829 2017.11

An implementation of a spiking neural network using digital spiking silicon neuron model on a SIMD processor Reviewed

10613 LNCS 437 - 438 2017.09

Fostering Professional Personnel for Intelligent Car and Robotics in Car-Robo Joint Graduate School Invited Reviewed

J. of JSEE 65 ( 4 ) 51 - 56 2017.07

Evaluation of multilevel memory capability of ReRAM using Ta<inf>2</inf>O<inf>5</inf>insulator and different electrode materials Reviewed

85 - 86 2017.06

Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links Reviewed

D. Pramanta, T. Morie, H. Tamukoh

Journal of Robotics, Networking and Artificial Life 4 ( 1 ) 91 - 96 2017.06

Self-Feedback Electrically Coupled Spin-Hall Oscillator Array for Pattern-Matching Operation Reviewed

K. Kudo, T. Morie

Appl. Phys. Express 10 ( 4 ) 043001 2017.03

Multi-Valued Quantization Neural Networks toward Hardware Implementation Reviewed

Y. Aratani, Y. Y. Jye, A. Suzuki, D. Shuto, T. Morie, H. Tamukoh

Proc. of the 2017 International Conference On Artificial Life And Robotics (ICAROB2017) 58 - 58 2017.01

Implementation of multi-FPGA Communication using Pulse-Coupled Phase Oscillators Reviewed

D. Pramanta, T. Morie, H. Tamukoh

Proc. of the 2017 International Conference On Artificial Life And Robotics (ICAROB2017) 57 - 57 2017.01

An Electrically Coupled Spin-Hall Oscillator Array for Pattern Matching Operation Reviewed

K. Kudo, T. Morie

61st Annual Conf. on Magnetism and Magnetic Materials (MMM 2016) 2016.11

A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines Reviewed

M. Yamaguchi, T. Kato, Q. Wang, H. Suzuki, H. Tamukoh, T. Morie

Proc. 23rd Int. Conf. on Neural Information Processing (ICONIP2016) 9947 248 - 255 2016.10

FPGA Implementation of Autoencoders Having Shared Synapse Architecture Reviewed

A. Suzuki, T. Morie, H. Tamukoh

Proc. 23rd Int. Conf. on Neural Information Processing (ICONIP2016) 9947 231 - 239 2016.10

Time-domain Weighted-sum Calculation for Ultimately Low Power VLSI Neural Networks Reviewed

Q. Wang, H. Tamukoh, T. Morie

Proc. 23rd Int. Conf. on Neural Information Processing (ICONIP2016) 9947 240 - 247 2016.10

Analog VLSI Circuits and Devices for Neuro-Inspired Time-Domain Computing Invited Reviewed

T. Morie

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM 2016) 117 - 118 2016.09

Hardware-oriented Algorithm for Chaotic Boltzmann Machines Reviewed

I. Kawashima, S. Uenohara, T. Kato, M. Yamaguchi, H. Suzuki, T. Morie, H. Tamukoh

Int. Workshop on Smart Info-Media Systems in Asia (SISA) 2016.09

Restricted Boltzmann Machines without Random Number Generators for Efficient Digital Hardware Implementation Reviewed

S. Hori, T. Morie, H. Tamukoh

The 25th Int. Conf. on Artificial Neural Networks (ICANN) 9886 391 - 398 2016.09

Depth-Based Visual Servoing Using Low-Accurate Arm Reviewed

L. Hofer, M. Tanaka, H. Tamukoh, A. A. F. Nassiraei, T. Morie

Joint 8th Int. Conf. on Soft Computing and Intelligent Systems and 17th Int. Symp. on Advanced Intelligent Systems (SCIS & ISIS 2016) 2016.08

Analog Memory Characteristics of 1T1R MoOx Resistive Random Access Memory Reviewed

M. Jo, R. Katsumura, A. Tsurumaki-Fukuchi, M. Arita, Y. Takahashi, H. Ando, and T. Morie

IEEE Silicon Nanoelectronics Workshop (SNW) 78 - 79 2016.06

Human Detection and Face Recognition Using 3D Structure of Head and Face Surfaces Detected by RGB-D Sensor Reviewed

M. Tanaka, H. Matsubara, T. Morie

Journal of Robotics and Mechatronics 27 ( 6 ) 691 - 697 2015.12

A Pixel-Parallel State-Propagation Algorithm with Self-Update of Propagation Direction for Subjective Contour Generation Reviewed

H. Sou, T. Morie

Int. Sympo. on Intelligent Signal Processing and Communication Systems (ISPACS 2015) 53 - 56 2015.11

CMOS Circuits and Nanodevices for Spike Based Neural Computing Invited Reviewed

T. Morie

IEEE Int. Meeting for Future of Electron Devices, Kansai 112 - 113 2015.06

More than Mooreでブレークスルーを狙う脳型チップ

森江隆

日本神経回路学会誌 ( Japanese Neural Network Society ) 22 ( 2 ) 51 - 52 2015.01

Morphological Associative Memory Employing a Split Store Method Reviewed

H. Tamukoh, K. Koga, H. Harada, T. Morie

Proc. 21th Int. Conf. on Neural Information Processing (ICONIP2014), (Lecture Notes in Computer Science, LNCS 8836) 3 341 - 348 2014.10

A Chaotic Spiking Oscillator That Acts As a Filter of Spike Trains Reviewed

S. Uenohara, T. Morie

Abs. Collection of the 2014 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2014) 723 - 726 2014.09

A Motion Detection Model Inspired by Hippocampal Function and Its Applications to Obstacle Detection Reviewed

H. Liang, T. Morie

Neurocomputing 129 59 - 66 2014.04

M-HOG 特徴量と色相の共起情報を用いた人検出法 Reviewed

中島佑樹, タンジュークイ, 金亨燮, 森江隆, 石川聖二

バイオメディカル・ファジィ・システム学会誌 16 ( 1 ) 67 - 74 2014.04

Digital Circuit Design of Pulse-coupled Phase Oscillator Systems for Coupled MRF Models Reviewed

Y. Suedomi, H. Tamukoh, M. Tanaka, K. Matsuzaka, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 89 - 92 2014.03

Object Segmentation Using 3D Information Obtained from RGB-D Sensor Reviewed

T. Matsumoto, M. Tanaka, H. Tamukoh, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 377 - 380 2014.03

Sound Quality Improvement of Low Bit Rate Coded Audio Signals with Nonlinear Functions Reviewed

T. Yoshino, Y. Sato, H. Tamukoh, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 237 - 240 2014.03

Robustness to CMOS Device Mismatches of Time-domain Voltage/Current Sampling Circuits for Implementing Large-scale Coupled Nonlinear Dynamical Systems Reviewed

S. Uenohara, D. Atuti, K. Matsuzaka, H. Tamukoh, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 93 - 96 2014.03

Videotaped obstacle extraction from a moving camera Reviewed

10 ( 2 ) 717 - 728 2014.02

Classifying 2D and 3D objects on a road employing the road plane Reviewed

1689 - 1692 2013.12

Parameterized Digital Hardware Design of Pulse-coupled Phase Oscillator Model toward Spike-based Computing Invited Reviewed

Y. Suedomi, H. Tamukoh, M. Tanaka, K. Matsuzaka, T. Morie

Proc. 20th Int. Conf. on Neural Information Processing (ICONIP2013) 2013.11

A PWM-Mode CMOS Threshold-Coupled-Map Circuit Robust to Device Mismatches Reviewed

S. Uenohara, D. Atuti, K. Matsuzaka, H. Tamukoh, T. Morie, K. Aihara

Abs. Collection of the 2013 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2013) 503 - 506 2013.09

Road region estimation and obstacles extraction using a monocular camera Reviewed

9 ( 9 ) 3561 - 3572 2013.07

Experimental Distinction between Chaotic and Strange Nonchaotic Attractors on the Basis of Consistency Reviewed

Uenohara, T. Mitsui, Y. Hirata, T. Morie, Y. Horio, K. Aihara

Chaos 23 ( 2 ) 23110-1 - 23110-9 2013.05

Obstacles extraction using a moving camera Reviewed

7729 LNCS ( PART 2 ) 441 - 453 2013.04

Gabor Features for Real-Time Road Environment Classification Reviewed

L. Mioulet, T. P. Breckon, A. Mouton, H. Liang, T. Morie

Proc. IEEE Int. Conf. on Industrial Technology (ICIT) 1117 - 1121 2013.02

スパイクベース非線形演算のためのCMOS結合位相振動子回路

東原敬, 松坂建治, 西広海, 森江, 隆

電子情報通信学会 NLP研究会 112 ( 389 ) 137 - 142 2013.01

FPGAにより制御される専用アナログチップを用いたスパイキングニューラルネットワークシステムの開発

前田道孝, Frank Maldonado H., 松尾貴之, 田中秀樹, 梁海超, 松坂建治, 森江隆, 合原一幸

電子情報通信学会 NC研究会 112 ( 390 ) 181 - 186 2013.01

電圧・電流波形サンプリング方式によるしきい値結合カオス回路の設計

上ノ原誠二, 厚地泰輔, 松坂建治, 森江隆, 合原一幸

電子情報通信学会 NLP研究会 112 ( 389 ) 105 - 110 2013.01

Obstacles Extraction from a Video Taken by a Moving Camera Reviewed

2012.12

知的センシグデバイスデバイスのための脳型処理モデルを実現するアナログ・ディジタル融合LSI Invited

森江隆, 秦佑輔、西広海、松坂建治

電気学会センサ・マイクロマシン部門大会, 第29回「センサ・マイクロマシンと応用システム」シンポジウム 2012.10

LSI実装に向けたパルス結合位相振動子系に基づくスパイクベース演算

松坂建治, 田中秀樹, 大久保悟, 東原敬, 森江隆

電子情報通信学会 NC研究会 112 ( 227 ) 127 - 132 2012.10

トマト果実自動収穫のためのKinectセンサを利用した果実・萼位置検出手法

栗谷康隆, 田中宙夫, 松原弘樹, 清水昌樹, 森江隆

画像の認識・理解シンポジウム IS1-76 2012.08

A Hierarchical Extension of the HOG Model Implemented in the Convolution-net for Human Detection Reviewed

5 ( 3 ) 54 - 62 2012.08

Biologically-inspired Learning Device using Three-terminal Ferroelectric Memristor Reviewed

275 - 276 2012.06

Bicycle Detection Using Pedaling Movement by Spatiotemporal Gabor Filtering Reviewed

K. Takahashi, Y. Kuriya, T. Morie

Int. J. of innovative Computing Information and Control 8 ( 6 ) 2012.06

Torus-doubling Process via Strange Nonchaotic Attractors Reviewed

376 1907 - 1914 2012.05

画像処理による道路状態・歩行者の認識,

森江隆, 石川聖二, 松岡　悟

光技術コンタクト ( 社団法人日本オプトメカトロニクス協会 ) 50 ( 6 ) 20 - 24 2012.04

強誘電体ゲートトランジスタを用いたシナプス素子におけるSTDP機能の実証

.西谷雄, 金子幸広, 上田路人, 森江隆, 藤井映志

電子情報通信学会 NC研究会 111 ( 483 ) 203 - 207 2012.03

A hierarchical extension of the HOG model implemented in the convolution-net for human detection

2012.02

A Motion Detection Model Inspired by the Neuronal Propagation in the Hippocampus Reviewed

H. Liang, T. Morie

E95-A ( 2 ) 576 - 585 2012.02

Obstacle detection using a moving camera Reviewed

767 - 770 2011.12

Moving objects detection at an intersection by sequential background extraction Reviewed

1752 - 1755 2011.12

Extraction of individual pedestrians employing stereo camera images Reviewed

1744 - 1747 2011.12

Applying HOG feature to the detection and tracking of a human on a bicycle Reviewed

1740 - 1743 2011.12

A 1-D CMOS Pixel Circuit Array Implementing a Region-Based Coupled MRF Model for Coarse Image Region Segmentation Reviewed

210 - 211 2011.12

Analysis of Associative Memory Operation in a VLSI Spiking Neural Network Reviewed

208 - 209 2011.12

Fundamental Study on Spiking Neuron Devices Reviewed

120 - 121 2011.11

A Motion Detection Model Inspired by Hippocampal Function and Its FPGA Implementation Reviewed

H. Liang T. Morie

18th Int. Conf. on Neural Information Processing (ICONIP2011) III ( 7064 ) 522 - 529 2011.11

ナノディスクアレイ構造とCMOS回路を結合したスパイキングニューロンデバイス

梁海超, 森江隆, 孫意来, 五十嵐誠, 寒川誠二

電子情報通信学会ニューロコンピューティング研究会 111 ( 241 ) 125 - 129 2011.10

Detecting a Human Body Direction Using Multiple-HOG Reviewed

First Int. Symp. on Future Active Safety Technology toward zero-traffic-accident (FAST-zero '11) 20117394-1 - 20117394-6 2011.09

Detection of Road Surface Condition Using Gabor Filter Reviewed

First Int. Symp. on Future Active Safety Technology toward zero-traffic-accident (FAST-zero '11) 20117341-1 - 20117341-5 2011.09

脳型情報処理デバイスの現状と今後の展開 Invited

森江隆, 梁海超, 孫意来, 田中秀樹, 五十嵐誠, 寒川誠二

応用物理学会シリコンテクノロジー分科会第140回研究集会 28 - 32 2011.08

A CMOS Nonlinear-Map Circuit Array for Threshold-Coupled Chaotic Maps Using Pulse-Modulation Approach Reviewed

European Conf. on Circuit Theory and Design (ECCTD 2011) 125 - 128 2011.08

Analog CMOS Circuit Implementation of a System of Pulse-Coupled Oscillators for Spike-Based Computation Reviewed

IEEE Int. Symp. on Circuits and Systems (ISCAS 2011) 2849 - 2852 2011.05

画素並列ハードウェアのための曲率を有する主観的輪郭生成アルゴリズム

山口雄一郎,森江隆

電子情報通信学会 NC研究会 110 ( 461 ) 65 - 70 2011.03

大局的画像領域分割のための領域および境界ベース結合MRFモデルを実現するPWM方式画素並列型LSIの設計

秦佑輔,松坂建治,西広海,中田一紀,森江隆

電子情報通信学会 NC研究会 110 ( 461 ) 59 - 64 2011.03

集積回路化を目指した大局的画像領域分割のための領域ベース結合MRFモデル Reviewed

梁海超, 川嶋佑輔, 松坂建治, 中田一紀, 岡田真人, 森江隆

電気学会論文誌C 131 ( 3 ) 567 - 575 2011.03

海馬の神経活動にヒントを得た単眼カメラ映像での動き検出モデルおよびその障害物検知への応用

梁海超,森江隆

電子情報通信学会 ITS研究会, Vol. 110, No. 420, ITS2010-62, pp. 269-274, 2011年2月22日, 北海道大学（札幌） 110 ( 420 ) 269 - 274 2011.02

時空間ガボールフィルタによるペダル漕ぎ運動検出を用いた自転車識別

高橋和志,栗谷康隆,森江隆

電子情報通信学会 ITS研究会 110 ( 420 ) 257 - 262 2011.02

車載カメラ画像のガボールフィルタ処理による自動車前方路面の乾湿判定

田中宙夫,森江隆,松岡悟,岩瀬耕二,山本康典

電子情報通信学会 ITS研究会 110 ( 420 ) 263 - 267 2011.02

Parametric Control in a Region-based Coupled MRF model with Phase Dynamics for Coarse Image Region Segmentation Reviewed

H. Liang,K. Nakada,K. Matsuzaka,T. Morie,M. Okada

The 13th IEEE International Conference on Computational Science and Engineering (CSE 2010) 190 - 195 2010.12

Bicycle Detection Using Pedaling Movement by Spatiotemporal Gabor Filtering Reviewed

K. Takahashi,Y. Kuriya,T. Morie

Int. Tech. Conf. of IEEE Region 10 (TENCON2010) 918 - 922 2010.11

Detecting a Human Body Direction Using a Feature Selection Method Reviewed

Y. Nakashima,J. K. Tan,S. Ishikawa,T. Morie

Proc. of Int. Conf. on Control, Automation and Systems 1424 - 1427 2010.10

集積回路実装に向けた大局的画像領域分割のための領域ベース結合MRFモデルのパラメータ制御

梁海超,松坂建治,中田一紀,岡田真人,森江隆

電子情報通信学会ニューロコンピューティング研究会 110 ( 264 ) 35 - 40 2010.10

Control of Activation Energy for Electron Transport in Two-Dimensional Array of Si Nanodisks Reviewed

M. Igarashi,C. H. Huang,T. Morie,S. Samukawa

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM) 934 - 935 2010.09

Coarse Image Edge Detection Using Self-Adjusting Resistive-Fuse Networks Reviewed

H. Liang,T. Morie

Proc. of 10th Int. Workshop on Pattern Recognition in Information Systems (PRIS 2010) 43 - 52 2010.06

A 2-Dimensional Si Nanodisk Array Structure for Spiking Neuron Models Reviewed

T. Morie,Y. Sun,H. Liang,M. Igarashi,C. Huang,S. Samukawa

IEEE Int. Symp. on Circuits and Systems (ISCAS 2010) 781 - 784 2010.06

Coarse Image Region Segmentation Performance of a Region-based Coupled MRF Model with Improved Evaluation Function Reviewed

K. Nakada,K. Matsuzaka,T. Morie

Fourteenth International Conference on Cognitive and Neural Systems (ICCNS), p. 31, Boston, USA, May 19-22 (May 20), 2010. 31 - 31 2010.05

車載カメラ映像からの横断歩道上の歩行者の検出法 Reviewed

タンジュークイ,三好誠,石川聖二,森江隆

バイオメディカル・ファジィ・システム学会誌 12 ( 1 ) 99 - 103 2010.05

Automatic Detection of Pedestrians from Stereo Camera Images Reviewed

J. K. Tan,K. Inumaru,S. Ishikawa,T. Morie

Artificial Life and Robotics 15 ( 4 ) 459 - 463 2010.04

On Detecting a Human and Its Body Direction from a Video Reviewed

Y. Nakashima,J. K. Tan,S. Ishikawa,T. Morie

Artificial Life and Robotics 15 ( 4 ) 455 - 458 2010.04

HOG特徴量と人マスクを用いた人物および身体方向の検出 Reviewed

中島佑樹,タンジュークイ,石川聖二,森江隆

画像電子学会誌 39 ( 6 ) 1104 - 1111 2010.04

Markerless Arm Posture Estimation Independent of Environment Reviewed

M. Shimizu,I. R. Khan,Y. Kuriya,H. Miyamoto,T. Morie

J. Signal Processing 14 ( 6 ) 475 - 481 2010.04

Coarse Image Region Segmentation in Spatio-Temporal Domain Using a Region-based Coupled MRF Model with Phase Dynamics Reviewed

K. Nakada,K. Matsuzaka,T. Morie

Australian Journal of Intelligent Information Processing Systems 11 ( 2 ) 6 - 11 2010.04

Control of Electron Transport in Two-Dimensional Array of Si Nanodisks for Spiking Neuron Device Reviewed

M. Igarashi,C.-H. Huang,T. Morie,S. Samukawa

Appl. Phys. Express 3 085202 - 085202 2010.04

Markerless Arm Posture Estimation Independent of Environment Reviewed

M. Shimizu,I. R. Khan,Y. Kuriya,H. Miyamoto,T. Morie

RISP 2010 Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'10) 2010.03

On Detecting a Human and Its Body Direction from a Video Reviewed

Y. Nakashima,J. K. Tan,S. Ishikawa,T. Morie

Int. Symp. on Artificial Life and Robotics (AROB 15th '10) #GS2-5 294 - 297 2010.02

Automatic Detection of Pedestrians from Stereo Camera Images Reviewed

K. Inumaru,J. K. Tan,S. Ishikawa,T. Morie

Int. Symp. on Artificial Life and Robotics (AROB 15th '10) #GS9-4 1018 - 1021 2010.02

しきい値処理により結合されたカオス力学系のパルス変調方式CMOS回路実現,

井福一毅,厚地泰輔,森江隆,堀尾喜彦,合原一幸

電子情報通信学会非線形問題研究会, NLP2009-154 109 ( 366 ) 65 - 70 2010.01

画素並列型異方性拡散LSIとそれを用いてエッジ補完を行う画像処理システム,

財津賢一郎,金永宰,栗谷康隆,森江隆

映像情報メディア学会技術報告情報センシング研究会 33 ( 56 ) 17 - 20 2009.12

A Simplified Region-Based Coupled MRF Model for Coarse Image Region Segmentation Toward its VLSI Implementation, Reviewed

K. Matsuzaka,T. Morie

Proc. of Int. Symp. on Nonlinear Theory and its Applications (NOLTA2009) 202 - 205 2009.10

Video Monitoring of Slope Failure Using Spatiotemporal Gabor Filtering Reviewed

K. Okamoto,T. Watanabe,H. Ban,Y. Maeda,A. Hanazawa,T. Morie

Proc. of the 2009 IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC2009) 986 - 991 2009.10

New Functional Device Characteristics with 2-Dimensional Array of Si Nanodisks Fabricated by Combination of Bio-Template and Ultimate Top-down Etching Reviewed

M. Igarashi,C. H. Huang,M. Tomura,M. Takeguchi,S. Horita,Y. Uraoka,T. Fuyuki,I. Yamashita,T. Morie,S. Samukawa

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM) 1364 - 1365 2009.08

A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function, Reviewed

H. Tanaka,T. Morie,K. Aihara

IEICE Trans. Fundamentals E92-A ( 7 ) 2009.07

Coarse Image Region Segmentation Using Region- and Boundary-based Coupled MRF Models and Their PWM VLSI Implementation Reviewed

Y. Kawashima,D. Atuti,K. Nakada,M. Okada,T. Morie

Proc. Int. Joint Conf. on Neural Networks (IJCNN 2009) 1559 - 1565 2009.06

A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach, Reviewed

D. Atuti,T. Morie,K. Aihara

IEICE Trans. Fundamentals E92-A ( 5 ) 1308 - 1315 2009.05

パルス変調方式を用いた電流サンプリング型CMOS任意カオス生成回路,

厚地泰輔,森江隆,合原一幸

電気学会電子回路研究会, ECT-09-19, 25 - 30 2009.01

時空間ガボールフィルタによる土砂災害前兆現象検知

岡本健,渡辺敏雄,花沢明俊,森江隆,伴弘司,前田裕二

電子情報通信学会パターン認識・メディア理解研究会, PRMU2008-131 108 ( 327 ) 139 - 144 2008.11

A Prototype System for Secure Human-Machine Interaction Based on Face and Gesture Recognition, Reviewed

I..R. Khan,T. Morie,H. Miyamoto,M. Shimizu,and Y. Kuriya

The 34th Annual Conf. of the IEEE Industrial Electronics Society (IECON'08), 1572 - 1577 2008.11

時間領域情報処理による脳型集積システム

森江隆,田中秀樹,厚地泰輔,是角圭祐,中田一紀

電子情報通信学会ニューロコンピューティング研究会, NC2008-68 108 ( 281 ) 55 - 60 2008.11

MOSFETのしきい値電圧の温度依存性を利用した温度補償電流源回路とその応用,

中島規成,森江隆

電気学会C部門電子回路研究会, ECT-08-64 1 - 5 2008.10

Face and Arm-Posture Recognition for Secure Human-Machine Interaction Reviewed

I. R. Khan,T. Morie,H. Miyamoto

IEEE Int. Conf. on Systems, Man and Cybernetics (SMC2008) 411 - 417 2008.10

CMOS Pulse-Modulation Circuit Implementation of Phase-Locked Loop Neural Networks, Reviewed

D. Atuti,K. Nakada,T. Morie

IEEE Int. Symp. on Circuits and Systems (ISCAS2008) 2174 - 2177 2008.05

領域ベース結合MRFモデルによる大局的画像領域分割とCMOS回路実現

川嶋佑輔,厚地泰輔,中田一紀,岡田真人,森江隆

電子情報通信学会ニューロコンピューティング研究会, NC2007-120 107 ( 542 ) 49 - 54 2008.03

パルス変調方式による相互結合位相振動子のCMOS 回路実現と評価

厚地泰輔,加藤直人,中田一紀,森江隆

電気学会電子回路研究会 25 - 29 2007.12

STDPを有するCMOSスパイキングニューラルネットワークLSIの評価

田中秀樹,森江隆,合原一幸

電子情報通信学会ニューロコンピューティング研究会, NC2007-61 107 ( 328 ) 37 - 42 2007.11

Projection-field-type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach Reviewed

O. Nomura,T. Morie

Neural Information Processing (Lecture Notes in Computer Science, Springer Berlin/Heidelberg 4984/2008 1081 - 1090 2007.11

Projection-field-type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach Reviewed

O. Nomura,T. Morie

14th Int. Conf. on Neural Information Processing (ICONIP2007) 196 - 196 2007.11

Brain-inspired Visual Processing: Real-time Face Authentication, arm Posture Recognition, and Shadow Elimination Reviewed

T. Morie,H. Miyamoto,A. Hanazawa,I. R. Khan,T. Kamada,Y. Kuriya,and M. Shimizu

4th Int. Conf. on Brain-Inspired Information Technology (BrainIT2007) 33 - 33 2007.11

An FPGA-based Collision Warning System Using Hybrid Approach Reviewed

H. Liang,T. Morie,Y. Suzuki,K. Nakada,T. Miki,H. Hayashi

7th Int. Conf. on Hybrid Intelligent Systems (HIS07) 30 - 35 2007.09

CMOS Circuit Implementation of a Coupled Phase Oscillator System Using Pulse Modulation Approach Reviewed

D. Atuti,N. Kato,K. Nakada,T. Morie

2007 European Conference on Circuit Theory and Design (ECCTD 2007) 827 - 830 2007.08

A Pulse-Modulation Circuit for Nonlinear Systems with Self Regulatory Threshold Dynamics Reviewed

D. Atuti,T. Morie,K. Aihara

15th IEEE Int. Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2007) 145 - 148 2007.07

Evaluation of a CMOS Spiking Neural Network Circuit with STDP Function Reviewed

H. Tanaka,T. Morie,K. Aihara

15th IEEE Int. Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2007) 313 - 316 2007.07

A Cellular-Automaton-Based Anisotropic Diffusion Algorithm for Subjective Contour Generation and Its Digital VLSI Implementation Reviewed

T. Morie,T. Yamamoto

Accepted for presentation at 2007 Conference on Unconventional Computing (UC 2007) 2007.07

Design of a CMOS Pixel Circuit for Coarse Region Segmentation/Extraction Based on Merged Analog/Digital Architecture Reviewed

N. Kato,T. Morie

J. Signal Processing 11 ( 4 ) 317 - 320 2007.07

Digital VLSI Architecture for Image Matching Based on 2D Cross-correlation Reviewed

M. Mitarai,K. Korekado,T. Morie

J. Signal Processing 11 ( 4 ) 345 - 348 2007.07

An Element Circuit for Nonlinear Dynamical Systems Using Phase Variables Reviewed

D. Atuti,T. Morie,T. Nakano,K. Nakada

Brain-Inspired IT III, International Congress Series 1301 156 - 159 2007.07

A CMOS Circuit for STDP with a Symmetric Time Window Reviewed

H. Tanaka,T. Morie,K. Aihara

Brain-Inspired IT III, International Congress Series 1301 152 - 155 2007.07

Moving Object Detection Algorithm Inspired by the Sequence Detection in the Hippocampus and its Digital LSI Implementation Reviewed

H. Hayashi,K. Nakada,T. Morie

Brain-Inspired IT III, International Congress Series 1301 35 - 38 2007.07

Brain-inspired Visual Processing for Robust Gesture Recognition Reviewed

T. Morie,H. Miyamoto,A. Hanazawa

Brain-Inspired IT III, International Congress Series 1301 31 - 34 2007.07

Digital VLSI Implementation of a Moving Object Detection Algorithm Based on Neuronal Propagation in the Hippocampus Reviewed

H. Liang,H. Nakayama,K. Nakada,T. Morie,H. Hayashi

International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2006) 614 - 617 2006.12

A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms Reviewed

D. Atuti,T. Morie,K. Aihara

IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS 2006) 1961 - 1965 2006.12

アナログ・デジタル融合回路方式による主観的輪郭生成のための画素並列型CMOS異方性拡散回路

金永宰,森江隆

電子情報通信学会ニューロコンピューティング研究会 106 ( 341 ) 31 - 36 2006.11

A CMOS Circuit for STDP with a Symmetric Time Windoww Reviewed

H. Tanaka,T. Morie,K. Aihara

Abst. of The 3rd Int. Conf. on Brain-Inspired Information Technology (BrainIT2006) 65 - 65 2006.09

An Element Circuit for Nonlinear Dynamical Systems Using Phase Variables Reviewed

D. Atuti,T. Morie,T. Nakano,K. Nakada

Abst. of The 3rd Int. Conf. on Brain-Inspired Information Technology (BrainIT2006) 66 - 66 2006.09

Brain-inspired Visual Processing for Robust Gesture Recognition Reviewed

T. Morie,H. Miyamoto,A. Hanazawa

Abst. of The 3rd Int. Conf. on Brain-Inspired Information Technology (BrainIT2006) 31 - 31 2006.09

A Real-time Image Processing System Using a Gabor-filtering LSI Realizing Primary Visual Cortex Functions Reviewed

S. Nagano,T. Morie,T. Nakano,K. Nakamura

Joint 3rd Int. Conf. on Soft Computing and Intelligent Systems and 7th Int. Symp. on Advanced Intelligent Systems (SCIS & ISIS 2006) 516 - 519 2006.09

A CMOS Synapse with STDP Function and Its Application to Hopfield-type Associative Memory Reviewed

H. Tanaka,T. Morie,K. Aihara

Int. Symp. on Nonlinear Theory and its Applications (NOLTA2006) 495 - 498 2006.09

An FPGA-based Real-time Scene-image Recognition System Using Relationship between Coarsely Segmented Regions Reviewed

T. Morie,T. Nakano

Int. Symp. on Artificial Brain with Emotion and Learning (ISABEL 2006) - Bio-Inspired Models and Hardware for Brain-like Intelligent Functions - 158 - 158 2006.08

A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory Reviewed

K. Sasaki,T. Morie,A. Iwata

IEICE Transactions on Electronics E89-C ( 11 ) 1637 - 1644 2006.04

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model based on a Merged/Mixed Analog-Digital Architecture Reviewed

O. Nomura,T. Morie,K. Korekado,T. Nakano,M. Matsugu,A. Iwata

IEICE Transactions on Electronics E89-C ( 6 ) 781 - 791 2006.04

A Pixel Circuit Implementing an Anisotropic Diffusion Algorithm for Subjective Contour Generation Using Merged Analog-Digital circuit Approach Reviewed

Y. Kim,T. Morie

J. Signal Processing 10 ( 4 ) 259 - 262 2006.04

An Image Recognition Algorithm Using Relationships between Segmented Coarse Regions Reviewed

T. Nakano,T. Morie

Brain-Inspired IT II, International Congress Series 1291 241 - 244 2006.04

An Analog CMOS Circuit for Spiking Neuron Models Reviewed

H. Tanaka,T. Morie,K. Aihara

Brain-Inspired IT II, International Congress Series 1291 217 - 220 2006.04

Subjective Contour Generation Using a Pixel-parallel Anisotropic Diffusion Algorithm Reviewed

Y. Kim,T. Morie

Brain-Inspired IT II, International Congress Series 1291 241 - 244 2006.04

Face Position Detection by a Convolutional Neural Network Using an Image Filtering Processor VLSI Reviewed

K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata

Brain-Inspired IT II, International Congress Series 1291 253 - 256 2006.04

Digital VLSI Architecture for Image Matching Based on 2D Cross-correlation Reviewed

M. Mitarai,K. Korekado,T. Morie

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 277 - 280 2006.03

An FPGA-based Real-time Moving-object Detection System Based on Neuronal Propagation in the Hippocampus Reviewed

H. Liang,T. Morie,H. Nakayama,K. Nakada,H. Hayashi

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 509 - 512 2006.03

Design of an 2D Image Matching Processor LSI Based on Merged Analog/Digital Architecture Reviewed

M. Sakai,T. Morie,M. Mitarai,K. Korekado

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 81 - 84 2006.03

Design of a CMOS Pixel Circuit for Coarse Region Segmentation/Extraction Based on Merged Analog/Digital Architecture Reviewed

N. Kato,T. Morie

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 89 - 92 2006.03

A Pixel Circuit Implementing an Anisotropic Diffusion Algorithm for Subjective Contour Generation Using Merged Analog-Digital circuit Approach Reviewed

Y. Kim,T. Morie

2006 RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'06) 2006.03

FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation Reviewed

T. Nakano,T. Morie,H. Ishizu,H. Ando,A. Iwata

Intelligent Automation and Soft Computing 12 ( 3 ) 307 - 316 2006.03

顔／物体認識のためのElastic Graph MatchingのFPGA実装とその性能評価

中野鉄平,森江隆

電子情報通信学会ニューロコンピューティング研究会 25 - 30 2005.11

Associative Memory Operation in a Hopfield-type Spiking Neural Network with Modulation of Resting Membrane Potential Reviewed

H. Tanaka,T. Morie,K. Aihara

2005 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2005) 313 - 316 2005.10

An Image Recognition Algorithm Using Coarse Region Segmentation and Relationship between the Regions Reviewed

T. Nakano,T. Morie

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 81 - 81 2005.10

Subjective Contour Generation Using a Pixel-parallel Anisotropic Diffusion Algorithm Reviewed

Y. Kim,T. Morie

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 94 - 94 2005.10

An Analog CMOS Circuit for Spiking Neuron Models Reviewed

H. Tanaka,T. Morie,K. Aihara

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 2005.10

Face Position Detection Using an Image Filtering Processor VLSI Reviewed

K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 86 - 86 2005.10

A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Reviewed

D. Atuti,T. Morie,K. Aihara

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 73 - 73 2005.10

A Convolutional Neural Network VLSI Architecture Using Sorting Algorithm Reviewed

O. Nomura,T. Morie,K. Korekado,M. Matsugu,A. Iwata

Int. Conf. on Advances in Natural Computation (ICNC'05) 1006 - 1014 2005.08

A Gabor Filtering VLSI Processor Mimicking a Primary Visual Cortex Function Reviewed

T. Morie,K. Nakamura,K. Korekado

Post-IJCNN2005 Workshop, Biologically-Inspired Models and Hardware for Human-like Intelligent Functions (BIMH2005) 2005.08

A Digital LSI Architecture of Elastic Graph Matching and Its FPGA Implementation Reviewed

T. Nakano,T. Morie

Proc. Int. Joint Conference on Neural Networks (IJCNN05) 689 - 694 2005.07

AD融合／混載アーキテクチャによる顔・物体認識のための画像フィルタリングプロセッサ

是角圭祐,森江隆,野村修,中野鉄平,真継優和,岩田穆

電子情報通信学会集積回路研究会 19 - 24 2005.07

V1単純細胞の機能を模倣するガボールフィルタLSIの評価

中村享平,是角圭祐,森江隆

電子情報通信学会ニューロコンピューティング研究会 17 - 22 2005.06

An Image Filtering Processor for Face/Object Recognition Using Merged/Mixed Analog-Digital Architecture Reviewed

K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata

2005 Symposium on VLSI Circuits 220 - 223 2005.06

A Pixel-parallel Anisotropic Diffusion Algorithm for Subjective Contour Generation Reviewed

Y. Kim,T. Morie

IEEE Int. Symp. on Circuits and Systems (ISCAS2005) 4237 - 4240 2005.05

A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation Reviewed

T. Nakano,T. Morie,M. Nagata,A. Iwata

J. Robotics and Mechatronics 17 ( 4 ) 378 - 386 2005.04

投射野型積和演算及び荷重基底分解アルゴリズムを用いたConvolutional Neural Network VLSI アーキテクチャ

野村修,森江隆,是角圭祐,真継優和,岩田穆

電子情報通信学会ニューロコンピューティング研究会 25 - 29 2004.11

主観的輪郭生成のための画素並列型異方性拡散アルゴリズム

金永宰,森江隆

映像情報メディア学会技術報告 41 - 44 2004.10

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition Reviewed

O. Nomura,T. Morie,K. Korekado,M. Matsugu,and A. Iwata

Int. Conf. on Knowledge-Based Intelligent Information and Engineering Systems (KES'2004) 995 - 1001 2004.09

A Face/Object Recognition System Using Coarse Region Segmentation and Dynamic-Link Matching Reviewed

T. Morie,T. Nakano

Brain-Inspired IT I, International Congress Series 1269 177 - 180 2004.09

Hardware Modeling and Design of Brain-like Information Systems Reviewed

T. Miki,T. Morie,and T. Yamakawa

Joint 2nd Int. Conf. on Soft Computing and Intelligent Systems and 5th Int. Symposium on Advanced Intelligent Systems (SCIS & ISIS 2004) 2004.09

AD融合回路方式による画素並列型ガボールフィルタLSI

森江隆,梅澤淳,岩田穆

電子情報通信学会信学技報 2004.08

A Spiking Neural Network with Negative Thresholding and Its Application to Associative Memory Reviewed

K. Sasaki,T. Morie,and A. Iwata

2004 IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS2004) IIー89 - IIIー92 2004.07

Gabor Filtering Using Cellular Neural Networks and its Application to Face/Object Recognition Reviewed

T. Morie,T. Nakano,J. Umezawa,and A. Iwata

World Automation Congress 2004.07

A Pixel-Parallel Image Processor for Gabor Filtering Based on Merged Analog-Digital Architecture Reviewed

T. Morie,J. Umezawa,and A. Iwata

2004 Symposium on VLSI Circuits 212 - 213 2004.06

Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps Reviewed

T. Morie,K Murakoshi,M Nagata,A. Iwata

IEICE Trans. Electron. E87-C ( 11 ) 1856 - 1862 2004.04

A VLSI Convolutional Neural Network for Image Recognition Using Merged/Mixed Analog-Digital Architecture Reviewed

K. Korekado,T. Morie,O. Nomura,H. Ando,T. Nakano,M. Matsugu,A. Iwata

J. Intelligent & Fuzzy Systems 15 ( 3/4 ) 173 - 179 2004.04

Gabor-Type Filtering Using Transient States of Cellular Neural Networks Reviewed

T. Morie,J. Umezawa,A. Iwata

Intelligent Automation and Soft Computing 10 ( 2 ) 95 - 104 2004.04

A Face/Object Recognition System Using Coarse Region Segmentation and Dynamic-Link Matching Reviewed

T. Morie,T. Nakano

Brain-Inspired IT I, International Congress Series 1269 177 - 180 2004.04

A Face/Object Recognition System Using Coarse Region Segmentation and Dynamic-Link Matching Reviewed

T. Morie,T. Nakano

International Symposium on Bio-Inspired Systems, Part IV, Brain-inspired Information Technology (BrainIT 2004) 2004.03

抵抗ネットワークの過渡状態を利用するガボール型フィルタ回路

森江隆,梅澤淳,岩田穆

電子情報通信学会信学技報 13 - 18 2003.11

減衰シナプスを導入したスパイキングニューロンによるホップフィールドネットワークを用いた高速連想メモリ

佐々木寛弥,森江隆,岩田穆

電子情報通信学会信学技報 55 - 60 2003.11

A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture Reviewed

K. Korekado,T. Morie,O. Nomura,H. Ando,T. Nakano,M. Matsugu,A. Iwata

Knowledge-Based Intelligent Information and Engineering Systems (KES2003) 2 169 - 176 2003.09

A Face/Object Recognition System Using FPGA Implementation of Coarse Region Segmentation Reviewed

T. Nakano,T. Morie,and A. Iwata

SICE Annual Conference 2003 1418 - 1423 2003.08

Coarse Image Region Segmentation Using Resistive-fuse Networks Implemented in FPGA Reviewed

T. Nakano,H. Ando,H. Ishizu,T. Morie,A. Iwata

The 7th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2003) Proceedings IV 186 - 191 2003.07

A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models Reviewed

T. Morie,T. Matsuura,M. Nagata,A. Iwata

IEEE Transactions on Nanotechnology 2 ( 3 ) 158 - 164 2003.04

Pulse Modulation VLSI Implementation of Clustering Algorithm Based on Stochastic Association Model Reviewed

T. Morie,T. Matsuura,A. Iwata

Artificial Neural Networks and Neural Information Processing ICANN/ICONIP 2003 International Conference Supplementary Proceedings 434 - 437 2003.04

大局的画像領域分割のためのデジタル方式抵抗ヒューズネットワークの設計とFPGAへの実装

中野鉄平,森江隆,安藤博士,石津任章,岩田穆

電子情報通信学会技術研究報告(ICD) 2003.03

パルスタイミングに基づくスパイキングホップフィールドネットワークによる高速連想メモリ

佐々木寛弥,森江隆,伊井慎一郎,岩田穆

電子情報通信学会技術研究報告(NC) 2002.11

A Cellular-Automaton-Type Image Extraction Algorithm and Its Implementation Using an FPGA Reviewed

T. Nakano,T. Morie,M. Nagata,A. Iwata

Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems 2 197 - 200 2002.10

自律移動ロボット用のビジョンシステムと画素選択処理機能を有する並列マッチングプロセッサの開発

山本美子,武田幹雄,渡部悠紀,岩田穆,森江隆,渡邊睦

電子情報通信学会技術研究報告（DSP,ICD,IE） 2002.10

画像処理IPとFPGA実装

石津任章,武田幹雄,馬場祥宏,佐野誠,藤原義也,原正純,森江隆,岩田穆

電子情報通信学会技術研究報告（DSP,ICD,IE） 2002.10

An Image Region Extraction LSI Based on a Merged/Mixed-Signal Nonlinear Oscillator Network Circuit Reviewed

H. Ando,T. Morie,M. Nagata,A. Iwata

28th European Solid-State Circuits Conference 703 - 706 2002.09

適応型CMOSイメージセンサ

今村俊文,山本美子,岩田穆,石津任章,森江隆

電子情報通信学会技術研究報告(ICD) 2002.09

An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing Reviewed

K. Katayama,M. Nagata,T. Morie,A. Iwata

IEICE Transactions on Electronics E85-C ( 8 ) 1596 - 1603 2002.08

A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models Reviewed

T. Morie,T. Matsuura,M. Nagata,A. Iwata

2002 IEEE Silicon Nanoelectronics Workshop 53 - 54 2002.06

A Multi-Nano-Dot Circuit and Structure Using Thermal-Noise Assisted Tunneling for Stochastic Associative Processing Reviewed

T. Morie,T. Matsuura,M. Nagata,A. Iwata

Journal of Nanoscience and Nanotechnology 2 ( 3 ) 343 - 349 2002.06

Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits Reviewed

M. Nagata,T. Morie,A. Iwata

IEEE 2002 Custom Integrated Circuit Conference 501 - 504 2002.05

Image Segmentation/Extraction Using Nonlinear Cellular Networks and their VLSI Implementation Using Pulse-Modulation Techniques Reviewed

IEICE Trans. Fundamentals E85-A ( 2 ) 381 - 388 2002.04

An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures Reviewed

T. Morie,T. Matsuura,M. Nagata,and A. Iwata

Advances in Neural Information Processing Systems 14,MIT Press 1115 - 1122 2002.04

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models Reviewed

M. Nagata,Y. Murasaka,Y. Nishimori,T. Morie,and A. Iwata

Proc. 7th Asia and South Pacific Design Automation Conference 71 - 76 2002.04

アナログ・ディジタル融合回路による視覚情報処理アーキテクチャ（特別招待論文）

岩田穆,森江隆

電子情報通信学会信学技報 2002.04

Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits Reviewed

IEEE Journal of Solid-State Circuits 36 ( 3 ) 539 - 549 2001.04

Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications Reviewed

IEICE Transactions on Fundamentals E84-A ( 2 ) 486 - 496 2001.04

A PWM Analog Memory Programming Circuit for Floating-Gate MOSFETs with 75us Programming Time and 11b Updating Resolution Reviewed

IEEE Journal of Solid-State Circuits 36 ( 8 ) 1286 - 1290 2001.04

A CMOS Stochastic Associative Processor Using PWM Chaotic Signals Reviewed

IEICE Trans. Electronics E84-C ( 12 ) 1723 - 1729 2001.04

Test Circuits for Substrate Noise Evaluation in CMOS Digital ICs Reviewed

Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC2001) 13 - 14 2001.04

A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation Reviewed

Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials(SSDM2001) 90 - 91 2001.04

Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies Reviewed

Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials (SSDM2001) 88 - 89 2001.04

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation Reviewed

Proceedings of International Symposium on Quality Electronic Design (ISQED2001) 482 - 487 2001.04

Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits Reviewed

Symposium on VLSI Circuits 159 - 162 2001.04

Design of a Pixel-Parallel Feature Extraction VLSI System for Biologically-Inspired Object Recognition Methods Reviewed

Proc. International Symposium on Nonlinear Theory and its Application (NOLTA2001) 371 - 374 2001.04

A Nonlinear Oscillator Network for Gray-level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation Reviewed

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E83-A ( 2 ) 329 - 336 2000.04

Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment Reviewed

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19 ( 6 ) 671 - 678 2000.04

Wafer-assisted Repair of Plasma-induced damage in the Silicon/Silicon-dioxide System Reviewed

Journal of Vacuum Science & Technology B 18 ( 3 ) 1268 - 1275 2000.04

CMOS Circuits Generating Arbitrary Chaos by Using Pulse Width Modulation Techniques Reviewed

IEEE Transactions on Circuits and Systems-I 47 ( 11 ) 1652 - 1657 2000.04

Quantum Dot Structures Measuring Hamming Distance for Associative Memories Reviewed

Superlattices & Microstructures 27 ( 5/6 ) 613 - 616 2000.04

A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors Reviewed

Nanotechnology 11 ( 3 ) 154 - 160 2000.04

A Smart Imager for the Vision Processing Front-end Reviewed

Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC2000) 19 - 20 2000.04

Reduced Substrate Noise Digital Design for Improving Embedded Analog Performance Reviewed

2000 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC2000) 224 - 225 2000.04

A Multi-Functional Cellular Neural Network Circuit Using Pulse Modulation Signals for Image Recognition Reviewed

Proceedings of 7th International Conference on Neural Information Processing (ICONIP-2000) 613 - 617 2000.04

A High-Resolution Hadamard Transform Circuit Using Pulse Width Modulation Technique Reviewed

Extended Abstracts of the 2000 InternationalConference on Solid State Devices and Materials (SSDM2000) 366 - 367 2000.04

A Multi-Quantum-Dot Associative Circuit Using Thermal-Noise Assisted Tunneling Reviewed

Extended Abstracts of the 2000 InternationalConference on Solid State Devices and Materials (SSDM2000) 306 - 307 2000.04

Quantitative Characterization of Substrate Noise for Physical Design Guides in Digital Circuits Reviewed

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (CICC2000) 95 - 98 2000.04

Pulse Modulation Circuit Architecture and its Application to Functional Image Sensors Reviewed

Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS2000) Ⅱ 301 - 304 2000.04

Quantum Dot Structures Measuring Hamming Distance for Associative Memories Reviewed

Extended Abstracts, 4th International Workshop on Quantum Functional Devices (QFD2000) 210 - 213 2000.04

Image Object Extraction using Resistive-Fuse and Oscillator Networks and a Pulse-Modulation Circuit for their LSI Implementation Reviewed

Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials (SSDM2000) 368 - 369 2000.04

An Arbitrary Chaos Generator Core Circuit Using PWM/PPM Signals Reviewed

Proceedings of the Asia and South Pacific Design Automation Conference(ASP-DAC2000) 23 - 24 2000.04

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique Reviewed

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E82-A ( 2 ) 356 - 363 1999.04

The Architecture of Delta Sigma Analog-to-Digital Converter using Voltage-Controlled Oscillator as a Multibit Quantizer Reviewed

IEEE Transactions on Circuits and Systems-II 46 ( 7 ) 941 - 945 1999.04

New Non-Volatile Analog Memory Circuits Using PWM Methods Reviewed

IEICE Transactions on Electronics E82-C ( 9 ) 1655 - 1661 1999.04

Analog LSI Implementation of Self-Learning Neural Networks Reviewed

Computers and Electrical Engineering 25 ( 5 ) 339 - 355 1999.04

Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment Reviewed

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (CICC'99) 575 - 578 1999.04

A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation Reviewed

Extended Abstracts of the 1999 InternationalConference on Solid State Devices and Materials (SSDM'99) 98 - 99 1999.04

A Nonlinear Oscillator Network Circuit for Image Segmentation with Double-threshold Phase Detection Reviewed

9th International Conference on Artificial Neural Networks(ICANN'99) 655 - 660 1999.04

Nonlinear Dynamical Systems Utilizing Pulse Modulation Signals and A CMOS Chip Generating Arbitrary Chaos Reviewed

Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-inspired Systems (MicroNeuro'99) 254 - 260 1999.04

A Stochastic Association Circuit Using PWM Chaotic Signals Reviewed

Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials (SSDM'99) 100 - 101 1999.04

A Smart CMOS Imager with Pixel Level PWM Signal Processing Reviewed

1999 Symposium on VLSI Circuits Digest of Technical Papers 141 - 144 1999.04

A Stochastic Associative Memory Using Single-Electron Tunneling Devices Reviewed

IEICE Transactions on Electronics E81-C ( 1 ) 30 - 35 1998.04

Pulse Modulation Circuit Techniques for Nonlinear Dynamical Systems Reviewed

Proceedings 1998 International Symposium on Nonlinear Theory and its Application (NOLTA'98) 447 - 450 1998.04

Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation Reviewed

Proceedings of the 5th International Conference on Neural InformationProcessing (ICONIP'98) 582 - 585 1998.04

An Architecture of Delta-Sigma A-to-D Converters using a Voltage Controlled Oscillator as a Multi-bit Quantizer Reviewed

Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'98) I 389 - 392 1998.04

Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Methods Reviewed

Proceedings of the 5th International Conference on Neural Information Processing (ICONIP'98) 586 - 589 1998.04

LSI Implementation of Neural Networks Using A Pulse-Width Modulation Method Reviewed

Proceedings of the 5th International Conference on Soft Computing and Information/Intelligent Systems (IIZUKA'98) 118 - 121 1998.04

Stochastic Associative Memory Using Single-Electron Devices and Its Application to Digit Pattern Association Reviewed

Extended Abstracts of the 1998 International Conference on Solid State Devices and Materials (SSDM'98) 190 - 191 1998.04

Novel Line-Test Methods Using A Subscriber Line Interface Circuit

Electronics and Communications in Japan, Part 1 81 ( 1 ) 22 - 30 1998.04

Nonlinear function generators and chaotic signal generators using a pulse-width modulation method Reviewed

Electronics Letters 33 ( 16 ) 1351 - 1352 1997.04

Self-Learning Neural Network LSI with High-Resolution Non-Volatile Analog Memory Reviewed

Proceedings International Conference on Neural Networks (ICNN'95) IV 1628 - 1632 1995.04

Analog LSI Implementation of Self-Learning Neural Networks Reviewed

Proceedings of the 3rd International Conference on Fuzzy Logic, Neural Nets and Soft Computing (IIZUKA'94) 565 - 566 1994.04

Analog VLSI Implementation of Adaptive Algorithms by an Extended Hebbian Synapse Circuit Reviewed

Proceedings of Third Australian Conference on Neural Networks (ACNN'92) 21 - 24 1992.04

A Submicrometer Megabit DRAM Process Technology Using Trench Capacitors Reviewed

IEEE J. Solid-State Circuits SC-20 ( 1 ) 130 - 136 1985.04

Electrical Characteristics of Isolation-Merged Vertical Capacitor (IVEC) Cell Reviewed

1985 Symposium on VLSI Technology Digest of Technical Papers 88 - 89 1985.04

Trench Coverage Characteristics of Polysilicon Deposited by Thermal Decomposition of Silane Reviewed

Japanese Journal of Applied Physics 23 ( 7 ) L482 - L484 1984.04

An Isolation-merged Vertical Capacitor Cell for Large Capacity DRAM Reviewed

Proceedings of the International Electron Device Meeting (IEDM'84) 240 - 243 1984.04

Depletion Trench Capacitor Technology for Megabit Level MOS dRAM Reviewed

IEEE Electron Device Letters 4 ( 11 ) 411 - 414 1983.04

Depletion Trench Capacitor Cell Reviewed

Extended Abstracts of 15th Conference Solid State Devices and Materials (SSDM'83) 253 - 256256 1983.04

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Papers - MORIE Takashi