研究者詳細 - 中村　和之

論文 - 中村　和之

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Differential signal balancer embedded in silicon LSI as smallest common-mode filter combined bifilar coupling inductors and stacked delay lines 査読有り国際誌

Masaaki Kameya, Eishi Gofuku and Kazuyuki Nakamura

Japanese Journal of Applied Physics 61 ( SC1079 ) SC1079-1 - SC1079-7 2022年03月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

The new differential signal balancer embedded in the metal wiring layer of silicon LSI having increased wiring density and improved characteristics is developed. An internal delay line circuit is stacked vertically to obtain a larger delay time than the extended horizontally structure, and the two inductors for common-mode noise rejection are configured with a stacked bifilar winding structure to obtain higher effective coupling and lower parasitic resistance. Compared to the previous design, the common-mode rejection ratios at 2.4 GHz and 5.4 GHz have been improved by 4.0 dB and 4.6 dB in a smaller area of 120 × 230 μm2, respectively.

DOI： 10.35848/1347-4065/ac5290

Kyutacar

Scopus

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Impact of Differential-mode Noise Converted from External RF Noise on Differential Transmission and its Reduction by Differential Signal Balancer 査読有り国際誌

Kameya M., Gofuku E., Nakamura K.

Asia-Pacific Microwave Conference Proceedings, APMC 2022-November 202 - 204 2022年01月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The impact of differential-mode noise converted from RF noise applied to the differential transmission line channel (DTLC) due to the common-mode filter (CMF) and glass cloth in the DTLC substrate is analyzed. The differential mode noise generated in DTLC with CMF is measured with a 4-port network analyzer. Based on this measurement result, the influence of glass cloth is incorporated into the electromagnetic simulation model of DTLC. By applying this DTLC model to circuit analysis, the suitability of various CMFs as solutions for RF interference is evaluated.

Scopus

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Noise Reduction Termination for RFI Induced Channel Resonance using Common-mode Choke and Differential Signal Balancer 査読有り国際誌

Masaaki Kameya, Eishi Gofuku, Kazuyuki Nakamura

2021 IEEE CPMT Symposium Japan, ICSJ 2021 180 - 183 2021年10月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Kyoto 2021年11月10日 - 2021年11月12日

The impact of the channel resonance due to the external RF noise is analyzed for the differential transmission line sandwiched between the common-mode filters (CMFs). The channel resonance causes a differential noise by the mode conversion. We confirm that the problem of the channel resonance can be removed by the differential signal balancer embedded in the metal layer of silicon LSI (DSB-EIM). The combination of DSB-EIM and a common-mode choke coil (CMC) can effectively remove external RF noise.

DOI： 10.1109/ICSJ52620.2021.9648895

Kyutacar

Scopus

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Differential Signal Balancer Embedded in Silicon LSI with Bifilar Coupling Inductors and Stacked Delay Lines 査読有り

Masaaki Kameya, Eishi Gofuku, Kazuyuki Nakamura

International Conference on Solid State Devices and Materials(SSDM) C-5-03 2021年09月

Compact differential signal balancer embedded in metal wiring layers of silicon LSI for common mode noise filtering 査読有り

Masaaki Kameya, Yang-Min Chang, Eishi Gofuku and Kazuyuki Nakamura

Japanese Journal of Applied Physics 59 ( SG ) SGGC01-11 - SGGC01-7 2020年02月

担当区分：責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

The differential signal balancer (DSB) is a discrete common mode filter component using a low temperature co-fired ceramic (LTCC) process in which non-magnetic materials are employed. In this paper, we have developed the new DSB embedded in metal wiring layers of silicon LSI for achieving the multiple ultra-high-speed differential transmission exceeding 10 Gb s-1 between LSIs. While the spiral inductors in the silicon CMOS process are affected by the substrate loss and conductor resistance with the thinner thicknesses for both metal and dielectric layers, its lumped circuit parameters are optimized well, and the obtained characteristics are almost comparable with that of the conventional DSB using LTCC. It has approximately -10 dB attenuation of common mode noise at 2.4 GHz with very small size of 120 μm 250 μm and volume size of about 1/6000 compared to the conventional DSB.

DOI： 10.35848/1347-4065/ab6b81

Kyutacar

Scopus

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Differential Signal Balancer Embedded in Metal Wiring Layers of Silicon LSI 査読有り

M. Kameya, C. Yang-Min, <B>K. Nakamura

International Conference on Solid State Devices and Materials(SSDM) M-3-05 2019年09月

Monte Carlo analysis by direct measurement using V<inf>th</inf>-shiftable SRAM cell TEG 査読有り国際誌

Yamaguchi S., Nishikata D., Imi H., Nakamura K.

IEEE International Conference on Microelectronic Test Structures 2018-March 93 - 96 2018年06月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The measurement system in which the Monte Carlo analysis of SRAM operation can be performed in actual measurement using Vth-shiftable SRAM cell TEG (VTST) was developed. The dynamic Vth-shift circuit (DVSC) using electrolytic capacitors and mechanical relays for setting individual Vth-shift voltages for six MOSFETs in a memory cell enables to share a programmable external voltage source. The measured results of the Monte Carlo analysis for SRAM function test and the static noise margin evaluation were agreed well with the simulated results. The proposed method can compactly cope with the recently proposed SRAM with a larger number of transistors.

DOI： 10.1109/ICMTS.2018.8383772

Scopus

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Monte Carlo Analysis by Direct Measurement using Vth-shiftable SRAM Cell TEG 査読有り

S. Yamaguchi, D. Nishikata, H. Imi, K. Nakamura

IEEE International Conference on Microelectronic Test Structures (ICMTS) 2018 M_5_2 2018年03月

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator 査読有り

Daisuke Nishikata, Mohammad Alimudin Bin Mohd Ali, Kento Hosoda, Hiroshi Matsumoto, Kazuyuki Nakamura

Japanese Journal of Applied Physics 57 ( 4S ) 04FF11-1 - 04FF11-5 2018年03月

担当区分：責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18μm CMOS process. The minimum operating voltage of 0.25V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push-pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

DOI： 10.7567/JJAP.57.04FF11

Kyutacar

Scopus

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Fully Digital Ternary Content Addressable Memory using Ratio-less SRAM Cells and Hierarchical-AND Matching Comparator for Ultra-low-voltage Operation 査読有り

D. Nishikata, M. A. Bin Mohd Ali, K. Hosoda, H.Matsumoto, K. Nakamura

International Conference on Solid State Devices and Materials(SSDM) 339 - 340 2017年09月

V<inf>th</inf>-shiftable SRAM cell TEGs for direct measurement for the immunity of the threshold voltage variability 査読有り国際誌

Yamaguchi S., Imi H., Tokumaru S., Kondo T., Yamamoto H., Nakamura K.

IEEE International Conference on Microelectronic Test Structures 2017年06月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We developed VTSTs for 6T-SRAM and RL-SRAM and evaluated them to investigate the influences of SRAM operation by Vth fluctuation using measured FCMs and CΔVths. As a result, we successfully confirmed the superior immunity of Vth fluctuation of the RL-SRAM than the 6T-SRAM.

DOI： 10.1109/ICMTS.2017.7954265

Scopus

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A Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability 査読有り

S. Yamaguchi, H. Imi, S. Tokumaru, T Kondo, H. Yamamoto, K. Nakamura

IEEE International Conference on Microelectronic Test Structures (ICMTS) 2017 59 - 61 2017年03月

A Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability 査読有り

S. Yamaguchi, H. Imi, S. Tokumaru, K. Nakamura

IEEE/ACM Workshop on Variability Modeling and Characterization 2016年09月

Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods 査読有り

Yusuke Kohara, Naoya Kubo, Tomofumi Nishiyama, Taiki Koizuka, Mohammad Alimudin, Amirul Rahmat, Hitoshi Okamura, Tomoyuki Yamanokuchi, Kazuyuki Nakamura

Japanese Journal of Applied Physics 55 ( 4S ) 04EF06-1 - 04EF06-7 2016年04月

A DC-balanced Bus-invert Coding for Stabilizing the Intermediate Power Level in Stacked-Vdd LSIs 査読有り

Y. Kohara, N. Kubo, M. Alimudin, A. Rahmat and K. Nakamura

International Conference on Solid State Devices and Materials(SSDM) 2015年09月

Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation 査読有り

Takahiro Kondo, Hiromasa Yamamoto, Satoko Hoketsu, Hitoshi Imi, Hitoshi Okamura, Kazuyuki Nakamura

Japanese Journal of Applied Physics 54 ( 4S ) 04DD11-1 - 04DD11-6 2015年04月

A Measurement of Ratio-less 12-transistor SRAM cell Operation at Ultra-low Supply-voltage 査読有り

T. Kondo, H. Yamamoto, H. Imi, H. Okamura, K. Nakamura

International Conference on Solid State Devices and Materials(SSDM) 82 - 83 2014年09月

A Stabilization Technique for Intermediate Power Level in Stacked-Vdd ICsusing Parallel I/O Signal Coding 査読有り

T. Nishiyama, T. Koizuka, H. Okamura, T.Yamanokuchi, K. Nakamura

International Conference on Solid State Devices and Materials(SSDM) 120 - 121 2013年09月

Mosaic SRAM Cell TEGs with Intentionally-added Device Variability for Confirming the Ratio-less SRAM Operation 査読有り

H. Okamura, T. Saito, H. Goto, M. Yamamoto, K. Nakamura

IEEE International Conference on Microelectronic Test Structures (ICMTS) 2013 212 - 215 2013年03月

A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM 査読有り

T. Saito, H. Okamura, M. Yamamoto, K. Nakamura

2012 4th IEEE International Memory Workshop (IMW) 2012年05月

A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch 査読有り

Y.Hirakawa, A. Motomura,K. Ota,N. Mimura, K. Nakamura

IEEE International Conference on Microelectronic Test Structures (ICMTS) 2012 2012年03月

Complementary Metal Oxide Semiconductor Operational Amplifier Offset Calibration Technique Using Closed Loop Offset Amplifier and Folded-Alternated Resistor String Digital-to-Analog Converter 査読有り

Hiroyuki Morimoto, Hiroaki Goto, Hajime Fujiwara, Kazuyuki Nakamura

Japanese Journal of Applied Physics 51 ( 2 ) 02BE10 - 02BE10-6 2012年02月

An Experimental Verification of the Design Margin Analysis Method for Even-Stage Ring Oscillators with CMOS Latch 査読有り

Y. Hirakawa, N. Mimura, A. Motomura, K. Nakamura

International Conference on Solid State Devices and Materials(SSDM) 2011年09月

CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC 査読有り

H. Morimoto, H. Goto, H. Fujiwara, K. Nakamura

2011 International Conference on Solid State Devices and Materials(SSDM) 2011年09月

An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-wire Serial I/O 査読有り

H. Morimoto, H. Koike, K. Nakamura

IEICE TRANSACTIONS on Electronics E94-C ( 6 ) 945 - 952 2011年06月

An Optimal Design Method for Complementary Metal Oxide Semiconductor Even-Stage Ring Oscillators Containing Latches 査読有り

Y. Kohara, M. Asano, Y. Kawakami, Y. Uchida, H. Koike, K. Nakamura

Japanese Journal of Applied Physics 49 ( 4 ) 04DE15 - 04DE15-6 2010年04月

An Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function 査読有り

H. Morimoto, H. Koike, K. Nakamura

15th Asia and South Pacific Design Automation Conference (ASP-DAC) 365 - 366 2010年01月

An Optimal Design Method for CMOS Even-Stage Ring Oscillators Containing Plural Latches 査読有り

Y. Kohara, Y. Kawakami, Y. Uchida, H. Koike, K. Nakamura

2009 International Conference on Solid State Devices and Materials(SSDM) 2009年10月

Static Noise Margin Evaluation Method Based on Direct Polynomial-Curve-Fitting with Universal SRAM Cell Inverter TEG Measurement 査読有り

K. Nakamura,K.Noda,H.Koike

IEEE International Conference on Microelectronic Test Structures (ICMTS) 2009年03月

An Optimal Design Method for Even-Stage Ring Oscillators with a CMOS Latch 査読有り

K. Nakamura,M.Asano,Y.Kohara,H.Koike

2008 International Conference on Solid State Devices and Materials (SSDM 2008) 2008年09月

A memory-based programmable logic device using look-up table cascade with synchronous static random access memories 査読有り

K. Nakamura,T. Sasao,M. Matsuura,K. Tanaka,K. Yoshizumi,H. Nakahara,Y. Iguch

Japanese Journal of Applied Physics 45 ( 4B ) 3295 - 3300 2006年04月

A memory-based programmable logic device using a look-up table cascade with synchronous SRAMs 査読有り

K. Nakamura,T. Sasao,M. Matsuura,K. Tanaka,K. Yoshizumi,H. Nakahara,Y. Iguchi

2005 International Conference on Solid State Devices and Materials (SSDM 2005) 2005年09月

Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs 査読有り

K. Nakamura,T. Sasao,M. Matsuura,K. Tanaka,K. Yoshizumi,H. Qin,Y. Iguchi

Cool Chips VIII, IEEE Symposium on Low-Power and High-Speed Chips 2005年04月

A realization of multiple-output functions by a look-up table ring 査読有り

H. Qin,T. Sasao,M. Matsuura,K. Nakamura,S. Nagayama,Y. Iguchi

IEICE Transactions on Fundamentals of Electronics E87-A 3141 - 3150 2004年12月

強誘電体メモリ（FeRAM）の長期データ保持特性テスト法査読有り

小池,田辺,山田,豊島,中村

電子情報通信学会論文誌 J86-C ( 8 ) 902 - 912 2003年08月

An On-Chip 100GHz Sampling 8-channel Sampling-Oscilloscope Macro with Embedded Sampling-Clock Generator 査読有り

M.Takamiya,M.Mizuno,K.Nakamura

2002 International Solid-State Circuits Conference(ISSCC) 182 - 183 2002年02月

A 2.5GHz 4-phase Clock Generator with Scalable No-Feedback-Loop Architecture 査読有り

K.Yamaguchi,M.Fukaishi,T.Sakamoto,A.Akiyama,K.Nakamura

IEEE Journal of Solid-State Circuits 36 ( 11 ) 1666 - 1672 2001年11月

Optimizing Bias Circuit Design of Cascode Operational Amplifiers for Wide Dynamic Range Operations 査読有り

T.Fukumoto,H.Okada,K.Nakamura

2001 International Symposium on Low Power Electronics and Design, 2001年08月

interconnection as an IP macro of a CMOS library 査読有り

T.Yoshikawa,I.Hatakeyama,K.Miyoshi,K.Kurata,J.Sasaki,N.Kami,T.Sugimoto,M.Fukaishi,K.Nakamura,K.Tanaka,H.Nishi,T.Kudoh

Proceedings of the Ninth Symposium on High Performance Interconnects (HOTI '01), 31 - 35 2001年08月

Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro 査読有り

K. Takeda,Y.Aimoto,K.Nakamura,S.Masuoka,K.Ishikawa,K.Noda,T.Takeshima,T.Murotani

2001 IEEE Symposium on VLSI Circuits 229 - 230 2001年06月

A 0.10um CMOS, 1.2V, 2GHz Phase-Locked Loop with Gain Compensation VCO 査読有り

K. Minami,M. Fukaishi,M. Mizuno,H. Onishi,K. Noda,K. Imai,T. Horiuchi,H. Yamaguchi,T. Sato,K. Nakamura,M.Yamashina

IEEE Custom Integrated Circuits Conf. (CICC) 213 - 216 2001年05月

A 2Gb/s 21CH Low Latency Transceiver Circuit for Inter-Processor Communication 査読有り

T.Tanahashi,K.Kurisu,H.Yamaguchi,S.Tomari,T.Matsuzaka,K.Nakamura,M.Fukaishi,S.Naramoto,T.Sato

2001 ISSCC Digest of technical Papers 60 - 61 2001年02月

A 2.5GHz 4-phase Clock Generator with Scalable and No Feedback Loop Architecture 査読有り

K.Yamaguchi,M.Fukaishi,T.Sakamoto,A.Akiyama,K.Nakamura

2001 ISSCC Digest of technical Papers, 398 - 399 2001年02月

A 20-Gb/s CMOS Multichannel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Displays 査読有り

M.Fukaishi,K.Nakamura,H.Heiuchi,Y.Hirota,Y.Nakazawa,H.Ikeno,H.Hayama,M.Yotsuyanagi

IEEE Journal of Solid-State Circuits 35 1611 - 1618 2000年11月

A CMOS 50% duty cycle repeater using complementary phase blending 査読有り

K.Nakamura,M.Fukaishi,M.Yotsuyanagi et al

2000 Symposium on VLSI Cricuits 48 - 49 2000年06月

A 20-Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Display 査読有り

M.Fukaishi,K.Nakamura,M.Yotsuyanagi,et.al.

2000 ISSCC Digest of technical Papers 260 - 261 2000年02月

Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology 査読有り

M,Kurisu,M.Fukaishi,H.Asazawa,M.Nishikawa,K.Nakamura,M.Yotsuyanagi

IEICE Transactions on Electronics E82-C ( 3 ) 428 - 437 1999年03月

A 4.25-Gb/s CMOS fiber channel transceiver with asynchronoustree-type demultiplexer and frequency conversion architecture 査読有り

M.Fukaishi,K.Nakamura,M.Sato,Y.Tsutsui,S.Kishi,M.Yotsuyanagi

IEEE Journal of Solid-State Circuits 33 2139 - 2147 1998年12月

A 6Gbps 0.18um CMOS Phase Detecting DEMUX Module Using Half-Frequency Clock 査読有り

K.Nakamura,M.Fukaishi,M.Yotsuyanagi et. al.

1998 Symposium on VLSI Cricuits 196 - 197 1998年06月

A 4.25Gbps CMOS Fiber Channel Transceiver with Asynchronous Binary Tree-type Demultiplexer and Frequency Conversion Architecture 査読有り

M.Fukaishi,K.Nakamura,M.Yotsuyanagi et.,al.

1998 ISSCC Digest of technical Papers 306 - 307 1998年02月

A 500MHz 4Mb CMOS Pipe-line Burst Cache SRAM with Point-to-Point Noise Reduction Coding I/O 査読有り

K.Nakamura,K.Takeda,H.Toyoshima,K.node,H.Ohkubo,T.Uchida,T.Shimizu,T.Itani,K.Tokashiki,K.Kishimoto

IEEE Journal of Solid-State Circuits 32 1758 - 1765 1997年11月

A 500MHz 4Mb CMOS Pipe-line Burst Cache SRAM with Point-to-Point Noise Reduction Coding I/O 査読有り

K.Nakamura,K.Takeda,H.Toyoshima,K.node,H.Ohkubo,T.Uchida,T.Shimizu,T.Itani,K.Tokashiki ,K.Kishimoto

1997 ISSCC Digest of Technical Papers 406 - 407 1997年02月

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM 査読有り

H.Toyoshima,S.Kuhara,K.Takeda,K.Nakamura,H.Okamura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki

IEEE Journal of Solid-State Circuits 31 1610 - 1617 1996年11月

A 50% Noise Reduction Interface Using Low-weight Coding 査読有り

K.Nakamura,Mark. A. Horowitz

1996 Symposium on VLSI Cricuits 144 - 145 1996年06月

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM 査読有り

S.Kuhara,H.Toyoshima,K.Takeda,K.Nakamura,H.Okamura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki

1996 ISSCC Digest of technical Papers 1996年02月

PLL Timing Design Techniques for Large-scale, High-speed, Low-cost SRAMs 査読有り

K.Nakamura,S.Kuhara,T.Kimura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki

Transactions on Electronics E78-C ( 7 ) 805 - 811 1995年07月

Design of 1.28-GB/s Bandwidth 2-Mb SRAM for Integrated Memory Array Processor Application 査読有り

T.Kimura,K.Nakamura,Y.Aimoto,T.Manabe,N.Yamashita,Y.Fujita,S.Okazaki,M.Yamashina

IEEE Journal of Solid-State Circuits 30 637 - 643 1995年06月

High Speed Sub-micron Bi-CMOS Memory 査読有り

M.Takada,K.Nakamura,T.Yamazaki

IEEE Transactions on Electron Devices 42 ( 3 ) 497 - 505 1995年03月

A 3.84GIPS Integrated Memory Array Processor 査読有り

Y.Fujita,N.Yamashita,T.Kimura,K.Nakamura,S.Okazaki

IEICE transactions on Systems and Computers J78-D-I ( 2 ) 82 - 90 1995年02月

An SIMD Type Integrated Memory Array Processor (IMAP) 査読有り

Y.Fujita,N.Yamashita,T.Kimura,K.Nakamura,S.Okazaki

International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) 1994年12月

220MHz Pipelined 16Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator 査読有り

K.Nakamura,T.Oguri,T.Atsumo,M.Takada,A.Ikemoto,H.Suzuki,T.Nishigori,T.Yamazaki

IEEE Journal of Solid-State Circuits 29 1317 - 1322 1994年11月

A 3.84GIPS Integrated Memory Array Processor LSI with 64 Processing Elements and a 2Mb SRAM 査読有り

N.Yamashita,T.Kimura,Y.Fujita,Y.Aimoto,T.Manabe,S.Okazaki,K.Nakamura,M.Yamashina

IEEE Journal of Solid-State Circuits 29 1366 - 1343 1994年11月

A High Performance 0.4um BiCMOS Technology for 16Mb BiCMOS SRAM's 査読有り

T.Yamazaki,H.Suzuki,T.Nishigori,K.Nakamura,T.Oguri,T.Atsumo,M.Takada,A.Ikemoto

European Solid-State Device Research Conference (ESSDERC) 1994年09月

PLL Timing Design Techniques for Large-scale, High-speed, Low-power and Low-cost SRAMs 査読有り

K.Nakamura,S.Kuhara,T.Kimura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki

Proceeding of 1994 Custom Integrated Circuit Conference 1994年05月

A 220MHz Pipelined 16Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator 査読有り

K.Nakamura,S.Kuhara,T.Kimura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki

1994 ISSCC Digest of Technical Papers 1994年02月

A 3.84GIPS Integrated Memory Array Processor LSI with 64 Processing Elements and 2Mb SRAM 査読有り

N.Yamashita,T.Kimura,Y.Fujita,Y.Aimoto,T.Manabe,S.Okazaki,K.Nakamura,M.Yamashina

1994 ISSCC Digest of Technical Papers 1994年02月

A 6ns ECL 100K I/O and 8ns 3.3V TTL I/O 4Mb BiCMOS SRAM 査読有り

K.Nakamura,T.Oguri,T.Atsumo,M.Takada,A.Ikemoto,H.Suzuki,T.Nishigori and T.Yamazaki

IEEE Journal of Solid-State Circuits 29 1504 - 1510 1992年11月

A Stacked Emitter Polysilicon (STEP) Bipolar Technology for 16Mb BiCMOS SRAMs 査読有り

H.Suzuki,T.Nishigori,T.Yamazaki,K.Nakamura,T.Oguri,T.Atsumo,M.Takada,A.Ikemoto

IEEE 1992 Bipolar Circuits and Technology Meeting Proceedings 100 - 103 1992年10月

A 6ns 4Mb ECL I/O BiCMOS SRAM with LV-TTL Mask Option 査読有り

K.Nakamura,T.Oguri,T.Atsumo,M.Takada,A.Ikemoto,H.Suzuki,T.Nishigori,T.Yamazaki

1992 ISSCC Digest of Technical Papers 212 - 213 1992年02月

Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs 査読有り

K.Nakamura,M.Takada,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Sekine,Y.Minato and H.Kimoto

IEICE Transactions on Electronics E74 ( 4 ) 1991年04月

A 5ns 1Mb ECL BiCMOS SRAM 査読有り

M.Takada,K.Nakamura,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Sekine,Y.Minato and H.Kimoto

IEEE Journal of Solid-State Circuits 25 1057 - 1062 1990年10月

A 5ns 1Mb BiCMOS SRAM with ECL Interface 査読有り

M.Takada,K.Nakamura,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Fukuda,Y.Minato and H.Kimoto

1990 ISCAS 1990年04月

A 5ns 1Mb ECL BiCMOS SRAM 査読有り

M.Takada,K.Nakamura,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Fukuda,Y.Minato and H.Kimoto

1990 ISSCC Digest of Technical Papers 138 - 139 1990年02月

Controlling Bloch lines and domain chopping for multiple stripes aligned in parallel 査読有り

K. Matsuyama,K. Nakamura,H. Asada,T. Suzuki,K. Fujimoto,and S. Konishi

Journal of Applied Physics 63 ( 8 ) 3171 - 3173 1988年04月

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