Updated on 2023/06/01

 
MATSUMOTO Satoshi
 
Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 7

Citation count denotes the number of citations in papers published for a particular year.

Affiliation
Faculty of Engineering Department of Electrical and Electronic Engineering
Job
Professor
External link

Degree

  • Waseda University  -  Doctor of Engineering   1996.12

Biography in Kyutech

  • 2016.04
    -
    2017.03
     

    Kyushu Institute of Technology   School of Engineering  

  • 2016.04
    -
    2017.03
     

    Kyushu Institute of Technology   Faculty of Engineering  

  • 2010.04
     

    Kyushu Institute of Technology   Faculty of Engineering   Department of Electrical and Electronic Engineering   Professor  

Papers

  • Impact of the multi-layer graphene for 3D power supply on chip Reviewed

    A.Furue, S. Matsumoto, and M. Hasegawa

    New Diamond and Nano Carbons 2022 ( Japan New Diamond Forum )   8P-28   2022.06

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Kanazawa   2022.06.06  -  2022.06.09

  • Voltage compensation performance of the voltage unbalance compensator using the method of symmetrical components Reviewed

    T. Katsuki, I. Yamakawa, A. Imakiire, and S. Matsumoto

    The 2022 International Power Electronics Conference(IPEC 2022) ( The Institute of Electrical Engineers of Japan )   2484 - 2490   2022.05

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Himeji   2022.05.15  -  2022.05.19

  • Design Consideration of 3D Power SoC Using Virtual Prototyping Reviewed

    A. Furue, S. Miyasaka, Y. Ohgushi, R. Yamanishi, and S. Matsumoto

    International Conference on Electronics Packaging 2022 ( The Japan Institute of Electronics Packaging )   FC2-2   2022.05

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Sapporo   2022.05.11  -  2022.05.14

    DOI: 10.23919/ICEP55381.2022.9795434

    DOI: 10.23919/ICEP55381.2022.9795434

  • Experimental Evaluation of Parasitic Bipolar Effects and Mechanical Stress Effects in SOI-Power-MOSFETs Reviewed

    Koki SHIOTSUKA, Masaaki KOGANEMARU, Satoshi MATSUMOTO, and Toru IKEDA

    Journal of The Japan Institute of Electronics Packing ( JIEP )   25 ( 1 )   103 - 110   2022.01

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    Language:Japanese   Publishing type:Research paper (scientific journal)

    DOI: doi.org/10.5104/jiep.JIEP-D-21-00007

  • Fully integrated transformer less floating gate driver for 3D power supply on chip Reviewed

    Y. Ogushi and S.Matsumoto

    IEEE 3D system integration conference 2021(3DIC2021) ( IEEE )   Session 8a   2021.11

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Raleigh   2021.11.15  -  2021.11.18

    DOI: 10.1109/3DIC52383.2021.9687603

  • Numerical investigations for 3D power supply on chip by coupling of thermal-fluid, circuit, and electromagnetic field simulations Reviewed

    A.Furue and S.Matsumoto

    IEEE 3D system integration conference 2021(3DIC2021) ( IEEE )   Session 8c   2021.11

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Raleigh   2021.11.15  -  2021.11.18

    DOI: 10.1109/3DIC52383.2021.9687610

  • Numerical predictions of 3D power-supply on chip taking into considerations of proximity effect Reviewed

    S. Miyasaka and S. Matsumoto

    IEEE 3D system integration conference 2021(3DIC2021) ( IEEE )   Session 8b   2021.11

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    USA   Raleigh   2021.11.15  -  2021.11.18

  • Development of the h-BN manufacturing process for 3D IC Reviewed

    M. Yokoi, S. Shinkai, and S. Matsumoto

    IEEE CPMT Symposium Japan 2021(ICSJ2021) ( IEEE )   120 - 121   ECR Session09   2021.11

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    Authorship:Last author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Kyoto   2021.11.10  -  2021.11.12

    DOI: 10.1109/ICSJ52620.2021.9648854

  • Comparison of the instability in device characteristics for thin-film SOI power n- and p- MOSFETs at high temperature under AC stress Reviewed International journal

    Riki Yamanishi, Satoshi Matsumoto

    Microelectronics reliability ( Elsevier )   126   114301   2021.11

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    DOI: doi.org/10.1016/i.microrel.2021.114301, 2021

  • Numerical investigations of the multi-layer graphene as a thermal interface material and an elector-magnetic field shield layer for 3D power supply on chip applications Reviewed

    A. Furue and S. Matsumoto

    International Power Supply on Chip Workshop 2021 ( IEEE )   Poster session 12   2021.10

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Philadelphia   2021.10.24  -  2021.10.27

  • Comparisons of instability in device characteristics at high temperature for thin-film SOI power n- and p-channel MOSFETs Reviewed

    M. Kaneda, K. Ariyoshi, and S. Matsumoto

    TENCON2020 ( IEEE )   TuA. 26.3   2020.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   On-line   2020.11.16  -  2020.11.19

  • Torque Performance of the 750 W Induction Motor with a Voltage Unbalance Compensator Utilized Independent DC Voltage Source Reviewed

    T. Katsuki, A. Imakiire, and S. Matsumoto

    ICEMS2020 ( IEEE )   LS6C-2   2020.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   On-line   2020.11.24  -  2020.11.27

  • Impact of the passive component structure for high efficiency and fast response POL using Power Supply on Chip Reviewed

    K. Kajihara, S. Abe, S. Matsumoto

    Journal of the Institute of Industrial Applications Engineers ( Institute of Industrial Applications Engineers )   8 ( 1 )   1 - 7   2020.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.12792/JIIAE.8.1

  • Si (100)-GaN/Si (111) low temperature wafer bonding process for 3D power supply on chip Reviewed

    R. Ishito, K. Ono, S. Matsumoto

    IEEE CPMT Symposium Japan 2019 (ICSJ2019) ( IEEE )   ECR Session12   2019.11

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    Japan   Kyoto   2019.11.18  -  2019.11.20

  • Transformer-less floating gate driver for 3D power SoC Reviewed

    M. Nakayama, S. Abe, S.Matsumoto

    2019 International 3D Systems Integration Conference (3DIC) ( IEEE )   B4P-C 4055   2019.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Sendai   2019.10.08  -  2019.10.10

  • Novel Software Defined Power Supply Utilizing Power Supply on Chip -Power supply which outputs the regulated output voltage by only connecting the load- Reviewed International journal

    T. Oka, S. Abe, S. Matsumoto

    21th European Conference on Power Electronics and Applications (EPE 2019, ECCE Europe)   DS2f 112   2019.09

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    Italy   Gen0va   2019.09.02  -  2019.09.06

  • Novel Fully Digital-controlled point of load converter based on H-bride DC-DC converter Reviewed

    T. Oka, S. Nakano, S. Abe, S. Matsumoto

    IEEJ Journal of Industry Application ( IEEJ )   8 ( 5 )   813 - 819   2019.09

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1541/ieejjia.8.813

  • Transient response of a digitally controlled power supply based on power-SoC Reviewed

    T. Oka, S. Abe, S. Matsumoto

    International Power Supply on Chip Workshop 2018   P7.8   2018.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Hsinchu   2018.10.17  -  2018.10.23

  • Design consideration of air core on-chip spiral coil for power supply on chip Reviewed

    S. Abe, H. Kaishakuji, S. Matsumoto

    International Power Supply on Chip Workshop 2018   P4.6   2018.10

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    Taiwan   Hsinchu   2018.10.17  -  2018.10.19

  • Numerical predictions of a novel 3D stacked power SoC structure based on hexagonal-BN Reviewed

    Y. Sato, K. Ono, S. Matsumoto, M. Hasegawa

    International Power Supply on Chip Workshop 2018   P5.3   2018.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Hsinchu   2018.10.17  -  2018.10.19

  • Impact of the semiconductor on hexagonal-BN structure for power supply on chip Reviewed

    Y. Sato, K. Ono, M. Nomura, S. Matsumoto, M. Hasegawa

    Extended Abstract of the 2018 International Conference on Solid State Devices and Materials   PS-4-08   2018.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    日本   東京   2018.09.10  -  2018.09.13

  • Design consideration of a 3D stacked power supply on chip Reviewed

    K. Ono, K. Hiura, S. Matsumoto,

    2018 IEEE the 68th Electronic Components and Technology Conference   Session 27.7   2018.05

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    アメリカ   San Diego   2018.05.29  -  2018.06.01

  • Operating Principle of Current Resonant Converter Using Air Core Transformer for Isolated Power Supply on Chip Reviewed

    S. Abe, H. Kaishakuji, S.Matsumoto,

    International Power Electronics Conference 2018   23A2-3, 2-18   2018.05

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    日本   新潟   2018.05.20  -  2018.05.24

  • A Novel Full Digital control H-bridge DC-DC converter for power Supply on Chip application Reviewed

    S. Nakano, T. Oka, S. Abe, S. Matsumoto

    International Power Electronics Conference 2018   23A2-3, 2-19   2018.05

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    日本   新潟   2018.05.20  -  2018.05.24

  • Potential of a power supply on chip for solar cell based energy harvesting systems Reviewed

    S28-2   2017.12

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    アメリカ   Honolulu   2017.12.12  -  2017.12.15

  • AC Hot carrier effect and PBTI of a thin film SOI Power n-MOSFET at high temperature Reviewed

    PS-14-06   2017.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    日本   仙台   2017.09.19  -  2017.09.22

  • Potential of the 0.35 µm CMOS gate driver technology for the GaN power devices Reviewed

    - N-6-03   2017.09

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    日本   仙台   2017.09.19

  • Impact of the 3D Stacking Power Supply on Chip for High Frequency DC-DC Converter Reviewed

    56 ( 4 )   04CR13   2017.04

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  • AC Hot Carrier Effect of the Thin-film SOI Power nMOSFET Reviewed

    56 ( 4 )   04CR17   2017.04

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  • A Silicon Based Multi-Tens MHz Gate Driver IC for GaN Power Devices Reviewed

    T. Akagi, S.Miyano, S. Abe, and S.Matsumoto,"

    2017 IEEE Applied Power Electronics Conference and Exposition(APEC)   1978 - 1982   2017.03

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Tampa   2017.03.26  -  2017.03.30

  • Reduced operating temperature of active layer Si covered by nanocrystalline diamond film Reviewed

    S.Duangchan, Y.Koishikawa, R. Shirahama, K. Oishi, A. Baba, S. Matsumoto and M.Hasegawa

    Journal of Material Science ; Materials in Electronics   28   617 - 624   2017.01

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  • Evaluation of ON-Chip Inductor and Transformer for Isolated Power-SoC Reviewed

    S. Abe, T. Akagi, and S. Matsumoto

    International Power Supply on Chip Workshop 2016   e-poster 05   2016.10

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    Spain   Madrid   2016.10.03  -  2016.10.05

  • Potential of the 3D stacking power SoC for high frequency switching applications Reviewed

    Y. Ikeda, K. Hiura, Y. Hino, and S. Matsumoto

    International Power Supply on Chip Workshop 2016   e-poster 09   2016.10

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    Spain   Madrid   2016.10.03  -  2016.10.05

  • Transient response of Field Programmable Power Supply Array based on power SoC Reviewed

    M. Higashida, S.Abe, and S. Matsumoto

    International Power Supply on Chip Workshop 2016   e-poster 08   2016.10

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    Spain   Madrid   2016.10.03  -  2016.10.05

  • Impact of the 3D Stacking Power Supply on Chip for High Frequency DC-DC Converter Reviewed

    K. Hiura, Y. Ikeda, Y. Hino, and S.Matsumoto

    Extended Abstract of the 2016 International Conference on Solid State Devices and Materials   PS-14-03,   2016.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Tsukuba   2016.09.26  -  2016.09.29

  • Comparisons of Hot-carrier Effects of Scaled N-Channel and p-Channel Thin-film SOI Power MOSFETs under Constant Drain Electric Field Reviewed

    K. Ikeno and S.Matsumoto

    Extended Abstract of the 2016 International Conference on Solid State Devices and Materials   PS-14-04   2016.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Tsukuba   2016.09.26  -  2016.09.29

  • Impact of three-dimensional stacking silicon on diamond substrate for the electrostatic discharge protection device Reviewed

    Y. Ikeda, K. Nakagawa, W. Yoshida, and S. Matsumoto

    Japanese Journal of Applied Physics   55 ( 04S )   04ER20   2016.04

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.7567/JJAP.55.04ER20

  • An isolated DC-DC converter using air-core inductor for power supply on chip applications Reviewed

    T. Akagi, M. Hatanaka, S. Matsumoto, and S. Abe

    IEEE INTELEC 2015   408   2015.10

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    Japan   Osaka   2015.10.18  -  2018.10.22

    DOI: 10.1109/INTLEC.2015.7572431

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  • A fully digitally controlled multiple input and output voltage buck-boost POL for power supply on chip Reviewed

    T. Hashiguchi, S. Abe, and S. Matsumoto

    IEEE INTELEC 2015   1086 - 1091   2015.10

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    Japan   Osaka   2015.10.18  -  2015.10.22

    DOI: 10.1109/INTLEC.2015.7572318

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  • The Heat Performance Study of Nanocrystal Diamond Film Used in a Thin Film Device Reviewed

    S. Duangchan, U. Koshikawa, R. Shirahama, K.Oishi, A. Baba, S. Matsumoto, and M.Hasagawa

    International Conference on Solid State Devices and Materials 2015   - PS14-4   2015.09

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    Japan   Sapporo   2015.09.27  -  2018.09.30

  • Impact of 3D Stacking Silicon on Diamond Substrate for the ESD Protection Device Reviewed

    Y. Ikeda, K.Nakagawa, and S.Matsumoto

    International Conference on Solid State Devices and Materials   PS-14-3   2015.09

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    Japan   Sapporo   2015.09.27  -  2015.09.30

  • A concept of field programmable power supply array utilizing power supply on chip -- Fully digital controlled multiple input and output voltages POL-- Reviewed

    M. Higashida, S. Abe, and S.Matsumoto

    17th European Conference on Power Electronics and Applications (EPE 2015, ECCE Europe)   LS1e.4   2015.09

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    Switaerland   Geneva   2015.09.08  -  2015.09.10

    DOI: 10.1109/EPE.2015.7309289

    Scopus

  • The Silicon on Diamond Structure by low temperature bonding technique Reviewed

    S. Duangchan, U. Uchikawa, U. Koshikawa, A. baba, K. Nakagawa, S.Matsumoto, M.Hasagawa, and S.Nishizawa,

    Proceedings of IEEE Electric Components and Technology Conference 2015   187 - 192   2015.05

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    USA   San Diego   2015.05.25  -  2015.05.29

    DOI: 10.1109/ECTC.2015.7159590

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  • Hot carrier effect and PBTI of a thin-film SOI power MOSFET at high temperature Reviewed

    W. Yoshida, T. Takasugi, and S. Matsumoto

    Japanese Journal of Applied Physics   54 ( 4 )   04DP17   2015.04

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    DOI: 10.7567/JJAP.54.04DP17

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    CiNii Article

  • Impact of the silicon on diamond structure for high temperature switching applications Reviewed

    H. Kanoya K. Nakagawa and S. Matsumoto

    Japanese Journal of Applied Physics   54 ( 4 )   04DP09   2015.04

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    DOI: 10.7567/JJAP.54.04DP09

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    CiNii Article

  • A novel multi-output back-boost POL architecture for power supply on chip Reviewed

    Takuto Hashiguchi, Satoshi Matsumoto, Seiya Abe

    International Power Supply on Chip Workshop 2014   67 - 67   2014.10

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    USA   Boston   2014.10.06  -  2014.10.08

  • Numerical evaluations of a new 3D stacking structure for power supply on chip Reviewed

    Wataru Yoshida, Kentaro Nakagawa, Satoshi Matsumoto, Takatoshi Yamada, Masataka Hasegawa

    International Power Supply on Chip Workshop 2014   73 - 73   2014.10

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    USA   Boston   2014.10.06  -  2014.10.08

  • Isolated power transfer system for power supply on chip Reviewed

    Seiya Abe, satoshi Matsumoto

    International Power Supply on Chip Workshop 2014   80 - 80   2014.10

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    USA   Boston   2014.10.06  -  2014.10.08

  • A novel concept of digitally controlled multiple output POL for power supply on chip Reviewed

    Takayuki Yamamoto, Satoshi Matsumoto, Seya Abe

    International communication Energy Conference   PO-33   2014.09

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    Canada   Vancouver   2014.09.28  -  2014.10.02

  • Impact of the silicon on diamond structure for high temperature switching applications Reviewed

    Hiroki Kanoya, Kentaro Nakagawa, Satoshi Matsumoto

    Exttended Abstract of 2014 Solid State Devices & Materials(SSDM2014   366 - 367   2014.09

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    Japan   Tsukuba   2014.09.08  -  2014.09.11

  • Hot carrier effect and PBTI of a thin-film SOI power MOSFET at high temperature Reviewed

    Wataru Yoshida, Tomoya Takasugu, Satoshi Matsumoto

    Extended Abstract of 2014 Solid State Devices & Materials(SSDM2014   362 - 363   2014.09

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    Japan   Tsukuba   2014.09.08  -  2014.09.11

  • Device characteristics of the thin-film SOI power MOSFETs in high temperature Reviewed

    Tsubasa Ishibashi, Yuka Morisawa, Satoshi Matsumoto

    Japanese Journal of Applied Physics   53 ( 6 )   064102   2014.06

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    DOI: 10.7567/JJAP.53.064102

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    CiNii Article

  • A novel load regulation technique for power-SoC with parallel connected POLs Invited Reviewed

    Seiya Abe, Akira Hidaka, Jungo Rikitake, Satoshi Matsumoto, Tamotsu Ninomiya

    2014 International Power Electronics Conference (IPEC2014)   2216 - 2221   2014.05

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    Japan   Hiroshima   2014.05.18  -  2014.05.21

    DOI: 10.1109/IPEC.2014.6869897

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  • Hot carrier effect of a scaled thin-film SOI power MOSFET under constant drain electric field Reviewed

    Tomoya Takasugi, Satoshi Matsumoto

    Japanese Journal of Applied Physics   53 ( 4 )   04EP17   2014.04

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  • Impact of silicon on diamond structure for power-supply on chip applications Reviewed

    Kentaro Nakagawa, Takuya Kodama, Satoshi Matsumoto, Takatoshi Yamada, Masakazu Hasegawa, SinichiNishizawa

    Japanese Journal of Applied Physics   53 ( 4 )   04EP16   2014.04

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  • Impact of Silicon on Diamond Structure for Power-Supply on Chip Applications Reviewed

    Kentaro Nakagawa, Takuya Kodama, Satoshi Matsumoto, Takatoshi Yamada, Masakazu Hasegawa, Sinichi. Nishizawa

    Extended Abstract of 2013 Solid State Devices & Materials (SSDM2013   1044 - 1045   2013.09

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    Japan   Fukuoka   2013.09.24  -  2013.09.27

  • Hot carrier effect of a scaled thin-film SOI power MOSFET under constant drain electric field Reviewed

    Tomoya Takasugi, Satoshi Matsumoto

    Extended Abstract of 2013 Solid State Devices & Materials(SSDM2013)   454 - 455   2013.09

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    Japan   Fukuoka   2013.09.24  -  2013.09.27

  • Design issues of a thin-film p-channel SOI power MOSFET for high temperature applications Reviewed

    53 ( 11-13 )   1778 - 1782   2013.09

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    DOI: 10.1016/j.microrel.2013.07.078

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  • A New Control Strategy for Power Supply on Chip Using Parallel Connected DC-DC Converters Reviewed

    Takayuki Yamamoto, Jungo Rikitake, Satoshi. Matsumoto, Seya. Abe, Tamotsu Ninomiya

    Proceedings ofThe 10th IEEE International Conference on Power Electronics and Drive systems   109 - 112   2013.04

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    Japan   Kitakyushu   2013.04.22  -  2013.04.25

    DOI: 10.1109/PEDS.2013.6526998

    Scopus

  • Parasitic bipolar effect of a thin-film silicon on insulator power Metal-Oide-Semiconductor Field-Effect Transistor in high temperature Reviewed

    Atsushi Uchida, Yuka Morisawa, Saoshi Matsumoto

    Jpn. J. Applied Physics   52 ( 04 )   04CP08   2013.04

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    DOI: 10.7567/JJAP.52.04CP08

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    CiNii Article

  • A thermoelectric power generation system with ultra low input voltage boost converter with maximum power point tracking Reviewed

    Akira Hidaka, Takuro Tsuji, Satoshi Matsumoto

    Proceedings of International Conference on Renewable Energy and Research Applications (ICRERA2012)   Green energy systems (II)_3   2012.11

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    Japan   Nagasaki   2012.11.12  -  2012.11.14

    DOI: 10.1109/ICRERA.2012.6477474

    Scopus

  • A stand-alone power supply system using single photovoltaic cell with maximum power point tracking Reviewed

    Takuro Tuji, Akira Hidaka, Satoshi Matsumoto

    Proceedings of International Conference on Renewable Energy and Research Applications (ICRERA2012)   Poster session IV_1   2012.11

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    Japan   Nagasaki   2012.11.11  -  2012.11.14

    DOI: 10.1109/ICRERA.2012.6477292

    Scopus

  • Design guideline of a thin film SOI power MOSFET for high thermal stability Reviewed

    Yuka Morisawa, Takuya Kodama, and Satoshi Matsumoto

    J. Microelectronics Reliability   52   2380 - 2384   2012.10

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    DOI: 10.1016/j.microrel.2012.06.101

    Scopus

  • Parasitic bipolar effect of a thin-film SOI power MOSFET in high temperature Reviewed

    Atsushi Uchida, Yuka. Morisawa, S.Matsumoto

    Extended Abstrac of 2012 Solid State Devices & Materials   452 - 453   2012.09

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    Japan   Kyoto   2012.09.25  -  2012.09.27

  • A novel small capacity photovoltaic module for mobile applications Reviewed

    Kita Takahashi, Satoshi Matsumoto

    Proc. 37th Photovoltaic Specialist Conference   Q36   2011.06

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    USA   Seattle   2011.06.19  -  2011.06.24

  • Future Power Electronics for Realizing Sustaining Society Invited Reviewed

    Satoshi Matsumoto

    International Workshop on Power Supply On Chip 2010(PwrSoc 10)   Session 6.6   2010.10

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    Ireland   Cork   2010.10.13  -  2010.10.15

  • Next generation energy electronics for realizing sustainable world Invited Reviewed

    Satoshi Matsumoto

    Workshop Proceedings of Analog VLSI Workshop 2010   13 - 17   2010.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Italy   Pavia   2010.09.08  -  2010.09.10

  • An air-breathing single cell small PEMFC system with AB5-type metal hydrideand an ultra-low voltage input boost converter Reviewed

    K. Akiyama,S. Matsumoto,A.Miyasaka,T.Shodai

    Journal of Power Sources   178 ( 1 )   37 - 44   2009.04

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  • A Novel Strategy of a Control IC for Boost Converter with Ultra Low Voltage Input and Maximum Power Point Tracking for Single Solar Cell Application Reviewed

    S. Matsumoto,Takahisa Shodai,Yasuyuki Kanai

    Proceedings of 21th International Symposium on Power Semiconductor Devices & ICs (ISPSD'09)   180 - 183   2009.04

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    2009.04  -  2009.04

  • Comparisons of the Hot Carrier Effect of Quasi-Silicon-on Insulator and Conventional Silicon-on-Insulator Power Metal-Oxide-Semiconductor Field-Effect-Transistors Formed by Reversed Silicon Wafer Direct Bonding Reviewed

    Jpn. J. Appl. Phy   47 ( 12 )   8739 - 8742   2008.04

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  • A quasi-SOI power MOSFET for radio frequency applications formed by reversed silicon wafer direct bonding Reviewed

    S. Matsumoto,Y. Hiraoka,T. Sakai,T. Yachi,T. Ishiyama,T. Kosugi,H. Kamitsuna,M. Muraguchi

    2008.04

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  • Comparisons of Radio-frequency performance of Quasi- Silicon-on-Insulator and Conventional SOI Power Metal-Oxide-Semiconductor Field-Effect-Transistors Reviewed

    Y.Hiraoka and S.Matsumoto

    Jpn. J. Appl. Phy   46 ( 12 )   7635 - 7638   2007.04

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  • Experimental Investigation of Pattern Layout Effect on Radio-Frequency Performance of Thin Film Silicon-on- Insulator Power Metal- OxideSemiconductor Field-Effect Transistors Reviewed

    S. Matsumoto and M.Mino

    Jpn. J. Appl. Phy   46 ( 9A )   5691 - 5694   2007.04

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  • Design Considerations for Linear Amplification and Low-Insertion Loss Thin Film Silicon-on- Insulator Power Metal Oxide Semiconductor Field-Effect Transistors Reviewed

    S. Matsumoto and Y.Hiraoka

    Jpn. J. Appl. Phy   46 ( 5A )   2873 - 2877   2007.04

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  • A novel photovoltaic module for severe shade conditions Reviewed

    Yasuyuki Kanai,S. Matsumoto

    Record of 2006 IEEE4th World Conference on Photovoltaic Energy Conversion Conference (WCPEC'06)   2   2174 - 2176   2006.04

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    2006.04  -  2006.04

  • Power electronics innovation with next generation advanced power devices Reviewed

    H. Ohashi,I. Omura,S. Matsumoto,Y.Sato,H,Tadano,I. Ishii

    IEICE. Trans. Commun   E87-B ( 12 )   3422 - 3429   2004.04

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  • Impact of the pattern layout on radio-frequency performance of thin-film SOI power MOSFETs Reviewed

    S.Matsumoto and M. Mino

    Proceedings of 16th International Symposium on Power Semiconductor Devices & ICs (ISPSD'04)   245 - 248   2004.04

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    2004.04  -  2004.04

  • Impact of silicon-on-insulator substrate parameters on the radio frequency performance of quasi-silicon-on-insulator power metal-oxide-semiconductor field effect transistors Reviewed

    S. Matsumoto,Yasushi Hiraoka ,Toshiaki Yachi

    Jpn.J.Appl.Phys.   42 ( 5A )   2560 - 2563   2003.04

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  • Design guidelines for linear amplification and low-insertion loss in 5-GHz-band SOI power MOSFETs Reviewed

    S.Matsumoto,Y.Hiraoka,M.Mino

    Proceedings of the European Solid-State Device Research Conference2002 (ESSDERC'02)   371 - 374   2002.04

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    2002.04  -  2002.04

  • Experimental Investigation of linear amplification characteristics of radio-frequency thin-film SOI power MOSFETs Reviewed

    S.Matsumoto,T.Sakai

    IEEE Trans. Electron Devices   ED-48 ( 12 )   2911 - 2916   2001.04

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  • マイクロ波シリコンパワーMOSFET Reviewed

    松本 聡

    電子情報通信学会論文誌C   J84-C ( 7 )   552 - 562   2001.04

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    Language:Japanese   Publishing type:Research paper (scientific journal)

  • A high-efficiency thin-film SOI power MOSFET having self-aligned offset gate structure for multi-gigahertz applications Reviewed

    S. Matsumoto,Y. Hiraoka,T. Sakai

    IEEE Trans. Electron Devices   ED-48 ( 6 )   1270 - 1274   2001.04

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  • Radio-frequency performance of a state-of-the art 0.5-m-rule thin-film SOI power MOSFET Reviewed

    S. Matsumoto,Y. Hiraoka,T. Sakai

    IEEE Trans. Electron Devices   ED-48 ( 6 )   1251 - 1255   2001.04

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  • A highly-efficient tungsten-polycide gate radio-frequency power metal-oxide-semiconductor field-effect-transistor using bonded silicon-on-insulator technology Reviewed

    S. Matsumoto,Y. Hiraoka,T. Sakai

    Jpn. J. Applied Physics   40 ( 3A )   1162 - 1166   2001.04

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  • Low on-resistance SOI power MOSFET using dynamic threshold (DT) concept for high efficient DC-DC converter Reviewed

    Y. Hiraoka,S. Matsumoto,T. Sakai

    Proceedings of 13th International Symposium on Power Semiconductor Devices & ICs (ISPSD'01)   267 - 270   2001.04

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    2001.04  -  2001.04

  • A high-efficiency 5-GHz-band SOI power MOSFET having a self-aligned drain offset structure Reviewed

    S. Matsumoto,Y. Hiraoka,and T. Sakai

    Proceedings of 13th International Symposium on Power Semiconductor Devices & ICs (ISPSD'01)   99 - 102   2001.04

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    2001.04  -  2001.04

  • Investigation on the fully- and partially-depleted thin-film Silicon-on-insulator power metal-oxide-Semiconductor Field-Effect-Transistors for high-frequency applications Reviewed

    S. Matsumoto,T. Sakai,T. Yachi

    Jpn. J. Applied Physics   39 ( 11A )   6155 - 6118   2000.04

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  • Comparison of high-frequency performance of quasi-SOI and conventional SOI power MOSFETs, Reviewed

    Y. Hiraoka,S. Matsumoto,and T. Sakai

    Proceedings of 12th International Symposium on Power Semiconductor Devices & ICs (ISPSD'00)   161 - 164   2000.04

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    2000.04  -  2000.04

  • Application of reversed siloicon wafer direct bonding to thin-film SOI power ICs Reviewed

    T. Ishiyama,S. Matsumoto,Y. Hiraoka,T. Sakai,T. Yachi,A. Ito,Y. Arimoto

    Jpn. J. Applied Physics   38 ( 3B )   1300 - 1304   1998.04

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  • Study on the device characteristics of a quasi-SOI power MOSFET fabricated by reversed silicon wafer direct bonding Reviewed

    S. Matsumoto,Y. Hiraoka,T. Ishiyama,T. Sakai,T. Yachi,I. Yamada,A. Ito,Y. Arimoto

    IEEE Trans. Electron Devices   ED-45 ( 9 )   1940 - 1945   1998.04

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  • Thin-film quasi-SOI power MOSFET fabricated by reversed silicon wafer direct bonding Reviewed

    S. Matsumoto,T. Yachi,H. Horie,Y. Arimoto

    IEEE Trans. Electron Devices   ED-45 ( 1 )   105 - 109   1998.04

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  • Effect of buried oxide thickness in a Thin-film Silicon on insulator power metal-oxide-semiconductor field-effect transistor Reviewed

    S. Matsumoto,T. Yachi

    Jpn. J. Applied Physics   37 ( 6A )   1997.04

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  • Study on parasitic bipolar effect in a 200-V-class power MOSFET using Silicon direct bonding SOI wafer Reviewed

    S. Matsumoto,T. Yachi

    IEICE Trans   E80-C ( 3 )   431 - 435   1997.04

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  • Integration of a power supply part for a system on silicon Reviewed

    S. Matsumoto,M.Mino,T. Yachi

    IEICE Trans. Communication and Computer Science   80-A ( 2 )   276 - 282   1997.04

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  • Analytical approach to breakdown voltage in thin-film SOI power MOSFETs Reviewed

    I J. Kim,S. Matsumoto,T. Sakai,T. Yachi

    Solid-State Electronics   39 ( 1 )   95 - 100   1996.04

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  • Device characteristics of a 30 V-class thin-film SOI power MOSFET Reviewed

    S. Matsumoto,I. J. Kim,T. Sakai,T. Fukumitsu,T. Yachi

    IEEE Trans. Electron Devices   ED-43 ( 5 )   746 - 752   1996.04

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  • A new high-performance lateral insulated gate bipolar transistor formed on quasi-SOI Reviewed

    S. Matsumoto,I. J. Kim,T. Yachi

    IEEE Electron Device Letter   16 ( 9 )   402 - 404   1995.04

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  • Failure analysis and new design of a thin-film SOI power MOSFET based on emission microscopy and 2-D device simulation Reviewed

    S. Matsumoto,T. Fukumitsu,I. J. Kim,T. Sakai,T. Yachi

    Jpn. J. Applied Physics   34 ( 4A )   1790 - 1795   1995.04

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  • Switching characteristics of a thin-film SOI power MOSFET Reviewed

    S. Matsumoto,I. J. Kim,T. Sakai,T. Fukumitsu,T. Yachi

    Jpn. J. Applied Physics   34 ( 2B )   817 - 821   1995.04

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  • Breakdown voltage improved for thin-film SOI power MOSFET's by buried oxide step structure Reviewed

    I. J. Kim,S. Matsumoto,T. Sakai,T. Yachi

    IEEE Electron Device Letters   15 ( 5 )   148 - 150   1994.04

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  • A high-performance self-aligned UMOSFET with vertical trench contact structure Reviewed

    S. Matsumoto,T. Ohno,H. Ishii,H. Yoshino

    IEEE Trans. Electron Devices   ED-41 ( 5 )   814 - 818   1994.04

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  • Device simulation of a thin-film silicon on insulator power metal-semiconductor field-effect transistor for structure optimization Reviewed

    S. Matsumoto,H. Yoshino

    Jpn. J. Applied Physics   33 ( 1B )   519 - 523   1994.04

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  • An intelligent power IC with double buried-oxide layers formed by SIMOX technology Reviewed

    T. Ohno,S. Matsumoto,and K. Izumi

    IEEE Trans. Electron Devices   ED-40 ( 11 )   2074 - 2080   1993.04

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  • Ultra low specific on-resistance UMOSFET with trench contact for source and body regions realized by selfaligned process Reviewed

    S. Matsumoto,T.Ohno,K. Izumi

    Electronics Letters   27 ( 18 )   1640 - 1641   1991.04

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  • Development of key components for SIMOX intelligent power LSIs, Reviewed

    T. Ohno,S. Matsumoto,K. Izumi

    25 ( 26 )   1071 - 1072   1989.04

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  • Study on Bi-CMOS devices utilizing SIMOX technology Reviewed

    S. Matsumoto,T. Ohno,K. Izumi

    Electronics Letters   25 ( 14 )   904 - 905   1989.04

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  • CMOS on local SOI using SIMOX technology Reviewed

    S. Matsumoto,T.Ohno,K. Izumi

    Electronics Letters   23 ( 11 )   576 - 577   1987.04

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Conference Prsentations (Oral, Poster)

  • A new control strategy of the on-chip POL based on parallel connections

    International Workshop on Power Supply On Chip 

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    Event date: 2012.11.16 - 2012.11.18   Language:English  

  • Numerical predictions of a new SOI structure using thin-diamond film used as insulator

    nternational Workshop on Power Supply On Chip 

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    Event date: 2012.11.16 - 2012.11.18   Language:English  

  • A high-efficiency 5-GHz-band power MOSFET fabricated by silicon-on-insulator technology

    2003 Japan-United State Joint Workshop on Space Solar Power System(JUSPS'03) 

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    Event date: 2003.04   Language:English  

Grants-in-Aid for Scientific Research

  • 高排熱と電磁ノイズ遮蔽を実現するパワーSupply on Chip用基板の研究

    Grant number:15H03965  2015.04 - 2018.03   基盤研究(B)

  • パワーSOC(Supply on Chip)実現に向けての回路・制御技術の研究

    Grant number:25630111  2013.04 - 2015.03   挑戦的萌芽研究

  • 超高密度パワーSOC(Supply on Chip)用集積回路基板の研究

    Grant number:24360111  2012.04 - 2016.03   基盤研究(B)

Contracts

  • パワーデバイスとSi-LSIを積層した3次元パワーSoCの実用化に係る調査

    2016.01 - 2016.06

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    Grant type:Consigned research