YASUGI Masahiro

写真a

Title

Professor

Laboratory

680-4 Kawazu, Iizuka-shi, Fukuoka

Research Fields, Keywords

Programming Languages, Parallel Processing

Homepage

http://www.yasugi.ai.kyutech.ac.jp/m/

Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 3

Citation count denotes the number of citations in papers published for a particular year.

Undergraduate Education 【 display / non-display

  • 1989.03   The University of Tokyo   Faculty of Engineering   Department of Electronic Engineering   Graduated   JAPAN

Post Graduate Education 【 display / non-display

  • 1994.03  The University of Tokyo  Graduate School, Division of Science  Department of Information Science  Doctoral Program  Completed  JAPAN

  • 1991.03  The University of Tokyo  Graduate School, Division of Engineering  Department of Electrical Engineering  Master's Course  Completed  JAPAN

Degree 【 display / non-display

  • The University of Tokyo -  Doctor of Science  1994.03

  • The University of Tokyo -  Master of Engineering  1991.03

Biography in Kyutech 【 display / non-display

  • 2019.04
    -
    Now

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Professor  

  • 2012.03
    -
    2019.03

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Artificial Intelligence   Professor  

Biography before Kyutech 【 display / non-display

  • 2007.04
    -
    2012.02

    Kyoto University   Graduate School of Informatics   Associate Professor   JAPAN

  • 2003.02
    -
    2007.03

    Kyoto University   Graduate School of Informatics   Associate Professor (as old post name)   JAPAN

  • 1998.04
    -
    2003.01

    Kyoto University   Graduate School of Informatics   Lecturer   JAPAN

  • 1995.04
    -
    1998.04

    Kobe University   Faculty of Engineering   Research Assistant   JAPAN

  • 1993.04
    -
    1995.03

    the Japan Society for the Promotion of Science   Special researcher of the Japan Society for the Promotion of Science   JAPAN

Academic Society Memberships 【 display / non-display

  • 1991.09
    -
    Now
     

    Japan Society for Software Science and Technology  JAPAN

  • 1991.11
    -
    Now
     

    Association for Computing Machinery  UNITED STATES

  • 1995.08
    -
    Now
     

    Information Processing Society of Japan  JAPAN

  • 2008.10
    -
    Now
     

    Automatic Tuning Research Group  JAPAN

Specialized Field (scientific research fund) 【 display / non-display

  • Software

 

Publications (Article) 【 display / non-display

  • Work-stealing Strategies That Consider Work Amount and Hierarchy

    Nakashima Ryusuke, Yasugi Masahiro, Yoritaka Hiroshi, Hiraishi Tasuku, Umatani Seiji

    Journal of Information Processing  ( Information Processing Society of Japan )  29   478 - 489   2021.07  [Refereed]

     View Summary

    <p>This paper proposes work-stealing strategies for an idle worker (thief) to select a victim worker. These strategies avoid small tasks being stolen to reduce the total task-division cost. We implemented these strategies on a work-stealing framework called Tascell. First, we propose new types of priority- and weight-based steal strategies. Programmers can let each worker estimate and declare, as a real number, the amount of remaining work required to complete its current task so that declared values are used as "priorities" or "weights". With a priority-based strategy, a thief selects the victim that has the highest known priority at that time. With a weight-based non-uniformly random strategy, a thief uses the relative weights of victim candidates as their selection probabilities. Second, we propose work-stealing strategies to alleviate excessive intra-node work stealing and excessive "steal backs" (or leapfroggings); for example, we allow workers to steal tasks from external nodes with some frequency even if work remains inside the current node. Our evaluation uses a parallel implementation of the "highly serial" version of the Barnes-Hut force-calculation algorithm in a shared memory environment and five benchmark programs in a distributed memory environment.</p>

    DOI CiNii

  • Parallelization of Matrix Partitioning in Construction of Hierarchical Matrices using Task Parallel Languages

    Zhengyang Bai, Tasuku Hiraishi, Hiroshi Nakashima, Akihiro Ida, Masahiro Yasugi

    Journal of Information Processing  ( Information Processing Society of Japan )  27   840 - 851   2019.12  [Refereed]

     View Summary

    © 2019 Information Proessing Soiety of Japan. A hierarchical matrix (H-matrix) is an approximated form that represents N × N correlations of N objects. H-matrix construction is achieved by partitioning a matrix into submatrices, followed by calculating the element values of these submatrices. This paper proposes implementations of matrix partitioning using task parallel languages, Cilk Plus and Tascell. Matrix partitioning is divided into two steps: cluster tree construction by dividing objects into clusters hierarchically, and block cluster tree construction by observing all cluster pairs at the same level of the cluster tree that satisfy an admissibility condition. As the two types of trees constructed and traversed in these steps are un-predictably unbalanced, it is expected that we can efficiently parallelize both these steps using task parallel languages. To obtain sufficient parallelism in the cluster tree construction, we not only execute recursive calls in parallel but also parallelize the inside of each recursive step. For the block cluster tree construction, we assigned each worker its own space so that the workers can store the cluster pairs without using locks. As a result, compared to a sequential implementation in C, we achieved up to an 11.5-fold speedup using Cilk Plus and a 12.6-fold speedup by Tascell for the cluster tree construction. For the block cluster tree construction, up to a 37.7-fold speedup by Cilk Plus and a 38.8-fold speedup using Tascell are achieved. In regard to the entire process of matrix partitioning, we achieved up to a 12.2-fold speedup by Cilk Plus and a 14.5-fold speedup using Tascell. All experiments were executed on two 18-core Xeon processors with real datasets to generate coefficient matrices used in the surface charge method.

    DOI Scopus CiNii

  • Extending a Work-Stealing Framework with Priorities and Weights

    Ryusuke Nakashima, Hiroshi Yoritaka, Masahiro Yasugi, Tasuku Hiraishi, Seiji Umatani

    Proceedings of the 9th Workshop on Irregular Applications: Architectures and Algorithms (IA3 2019) (held in conjunction with SC 2019)      9 - 16   2019.11  [Refereed]

    USA  Denver  2019.11  -  2019.11

     View Summary

    © 2019 IEEE. This paper proposes priority-based and weight-based steal strategies for an idle worker (thief) to select a victim worker in work-stealing frameworks. Typical work-stealing frameworks employ uniformly random victim selection. We implemented the proposed strategies on a work-stealing framework called Tascell; Tascell programmers can let each worker estimate and declare the remaining work amount of its current task as a real number so that the enhanced Tascell framework can use declared values as priorities or weights. To reduce the total task division cost, the proposed strategies avoid stealing small tasks. With a priority-based strategy, a thief selects the victim that has the highest known priority at that time. With a weight-based non-uniformly random strategy, a thief uses the relative weights of victim candidates as their selection probabilities. The proposed selection strategies achieved superior performance compared to uniformly random selection. Our evaluation uses a parallel implementation of the ''highly serial'' version of the Barnes-Hut force calculation algorithm in a shared memory environment and five benchmark programs in a distributed memory environment.

    DOI Scopus

  • HOPE: A Parallel Execution Model Based on Hierarchical Omission

    Masahiro Yasugi, Daisuke Muraoka, Tasuku Hiraishi, Seiji Umatani, Kento Emoto

    Proceedings of the 48th International Conference on Parallel Processing (ICPP 2019)      77:1 - 77:11   2019.08  [Refereed]

    Kyoto  2019.08  -  2019.08

     View Summary

    © 2019 ACM. This paper presents a new approach to fault-tolerant language systems without a single point of failure for irregular parallel applications. Work-stealing frameworks provide good load balancing for many parallel applications, including irregular ones written in a divide-and-conquer style. However, work-stealing frameworks with fault-tolerant features such as checkpointing do not always work well. This paper proposes a completely opposite "work omission" paradigm and its more detailed concept as a "hierarchical omission"-based parallel execution model called HOPE. HOPE programmers' task is to specify which regions in imperative code can be executed in sequential but arbitrary order and how their partial results can be accessed. HOPE workers spawn no tasks/threads at all; rather, every worker has the entire work of the program with its own planned execution order, and then the workers and the underlying message mediation systems automatically exchange partial results to omit hierarchical subcomputations. Even with fault tolerance, the HOPE framework provides parallel speedups for many parallel applications, including irregular ones.

    DOI Scopus

  • Evaluating Portable Mechanisms for Legitimate Execution Stack Access with a Scheme Interpreter in an Extended SC Language

    Masahiro Yasugi, Reichi Ikeuchi, Tasuku Hiraishi, Tsuneyasu Komiya

    Journal of Information Processing    27   177 - 189   2019.02  [Refereed]

     View Summary

    © 2019 Information Processing Society of Japan. Scheme implementations should be properly tail-recursive and support garbage collection. To reduce the development costs, a Scheme interpreter called JAKLD, which is written in Java, was designed to use execution stacks simply. JAKLD with interchangeable garbage collectors was reimplemented in C. In addition, we have proposed an efficient C-based implementation written in an extended C language called XC-cube, which features language mechanisms for implementing high-level programming languages such as “L-closures” for legitimate execution stack access, with which a running program/process can legitimately access data deeply in execution stacks (C stacks). L-closures are lightweight lexical closures created from nested function definitions. In addition to enhanced C compilers, we have portable implementations of L-closures, which are translators from an extended S-expression based C language into the standard C language. Furthermore, we have another mechanism for legitimate execution stack access, called “closures”. Closures are standard lexical closures created from nested function definitions. Closures can also be implemented using translators. In this study, JAKLD was reimplemented in an extended SC language (S-expression based C language) that features nested functions to evaluate (L-)closures and their implementations, including translators.

    repository DOI Scopus CiNii

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Publications (Books) 【 display / non-display

  • Concurrent Objects and Beyond (Festschrift for Prof. Yonezawa)

    Masahiro Yasugi ( Joint Work )

    Springer  2014.09 ISBN: 978-3-662-44470-2

  • Parallel Language and Compiler Research in Japan

    Satoshi Matsuoka, Masahiro Yasugi, Kenjiro Taura, Tomio Kamada, Akinori Yonezawa ( Joint Work )

    Kluwer Academic Publishers  1995.08 ISBN: 0792395069

Conference Prsentations (Oral, Poster) 【 display / non-display

  • Copy Reduction and Latency Hiding for MPI-Based Implementations of the Tascell Task-Parallel Language

    Huangcheng Cai, Tasuku Hiraishi, Hiroshi Nakashima, Masahiro Yasugi

    第23回プログラミングおよびプログラミング言語ワークショップ(PPL2021)  (オンライン)  2021.03  -  2021.03 

  • UTSベンチマークを用いた階層的計算省略に基づく並列実行モデルの性能評価

    志岐 優介, 八杉 昌宏, 平石 拓

    第23回プログラミングおよびプログラミング言語ワークショップ(PPL2021)  (オンライン)  2021.03  -  2021.03 

  • out-of-core行列積とタスク並列言語Tascellによる並列化の評価

    上中野 寛太, 八杉 昌宏, 平石 拓

    第23回プログラミングおよびプログラミング言語ワークショップ(PPL2021)  (オンライン)  2021.03  -  2021.03 

  • 移植性に優れた計算状態操作機構を用いた並列言語処理系の性能評価

    竹内 千裕, 八杉 昌宏, 平石 拓

    第23回プログラミングおよびプログラミング言語ワークショップ(PPL2021)  (オンライン)  2021.03  -  2021.03 

  • Work-Stealing Strategies That Consider Work Amount and Hierarchy

    Ryusuke Nakashima, Masahiro Yasugi, Hiroshi Yoritaka, Tasuku Hiraishi, Seiji Umatani

    情報処理学会第132回プログラミング研究会  (オンライン)  2021.01  -  2021.01 

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Lectures 【 display / non-display

  • 並列/高信頼プログラミング言語と実装技術

    東京大学コンピュータ科学専攻講演会 ( 東京大学 )  2011.07.21 

  • Frameworks for Multicore Platforms

    Workshop on Resource Management of Manycore, GPU, and NVRAM ( Seoul, Korea )  2011.02.18 

  • 並列プログラミング言語と実装技術

    東京大学情報理工実践プログラム特別講演 ( 東京大学 情報理工学系研究科 秋葉原拠点 )  2010.09.17 

  • 高水準プログラミングによる細部の自由と計算状態操作機構

    自動チューニング技術の現状と応用に関するシンポジウム   2009.10.22 

Honors and Awards 【 display / non-display

  • ICPP 2019 Best poster award

    2019.08.07     JAPAN

    Winner: Zhengyang Bai, Tasuku Hiraishi, Hiroshi Nakashima, Akihiro Ida, Masahiro Yasugi

  • xSIG 2019 Outstanding Research Award

    2019.05.28     JAPAN

    Winner: Zhengyang Bai, Tasuku Hiraishi, Hiroshi Nakashima, Akihiro Ida, Masahiro Yasugi

  • ACSI2015 Outstanding Research Award

    2015.01.26     JAPAN

    Winner: Shingo Okuno, Tasuku Hiraishi, Hiroshi Nakashima, Masahiro Yasugi, Jun Sese

  • the 2009 IPSJ Transactions on Programming Outstanding Paper Award

    2010.05.31     JAPAN

    Winner: Masahiro YASUGI, Tasuku HIRAISHI, Takenari SHINOHARA, Taiichi YUASA

 

Activities of Academic societies and Committees 【 display / non-display

  • 2021.03
    -
    2021.08

    IACC (International Association for Computers and Communications)   50th International Conference on Parallel Processing (ICPP 2021) Program Committee member

  • 2021.03
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    2021.07

    Information Processing Society of Japan  

  • 2020.06
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    2022.05

    IEEE   Transactions on Parallel and Distributed System's Editorial Board Associate Editor

  • 2020.04
    -
    2022.03

    Japan Society for Software Science and Technology  

  • 2020.03
    -
    2020.07

    Information Processing Society of Japan  

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