担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

We propose an auxiliary data stream structure as a robust classification model. The model treats one modal as the main input and the other modals as supports. The model chooses how much of the sub-modal is used for classification. We experimented with two and three modal inputs. Moreover, we added pseudo-shadows to the visual information for the experiment with three modal inputs. In all experiments, our proposed model improves the accuracy and robustness to environmental disturbances by using multiple modals.

DOI： 10.5954/icarob.2023.os17-3

CiNii Research

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

A field-programmable gate array (FPGA) device which has a Zynq architecture becomes popular these days. It is featured by integration of processing system (PS) and programmable logic (PL) into a single chip. While we tend to focus on the performance of PL, we can not ignore PS load completely. In this paper, using a Zynq FPGA board, we explore how our object detection system performance changes with PS load and report our experiment results.

DOI： 10.5954/icarob.2023.os17-5

CiNii Research

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

Home service robots have pick-and-place tasks to grasp and carry objects. When performing pick-andplace tasks, robots need to process to search for objects in the case of missing a target object. We propose approaches for the robot to search for a target object from a shelf and a method for selecting empty spaces to move off-target objects. The proposed method is based on two recognition models to select a space and plan motions. The object is to be moved and the space is selected based on the size and position of empty spaces. In the experiments, the robot planned actions to search for a target object from a shelf and to place an object near a group of similar objects. We used these in the RoboCup@Home competition to evaluate the effectiveness of the proposed method.

DOI： 10.5954/icarob.2023.os17-2

CiNii Research

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

This paper proposes a method for recognizing the poses of a flexible-indefinite object. Some flexible-indefinite objects, such as fried shrimp, differ between individuals. Therefore, it is difficult to estimate the pose of these foods by point cloud fitting or other methods. We propose "pseudo-skeleton" data for these objects. Pseudo-skeleton data consists of "key-points," which are joints, and "bones," which connect between key-points. For example, fried shrimp are given 3 key-points; "head," "belly," and "tail." In addition, the bones that connect them are given. In the experiment, objects pose recognition model based on the human pose recognition model trains pseudo-skeleton data of fried shrimp. We confirmed that the model estimates the poses in the images.

DOI： 10.5954/icarob.2023.os17-1

CiNii Research

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

We propose an efficient semantic map to realize flexible human-robot interaction (HRI) in domestic environments. Our proposed map is created from an output of Simultaneous Localization and Mapping and already-known environmental information such as furniture and room. In this study, we evaluated the effectiveness of our proposed method on two benchmark tests for HRI in RoboCup@Home held in Bangkok in 2022. In the RoboCup@Home, we employ 3D human recognition to apply our proposed map to HRI, such as "find and offer an empty seat." Our proposed method had the best score of all teams on both tests. The results of our experiments are available at https://youtube.com/playlist?list=PLfbN50Mwh2DG3OPDeCHo4TNuyrU4qYCrJ.

DOI： 10.5954/icarob.2023.os17-4

CiNii Research

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

Manual annotation is common, but problems occur, such as oversight and mislabeling via human error. These problems are known to affect the quality of datasets significantly. To resolve these problems, we propose a method to automatically generate high-quality and large datasets in a short time using a simulator. Our proposed method uses domain randomization to minimize domain gaps without faithfully reproducing real scenes. The generated dataset achieved more than 80% recognition accuracy against the real image dataset.

DOI： 10.5954/icarob.2023.os17-6

CiNii Research

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Kyutacar

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Kyutacar

記述言語：日本語   掲載種別：研究論文（研究会，シンポジウム資料等）

任意視点画像生成において Neural Radiance Fields は非常に強力な手法ではあるが，学習のためには多くの画像が必要である．本発表では，パラメトリック固有空間法のアナロジーとして，教師データが存在しない未知視点において，近傍視点の画像から擬似的に生成した特徴ベクトルを教師信号として学習に用いることで，少数の画像でも学習できる Manifold NeRF を提案する．実験の結果，疑似教師信号を用いることで，データセットが少量でも精度良く任意視点画像が生成できることを確認した．

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Kyutacar

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Kyutacar

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Lisbon, Portugal  

High-speed and accurate human recognition is necessary to realize safe autonomous mobile robots. Recently, human recognition methods based on deep learning have been studied extensively. However, these methods consume large amounts of power. Therefore, this study focuses on the Gaussian mixture model of multiresolution co-occurrence histograms of oriented gradients (GMM-MRCoHOG), which is a feature extraction method for human recognition that entails lower computational costs compared to deep learning-based methods, and aims to implement its hardware for high-speed, high-accuracy, and low-power human recognition. A digital hardware implementation method of GMM-MRCoHOG has been proposed. However, the method requires numerous look-up tables (LUTs) to store state spaces of GMM-MRCoHOG, thereby impeding the realization of human recognition systems. This study proposes a LUT reduction method to overcome this drawback by standardizing basis function arrangements of Gaussian mixture distrib (More)

DOI： 10.5220/0011698400003417

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Kyutacar

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Kyutacar

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

An Ag2Se nanowire random network was fabricated for application as a data augmentation device and combined with a binary convolutional neural network (BCNN) to achieve high accuracy in voice classification tasks. Due to the nonlinear high-dimensional characteristics resulting from the formation of the conductive filament at the cross junction, the Ag2Se device could transform input data into higher-order multiple signals, thereby enhancing the accuracy of the classification task by augmenting input signals. The results indicate that materials can realize data augmentation with the same performance as software, suggesting that material-based hardware can be used as an elemental technology for information processing.

DOI： 10.35848/1882-0786/acae6a

Kyutacar

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Manual annotation is common, but problems occur, such as oversight and mislabeling via human error. These problems are known to affect the quality of datasets significantly. To resolve these problems, we propose a method to automatically generate high-quality and large datasets in a short time using a simulator. Our proposed method uses domain randomization to minimize domain gaps without faithfully reproducing real scenes. The generated dataset achieved more than 80% recognition accuracy against the real image dataset.

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

This study aims to implement a reservoir-based convolutional neural network (CNN) on physical reservoir computing (RC) to develop an efficient image recognition system for edge AI. Therefore, we propose a novel reservoir-based convolution circuit system that uses in-material reservoir computing, a type of physical RC made from a sulfonated polyaniline network. The experimental results demonstrate that the proposed circuit system extracts image features in the same way as the original CNN and that a reservoir-based CNN on the in-material RC achieves an accuracy rate of 81.7% in an image classification task while an echo state network-based CNN achieves 87.7%.

DOI： 10.1109/ISCAS46773.2023.10181436

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

<p>In this study, we introduce a reservoir-based one-dimensional (1D) convolutional neural network that processes time-series data at a low computational cost, and investigate its performance and training time. Experimental results show that the proposed network consumes lower training computational costs and that it outperforms the conventional reservoir computing in a sound-classification task.</p>

DOI： 10.1587/transfun.2023eal2050

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/transfun/advpub/0/advpub_2023EAL2050/_pdf

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

A field-programmable gate array (FPGA) device with a Zynq architecture integrates a processing
system (PS) and programmable logic (PL) into a single chip. Although the PL performance is
typically considered, the PS load cannot be completely ignored. In this study, using an FPGA
board with a Zynq architecture, the conditions under which an object detection system performs
the best, while considering the PS and PL load balance, are explored.

DOI： 10.57417/jrnal.10.2_105

CiNii Research

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

With advancements in deep learning (DL), artificial intelligence (AI) technology has become an indispensable tool. However, the application of DL incurs significant computational costs, making it less viable for edge AI scenarios. Consequently, the demand for cost-effective AI solutions, other than DL-based approaches, is increasing. Reservoir computing (RC) has attracted interest owing to its ability to provide low-cost training alternatives, holding great promise for edge AI applications. However, the training capability of RC is constrained by its reliance on a single linear layer, while weight connections in the remaining layers remain static during training. Moreover, accomplishing continuous learning tasks is difficult owing to the catastrophic forgetting in the linear layer. Therefore, we propose the integration of self-organizing multiple readouts to enhance RC's training capability. Our method distributes training data across multiple readouts, which prevents catastrophic forgetting of readouts and empowers each readout to adeptly assimilate new data, thereby elevating the overall training performance. The self-organizing function, which assigns similar data to the same readout, optimizes the memory utilization of these multiple readouts. Experimental results show that an RC equipped with the proposed multiple readouts successfully solved a continuous learning task by mitigating catastrophic forgetting because of the data distribution to the multiple readouts. Additionally, the RC achieved higher accuracy in a sound recognition task compared with the existing RC paradigm because of ensemble learning in the multiple readouts. Multiple readouts are effective in enhancing the training capability of RC and can contribute to the realization of RC applications.

DOI： 10.1109/ACCESS.2023.3340311

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We demonstrate a chaotic Boltzmann machine annealer, which is a field-programmable gate array (FPGA)-based high-performance annealing machine, and a control system powered by two open-source software packages. The annealer is employed in solving a large-scale real-world optimization problem, the traffic flow optimization. This involves distributing 500 car routes between the Haneda Airport area to the Pacifico Yokohama area, the venue of the International Conference on Field Programmable Technology 2023, while minimizing the total driving distance and preventing traffic jams. We obtain solutions that are comparable in accuracy to solutions of simulated annealing running on a graphics processing unit (GPU-SA) and a central processing unit (CPU-SA). The annealing machine on an FPGA is approximately 571 and 97600 times as fast as the GPUSA and the CPU-SA, respectively. We will demonstrate solving traffic flow optimization in the towns familiar to the visitors.

DOI： 10.1109/ICFPT59805.2023.00038

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We propose look-up tables networks-based reservoir computing (LUTNet-RC). This work is the first trial of applying LUTNets to RC. LUTNet-RC consists of a LUT-based reservoir layer and a non-LUT-based output layer. LUTNets have disadvantages such as limited sparse connectivity and weights cannot be changed after implementation. However, when applied to a reservoir layer of RC (LUT-based reservoir layer), these disadvantages are eliminated, because this layer works with sparse connectivity and the weights are fixed, so only the advantage of small circuit resources is obtained. For the LUT-based reservoir layer, we propose and model a multi-bit weight reservoir, modifying the conventional binarized reservoir to improve calculation accuracy. In the case of LUTNets, the proposed multi-bit weight reservoir can be implemented without the increase in utilized circuit resources because LUTNets focus only on the input-output relationship on neurons. Additionally, we propose a speed-up method in the output layer with time division calculation, which compares the current network state with previous states and then calculates only status-changed neurons. As a result, we implement a LUTNet-RC with 1500 reservoir neurons on a field-programmable gate array (KR260) running at 100MHz. The utilized circuit resources are dominated by LUTs, which use approximately 26% of the total amount of LUTs. The LUTNet-RC can infer more than 106 data per second. We also verify the LUTNet-RC performance using nonlinear auto-regressive moving average 10 (NARMA10) and the performance is comparable to conventional works. We conclude that the LUTNet-RC is one of the highest-performance RC on an FPGA.

DOI： 10.1109/ICFPT59805.2023.00024

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

California, United States of America  

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We propose an efficient semantic map to realize flexible human-robot interaction (HRI) in domestic environments. Our proposed map is created from an output of Simultaneous Localization and Mapping and already-known environmental information such as furniture and room. In this study, we evaluated the effectiveness of our proposed method on two benchmark tests for HRI in RoboCup@Home held in Bangkok in 2022. In the RoboCup@Home, we employ 3D human recognition to apply our proposed map to HRI, such as "find and offer an empty seat." Our proposed method had the best score of all teams on both tests. The results of our experiments are available at https://youtube.com/playlist?list=PLfbN50Mwh2DG3OPDeCHo4TNuyrU4qYCrJ.

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

A field-programmable gate array (FPGA) device which has a Zynq architecture becomes popular these days. It is featured by integration of processing system (PS) and programmable logic (PL) into a single chip. While we tend to focus on the performance of PL, we can not ignore PS load completely. In this paper, using a Zynq FPGA board, we explore how our object detection system performance changes with PS load and report our experiment results.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85149463385&origin=inward

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Home service robots have pick-and-place tasks to grasp and carry objects. When performing pick-and-place tasks, robots need to process to search for objects in the case of missing a target object. We propose approaches for the robot to search for a target object from a shelf and a method for selecting empty spaces to move off-target objects. The proposed method is based on two recognition models to select a space and plan motions. The object is to be moved and the space is selected based on the size and position of empty spaces. In the experiments, the robot planned actions to search for a target object from a shelf and to place an object near a group of similar objects. We used these in the RoboCup@Home competition to evaluate the effectiveness of the proposed method.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85149480150&origin=inward

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a method for recognizing the poses of a flexible-indefinite object. Some flexible-indefinite objects, such as fried shrimp, differ between individuals. Therefore, it is difficult to estimate the pose of these foods by point cloud fitting or other methods. We propose "pseudo-skeleton" data for these objects. Pseudo-skeleton data consists of "key-points," which are joints, and "bones," which connect between key-points. For example, fried shrimp are given 3 key-points; "head," "belly," and "tail." In addition, the bones that connect them are given. In the experiment, objects pose recognition model based on the human pose recognition model trains pseudo-skeleton data of fried shrimp. We confirmed that the model estimates the poses in the images.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85149467263&origin=inward

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We propose an auxiliary data stream structure as a robust classification model. The model treats one modal as the main input and the other modals as supports. The model chooses how much of the sub-modal is used for classification. We experimented with two and three modal inputs. Moreover, we added pseudo-shadows to the visual information for the experiment with three modal inputs. In all experiments, our proposed model improves the accuracy and robustness to environmental disturbances by using multiple modals.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85149480798&origin=inward

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Ising machines are attracting attention for their ability to solve large-scale combinatorial optimization problems because these problems are difficult to solve. To accelerate the computing of Ising machines, implementation of Ising machines with digital circuits such as simulated annealing (SA) machines is in progress. However, these Ising machines on digital circuits require random number generators, which are implemented with large circuit resources. This work focuses on chaotic Boltzmann machines (CBMs), which imitate the stochastic behavior of Boltzmann machines (BMs) with deterministic chaotic dynamics. CBMs are one of the models that work as chaotic simulated annealing (CSA) machines within Ising machines. Therefore, we can implement the Ising machines without random number generators by using CBMs. In conventional work, CSA machines using CBMs (CBM-CSAs) are implemented with some hardware-oriented algorithms, but the CBM-CSA circuit is not optimized for these hardware-oriented algorithms. In the conventional CBM-CSA circuit, memory circuits are implemented separately, which prevents making the CBM-CSA from larger, and neuron circuits require the reset of accumulated values, which causes the increase in the calculation time. To solve these problems, we implement only one large memory circuit to make the CBM-CSA larger and improve the neuron circuits to allow dynamic changes of inputs to arithmetic circuits to inhibit the increase in the calculation time. As a result, we implement a CBM-CSA with 4096 nodes on an FPGA (Alveo U250), and the CBM-CSA can control 16-bit width weights and run at 100MHz. We evaluate the implemented CBM-CSA by solving K4000, max-cut problem, which is one of the combinatorial optimization problems. The best solution of CBM-CSA is comparable to that of the SA on the central processing unit (CPU). Moreover, the CBM-CSA is approximately 600 times as fast as the SA on the CPU and approximately twice as fast as the conventional Ising machine on an FPGA based on the improvements in this work. Furthermore, this work implements one of the highest-performance Ising machines on a single FPGA.

DOI： 10.1109/IJCNN54540.2023.10191342

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Traversability estimation is essential for safe path planning in robotics and autonomous driving. In this study, we propose an accurate and dense traversability estimation system for extreme environments such as disaster areas. Traversability estimations often occur undefined regions due to the shielding and sparsity of sensor data. These regions may lead to the selecting of dangerous paths. The proposed system uses point cloud accumulation and the Bayesian generalized kernel (BGK) elevation estimation to create a dense Digital elevation map (DEM) with no undefined regions from point clouds obtained from light detection and ranging (LiDAR). Subsequently, traversability is estimated from road surface roughness, slope and vehicle performance using fuzzy logic in our system. In our experiments, our system is installed in an experimental vehicle, and the experiments conducted on rocky terrain, slopes, and craters to verify its effectivity in extreme environments. Results show that our system can create a dense DEM with few undefined regions and estimate valid traversability for all obstacles.

DOI： 10.1109/IV55152.2023.10186556

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Emerging non-volatile memory devices, such as resistive random access memory (ReRAM) and voltage-controlled magnetoresistive random access memory (VC-MRAM), promise low energy consumption for artificial intelligence applications. However, when implementing deep neural networks (DNNs) using such memory devices, write-error may cause millions of bit-flipping to DNN. This easily degrades the DNN performance. To address this problem, we propose a novel repetition coding for deep-learning (RC-DL), which is a repetition coding designed to protect IEEE 32-bit floating-point (FP32) DNN models. Compared to conventional repetition coding, the proposed RC-DL exploits FP32 non-uniform magnitude encoding by increasing the repeat rates to protect sensitive bit positions and reduce the repeat rates to insensitive bit positions. Hence, RC-DL uses a number of bits equivalent to a 3-bit repetition code while delivering the performance close to 11-bit repetition code. We perform extensive Monte Carlo simulations to simulate the write-error property with ImageNet 2012 pretrained models. The DNN models with RC-DL are shown to be operable in the extremely imperfect environment while delivering with only minor reductions in DNN performance.

DOI： 10.1109/IJCNN54540.2023.10191433

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

DOI： 10.11517/jsaisigtwo.2022.challenge-060_07

CiNii Research

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

DOI： https://doi.org/10.1587/nolta.13.397

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

With the advent of deep learning, significant improvements in image recognition performance have been achieved. In image recognition, it is generally assumed that all the test data are composed of known classes. This approach is termed as closed-set recognition. In closed-set recognition, when an untrained, unknown class is input, it is recognized as one of the trained classes. The method whereby an unknown image is recognized as unknown when it is input is termed as open-set recognition. Although several open-set recognition methods have been proposed, none of these previous methods excel in terms of all three evaluation items: learning cost, recognition performance, and scalability from closed-set recognition models. To address this, we propose an open-set recognition method using the distance between features in the multidimensional feature space of neural networks. By applying center loss to the feature space, we aim to maintain the classification accuracy of closed-set recognition and improve the unknown detection performance. In our experiments, we achieved state-of-the-art performance on the MNIST, SVHN, and CIFAR-10 datasets. In addition, the proposed approach shows excellent performance in terms of the three evaluation items.

DOI： 10.5220/0010816600003124

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In this research, we focus on Gaussian mixture model-multiresolution co-occurrence histograms of oriented gradients (GMM-MRCoHOG) features using luminance gradients in images and propose a hardware-oriented algorithm of GMM-MRCoHOG to implement it on a field programmable gate array (FPGA). The proposed method simplifies the calculation of luminance gradients, which is a high-cost operation in the conventional algorithm, by using lookup tables to reduce the circuit size. We also designed a human-detection digital architecture of the proposed algorithm for FPGA implementation using high-level synthesis. The verification results showed that the processing speed of the proposed architecture was approximately 123 times faster than that of the FPGA implementation of VGG-16.

DOI： 10.5220/0010848100003124

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

We propose binary or ternary weights with 8-bit integer activation convolutional neural networks. This model is designed as a middle ground between 8-bit integer and 1-bit or 2-bit quantized models. We discover that conventional 1-bit or 2-bit only-weight quantization methods (i.e., BinaryConnect and Ternary weights network) can be utilized jointly with 8-bit integer activation quantization without significant fractions. Based on these two methods, we evaluate our model with a VGG16-like model and CIFAR10 dataset. Our model provides competitive results to a conventional floating-point model.

DOI： 10.5954/icarob.2022.os15-1

CiNii Research

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

This paper proposes a method to estimate appropriate primitive shapes by automatically using a point cloud of objects. The process is as follows. First is to estimate a rotation angle of the object and, then place a primitive shape (i.e., cylinder or sphere) in the center of the object. The primitive shape is either stretched or compressed to fit the object. The distance between all the point cloud of the object and the primitive shape are measured. We apply these methods with various primitive shapes and find the most suitable primitive shape. We show that objects like apples and chikuwa can be recognized with primitive objects, such as spheres and cylinders.

DOI： 10.5954/icarob.2022.os15-5

CiNii Research

記述言語：英語   掲載種別：研究論文（学術雑誌）

Hardware-based machine intelligence with the network architecture of reservoir computing (RC) is gaining interest because of its biological computational resemblance along with an easy and efficient neural network training approach. Herein, such a physical RC (in-materio RC) platform consisting of a recurrent network formed by the single-walled carbon nanotube (SWNT)–porphyrin polyoxometalate (Por–POM) complex is demonstrated. The network architecture executes the fundamental reservoir properties of nonlinearity, higher harmonic generation, and 1/fγ power law information processing ability. Based on these functionalities, an RC benchmark task of waveform generation is performed where the device achieves maximum fitting accuracy of 99.4%. Furthermore, a supervised object classification task based on a one-hot vector target is also executed using Toyota Human Support Robot tactile inputs. The successful classification of objects of different hardness is enhanced when the device output response follows the 1/fγ power law of maximized information processing.

DOI： 10.1002/aisy.202100145

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

<p>Reservoir computing (RC) has attracted attention and has been used in many applications because of its low training cost. Multiple studies using RC for image recognition have been proposed, and some have achieved accuracy rates of greater than 99% on the MNIST dataset. For the Fashion-MNIST and CIFAR-10 datasets, however, they have not yet achieved high accuracy. This study proposes a novel convolutional neural network based on RC that can be optimized by ridge regression rather than back-propagation. The reservoir-based network has multiple reservoirs with various leak rates to extract features with various spatial frequencies from the inputs. The experimental results show that the performance of the proposed model achieves higher accuracy rates in the mentioned datasets compared with those of other reservoir-based image recognition approaches.</p>

DOI： 10.1587/nolta.13.397

CiNii Research

その他リンク： http://hdl.handle.net/10228/00009117

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Artificial general intelligence, which imitates the human brain, is aspired. Episodic memories are considered to be a key feature in building human brain functions. This paper proposes a memory-based entorhinal-hippocampal model that encodes spatial and non-spatial information, essential to realize episodic memories. The model works as a memory that stores the location of objects and events as neural activity packets. This paper also proposes an area-efficient hardware implementation method for field-programmable gate arrays (FPGAs). Our proposal utilizes on-chip random access memories (RAMs) to achieve a large-scale implementation of our model. Circuit simulations validated the behavior of our hardware-friendly model. The results of logic synthesis revealed the area efficiency of the FPGA implementation method that utilizes on-chip RAMs.

DOI： 10.1109/ISCAS48785.2022.9937768

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

This study proposes an implementation method of a hardware-oriented restricted Boltzmann machine (RBM) without random number generators (RNGs) that employ cut-off bits, which are obtained from fixed-point binary arithmetic operations on digital hardware, such as field-programmable gate arrays (FPGAs), instead of random numbers. Most FPGA circuits employ fixed-point binary arithmetic operations to improve hardware resource efficiency. Therefore, the proposed method applies the unique feature of the operation, which is bit width extension and cut-off bits. Stochastic neural networks, including RBMs, employ sampling processes based on a probability distribution associated with the network, and the processes require many random numbers. However, implementing RNGs in hardware is costly because it requires considerable hardware resources. The proposed method can mitigate this requirement. To validate the proposed method, we implement an RBM with the proposed method on the software, emulate fixed-point binary arithmetic operations, and train the RBM using the MNIST and Fashion MNIST datasets. Furthermore, we apply the chi-square goodness-of-fit test to evaluate the uniformity of the cut-off bits. Additionally, we compare hardware resource requirements and power consumption for the proposed method and some major RNGs, a linear feedback shift register (LFSR), and a xorshift. Experimental results showed that it was possible to use the cut-off bits for training the RBM using the datasets and clarified the properties of the cut-off bits using statistical analyses. Moreover, hardware implementation of the proposed method involved the lowest hardware resource requirements and power consumption among the RNGs compared in this study.

DOI： 10.1109/ACCESS.2022.3168026

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

This paper introduces an autonomous tiny robot car equipped with a camera-based lane detection function and a traffic signal/obstacle, pedestrian recognition function. Each function is integrated by Robot Operating System 2 (ROS2), a middleware for robot system development. Autonomous driving without the need for a driver requires not only lane-following driving but also traffic signal recognition and obstacle recognition. These functions are implemented on FPGA, and we evaluated them. According to these results, the execution time of traffic signal recognition by FPGA was 1.2 to 3.4 times faster than CPU execution. YOLOv4 is used for obstacle recognition, which improved mAP by 3.79 points compared to YOLO v3-Tiny.

DOI： 10.1109/ICFPT56656.2022.9974433

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

Deep learning technology has made remarkable progress in recent years and has been adopted for a variety of applications such as smartphones and cloud servers. These systems employ dedicated processors to reduce power consumption and process massive amounts of data. In this paper, we propose a field-programmable gate array (FPGA) infrastructure for easy verification of user logic. The infrastructure makes it easy to communicate and control a host PC and user logic. We implemented two example logics, which were simple image processing and a restricted Boltzmann machine, into the infrastructure to confirm these features

DOI： 10.57417/jrnal.9.1_37

Scopus

CiNii Research

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85178265499&origin=inward

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

This paper proposes ternary or binary weights with 8-bit integer activation convolutional neural networks. Our proposed model serves as the middle ground between 8-bit integer and lower than 8-bit precision quantized models. Our empirical experiments established that the conventional 1-bit or 2-bit only-weight quantization methods (i.e., BinaryConnect and ternary weights network) can be used jointly with the 8-bit integer activation quantization. We evaluate our model with the VGG16-like model to operate with the CIFAR10 and CIFAR100 datasets. Our models showcompetitive results to the general 32-bit floating point model.

DOI： 10.57417/jrnal.9.2_171

Scopus

CiNii Research

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85176926162&origin=inward

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

The World Robot Challenge is an international competition for the social implementation of robots. Among them, the Partner Robot Challenge (Real Space) is a category that focuses on domestic service robots, competing to achieve simple tasks such as tidying a room, avoiding small obstacles, grasping a specified object from the shelf, and delivering an object to a waving person. In this category, we focused on the theme of ‘Keep Moving’ and worked on researching and developing technologies for object recognition, grasping, and other tasks. For object recognition, we propose an automatic dataset generator using a physics simulator and generate about 490,000 images in two hours. We trained it with an instance segmentation model, achieving an accuracy of about 79.3% in all games. For object grasping, we installed a three-dimensional sensor on the robot hand, and achieved successful grasping with high accuracy of about 79.6% (88.9% excluding failures due to hardware problems) in all games. In addition, we propose a motion synthesis method that simultaneously performs movement and posture transition to achieve high-speed motion. When navigation is executed, the robot changes to the navigation posture while aiming for the goal. Before reaching the goal, it changes the posture for the following action. As a result, we realized a speedup of about 1.32 times in the pick-and-place task. In the tidy-up task, the robot could clear an average of 14 objects and a maximum of 16 objects in 15 minutes. In the obstacle avoidance task, the robot succeeded five times out of six games, and in the delivery task, it succeeded four times out of six games. Throughout all the tasks, we scored 800 points twice, the highest score in the world, and won the championship. This research is aimed at the practical application of domestic service robots. We believe that the results presented in this paper demonstrate the practicality of domestic service robots in a well-developed environment. The video of the finals is available at https://youtu.be/ElUb8bfSC34?t=5511 (right side). The our source code using the simulator is available at https://github.com/Hibikino-Musashi-Home/hma_wrs_sim_ws.

DOI： 10.1080/01691864.2022.2115315

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85137831520&origin=inward

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a method to estimate appropriate primitive shapes by automatically using a point cloud of objects. The process is as follows. First is to estimate a rotation angle of the object and, then place a primitive shape (i.e., cylinder or sphere) in the center of the object. The primitive shape is either stretched or compressed to fit the object. The distance between all the point cloud of the object and the primitive shape are measured. We apply these methods with various primitive shapes and find the most suitable primitive shape. We show that objects like apples and chikuwa can be recognized with primitive objects, such as spheres and cylinders.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85125142021&origin=inward

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We propose binary or ternary weights with 8-bit integer activation convolutional neural networks. This model is designed as a middle ground between 8-bit integer and 1-bit or 2-bit quantized models. We discover that conventional 1-bit or 2-bit only-weight quantization methods (i.e., BinaryConnect and Ternary weights network) can be utilized jointly with 8-bit integer activation quantization without significant fractions. Based on these two methods, we evaluate our model with a VGG16-like model and CIFAR10 dataset. Our model provides competitive results to a conventional floating-point model.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85125143140&origin=inward

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1109/ISPACS51563.2021.9651058

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1109/ISPACS51563.2021.9650985

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In recent years, many high-precision color image quantization (CIQ) methods have been proposed. However, they do not consider human visual impression, exposing the image to the possibility of altering its visual impression. In this paper, we propose a novel CIQ method that considers human visual impression. An impression is calculated by using a saliency map of an original image and the frequency of each of its colors to prevents CIQ from changing the impression of the image. Quantitative and qualitative evaluations of the experimental results demonstrate that the proposed method preserves the impressionistic colors better than the general CIQ methods.

DOI： 10.1109/ISCIT52804.2021.9590610

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

This study presents novel ReLU functions-based on stochastic computing (SC-based ReLU). The conventional SC-based ReLU for an addition method using approximate parallel counter (APC), which outputs the sum of multiple inputs every clock cycle works as a ReLU using accumulator. However, this conventional method loses the high fault tolerance, which is one of the advantages of stochastic computing (SC). Therefore, we propose an SC-based ReLU using a finite state machine (FSM) instead of an accumulator for an addition method using a multiplexer (MUX) which determines the outputs stochastically. For example, if an error occurs in the value of the accumulator in the conventional method, all subsequent operations will be wrong. However, in the case of the proposed SC-based ReLU using FSM, even if an error occurs in the current state of the FSM, it quickly returns the correct state of the FSM. Thus, the proposed SC-based ReLU using FSM for MUX is more fault tolerant than the conventional SC-based ReLU using the accumulator. However, the accuracy of the addition methods using MUX is poor because the output is determined stochastically, and a large length of bitstream (BSL) is required for accurate calculation. As the BSL becomes larger, the latency for the calculation increases, decreasing the performance. Therefore, we propose a SC-based ReLU using FSM for APC. The addition method using APC doesn’t require BSL as large as the addition method using MUX to obtain correct calculation results. Compared with the conventional SC-based ReLU using an accumulator for APC, the proposed SC-based ReLU using FSM for APC shows sufficient accuracy even with a small BSL. The proposed SC-based ReLU using FSM has also a high fault tolerance,

DOI： 10.34385/proc.66.RS1-5

記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

In this research, we propose a Convolutional Network with sub-Networks (CNSN), i.e., a Convolutional Neural Network (CNN) or base-model that can be divided into sub-models on demand. The CNN architecture, entails that feature map shapes are varied throughout the model, therefore, the hidden layer within CNN may not directly process an input image without modification. To address this problem, we propose a step-down convolutional layer, which is a convolutional layer acting as an input layer for the sub-model. This step-down convolutional layer reshapes and processes an input image to a preferred representation to the sub-model. To train CNSN, we treat the base-model and sub-models as distinct models. Each model is forward-and back-propagated separately. Using multi-model loss, i.e., a linear combination of losses from base-model and sub-models, we thus update model parameters that can be utilized in both base-model and sub-models.

DOI： 10.2991/jrnal.k.210521.012

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85120732958&origin=inward

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

In this study, we introduced a mixed-precision weights network (MPWN), which is a quantization neural network that jointly utilizes three different weight spaces: binary {−1,1}, ternary {−1,0,1}, and 32-bit floating-point. We further developed the MPWN from both software and hardware aspects. From the software aspect, we evaluated the MPWN on the Fashion-MNIST and CIFAR10 datasets. We systematized the accuracy sparsity bit score, which is a linear combination of accuracy, sparsity, and number of bits. This score allows Bayesian optimization to be used efficiently to search for MPWN weight space combinations. From the hardware aspect, we proposed XOR signed-bits to explore floating-point and binary weight spaces in the MPWN. XOR signed-bits is an efficient implementation equivalent to multiplication of floating-point and binary weight spaces. Using the concept from XOR signed bits, we also provide a ternary bitwise operation that is an efficient implementation equivalent to the multiplication of floating-point and ternary weight space. To demonstrate the compatibility of the MPWN with hardware implementation, we synthesized and implemented the MPWN in a field-programmable gate array using high-level synthesis. Our proposed MPWN implementation utilized up to 1.68-4.89 times less hardware resources depending on the type of resources than a conventional 32-bit floating-point model. In addition, our implementation reduced the latency up to 31.55 times compared to 32-bit floating-point model without optimizations.

DOI： 10.1371/journal.pone.0251329

Kyutacar

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

<p>In this study, with the aim of installing an object recognition algorithm on the hardware device of a service robot, we propose a Binarized Dual Stream VGG-16 (BDS-VGG16) network model to realize high-speed computations and low power consumption. The BDS-VGG16 model has improved in terms of the object recognition accuracy by using not only RGB images but also depth images. It achieved a 99.3% accuracy in tests using an RGB-D Object Dataset. We have also confirmed that the proposed model can be installed in a field-programmable gate array (FPGA). We have further installed BDS-VGG16 Tiny, a small BDS-VGG16 model in XCZU9EG, a system on a chip with a CPU and a middle-scale FPGA on a single chip that can be installed in robots. We have also integrated the BDS-VGG16 Tiny with a robot operating system. As a result, the BDS-VGG16 Tiny installed in the XCZU9EG FPGA realizes approximately 1.9-times more computations than the one installed in the graphics processing unit (GPU) with a power efficiency approximately 8-times higher than that installed in the GPU.</p>

DOI： 10.20965/jrm.2021.p0386

Kyutacar

Scopus

CiNii Article

CiNii Research

その他リンク： https://ci.nii.ac.jp/naid/130008027729

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

In this paper, we introduce a network with sub-networks: a neural network whose layers can be detached into sub-neural networks during the inference phase. To develop trainable parameters that can be inserted into both base-model and sub-models, first, the parameters of sub-models are duplicated in the base-model. Each model is separately forward-propagated, and all models are grouped into pairs. Gradients from selected pairs of networks are averaged and used to update both networks. With the Modified National Institute of Standards and Technology (MNIST) and Fashion-MNIST datasets, our base-model achieves identical test-accuracy to that of regularly trained models. However, the sub-models result in lower test-accuracy. Nevertheless, the sub-models serve as alternative approaches with fewer parameters than those of regular models.

DOI： 10.2991/jrnal.k.201215.006

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

This paper proposes a hardware-oriented dropout algorithm, which is efficient for field programmable gate array (FPGA) implementation. In deep neural networks (DNNs), overfitting occurs when networks are overtrained and adapt too well to training data. Consequently, they fail in predicting unseen data used as test data. Dropout is a common technique that is often applied in DNNs to overcome this problem. In general, implementing such training algorithms of DNNs in embedded systems is difficult due to power and memory constraints. Training DNNs is power-, time-, and memory- intensive; however, embedded systems require low power consumption and real-time processing. An FPGA is suitable for embedded systems for its parallel processing characteristic and low operating power; however, due to its limited memory and different architecture, it is difficult to apply general neural network algorithms. Therefore, we propose a hardware-oriented dropout algorithm that can effectively utilize the characteristics of an FPGA with less memory required. Software program verification demonstrates that the performance of the proposed method is identical to that of conventional dropout, and hardware synthesis demonstrates that it results in significant resource reduction.

DOI： 10.1016/j.neucom.2020.11.055

Kyutacar

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>本研究では，自動運転技術における自車位置推定のために，You Only Look Once（YOLO）を処理に組み込むことで道路標示検出システムの性能向上を行う．従来手法では，輝度値に基づくテンプレートマッチングで道路標示を検出する．しかし，この手法では日光による白飛びや標示の掠れにより検出できないものが存在する．これに対し，提案手法ではYOLOで道路標示の存在する領域を探索し，テンプレートマッチングの適用範囲を制限する．これにより，誤検出の発生を抑制でき，テンプレートマッチングの検出閾値を下げ，これまで未検出であった道路標示の数を削減できる．また，テンプレートマッチングの探索領域も制限され，処理速度も向上できる．実験の結果，提案手法は誤検出数は0のまま，従来手法よりも未検出数を低減できた．また，従来手法と比較してシステムのAccuracyは0.013，処理速度は4.6 FPS上がった．</p>

DOI： 10.3156/jsoft.33.1_566

Kyutacar

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007986500

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

Constructing a large food dataset is time and effort consuming due to the need to cover the feature variations of food items. Hence, a huge data is needed for training neural networks. This paper aims to advocate the Cycle-GAN to build up large food dataset based on large number of simulated images and relatively few real captured images thus obtaining more realistic images effortlessly compared with traditional capturing. Real RGB and depth images of variant food samples allocated over turntable were captured in three different angles using real-sense depth camera with different backgrounds. Furthermore, for simulated images, the Autodesk 3D_Maya software was employed using the same parameters of captured real images. Results showed that generally, realistic style transfer on simulated food objects was obtained as a result of employing Cycle-GAN. GAN proved to be an efficient tool that could minimize imaging efforts resulting in realistic images.

DOI： 10.5954/icarob.2021.os19-4

CiNii Research

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

Constructing a food dataset is time and effort consuming due to the requirement for covering the feature variations of food samples. Additionally, a large dataset is needed for training neural networks. Generative adversarial networks (GANs) are a recently developed technique to learn deep representations without extensively annotated training data. They can be used in several applications, including generating food datasets. This paper advocates the use of Cycle-GAN to generate a large pseudo-realistic food dataset based on a large number of simulated images and a small number of real images in comparison to traditional techniques. A single depth camera in three different angles and a turntable are arranged to capture real RGB-D images of food samples. 3D modeling software is used to generate simulated images using the same configuration of captured real images. Results showed that Cycle-GAN realistic style transfer on simulated food objects is achievable, and that it can be an efficient tool to minimize real image capturing efforts.

DOI： 10.57417/jaalr.2.3_128

CiNii Research

記述言語：英語   掲載種別：研究論文（学術雑誌）

A sulfonated polyaniline (SPAN) organic electrochemical network device (OEND) is fabricated using a simple drop-casting method on multiple Au electrodes for use in reservoir computing (RC). The SPAN network has humidity-dependent electrical properties. Under high humidity, the SPAN OEND exhibits mainly ionic conduction, including charging of an electric double layer and ionic diffusion. The nonlinearity and hysteresis of the current–voltage characteristics progressively increase with increasing humidity. The rich dynamic output behavior indicates wide variations for each electrode, which improves the RC performance because of the disordered network. For RC, waveform generation and short-term memory tasks are realized by a linear combination of outputs. The waveform task accuracy and memory capacity calculated from a short-term memory task reach 90% and 33.9, respectively. Improved spoken-digit classification is realized with 60% accuracy by only 12 outputs, demonstrating that the SPAN OEND can manage time series dynamic data operation in RC owing to a combination of rich dynamic and nonlinear electronic properties. The results suggest that SPAN-based electrochemical systems can be applied for material-based computing, by exploiting their intrinsic physicochemical behavior.

DOI： 10.1002/adma.202102688

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

This paper introduces our autonomous driving system equipped with recognition processing units from a camera image for hazard object / human-doll detection and drive lane detection. In particular, this paper focuses on a dataset generation method for neural networks and a generation tool 'FPGA Oriented Easy Synthesizer Tool (FOrEST)' for ROS2-FPGA nodes. The results show that mAP of a neural network trained by the generated dataset is 94%, and a overhead of ROS2-FPGA communication by the FOrEST is 2-3 ms.

DOI： 10.1109/ICFPT52863.2021.9609880

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In our work, a new area-efficient multiply-accumulation scheme for time-domain neural processing named differential multiply-accumulation is proposed. Our new scheme reduces hardware resources utilization of multiply-accumulation with suppressing the increasing computational time resulting from the time-multiplexing. As a result, 2,048 neurons of fully connected CBM and RC-CBM were synthesized for a single field-programmable gate array (FPGA).

DOI： 10.1109/ICFPT52863.2021.9609809

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We explain about how the difference of implementation methods written in C++ in High-Level Synthesis (HLS) influences on latency for tiny You only look once (YOLO) v2, a real-time object detection system to infer on an FPGA. To utilize features of FPGA, we need to implement hardware-oriented algorithms such as the weight binalization. We primarily focus on convolution in tiny YOLO v2 network and we report execution results on the Xilinx SDSoC development environment to know whether methods are appropriate or not.

DOI： 10.5954/ICAROB.2021.OS19-2

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Constructing a large food dataset is time and effort consuming due to the need to cover the feature variations of food items. Hence, a huge data is needed for training neural networks. This paper aims to advocate the Cycle-GAN to build up large food dataset based on large number of simulated images and relatively few real captured images thus obtaining more realistic images effortlessly compared with traditional capturing. Real RGB and depth images of variant food samples allocated over turntable were captured in three different angles using real-sense depth camera with different backgrounds. Furthermore, for simulated images, the Autodesk 3D_Maya software was employed using the same parameters of captured real images. Results showed that generally, realistic style transfer on simulated food objects was obtained as a result of employing Cycle-GAN. GAN proved to be an efficient tool that could minimize imaging efforts resulting in realistic images.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85108817301&origin=inward

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In the field of neuroscience, reservoir computing (RC) has been viewed as a model of the neuron computational system. RC is a framework for constructing recurrent neural networks, which is used for modeling the parts of the brain to solve the temporal problem. We construct the network inside the reservoir using the Pulse-Coupled Phase Oscillator (PCPO) with neighbor topology connections on field-programmable-gate-array (FPGA). Winfree model is used for PCPO spiking-based. We investigate the stability of the edge phenomenon using the zero one test (Z1-Test) methodology. We evaluate the proposed model on the time series generation tasks. We have successfully implemented and verified using FPGA that the 3x3 and 10x10 PCPO working as a Reservoir on the network.

DOI： 10.1109/ISCAS51556.2021.9401215

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In this study, we propose a hardware-oriented Gaussian mixture model - multiresolution co-occurrence histograms of oriented gradients (GMM-MRCoHOG) algorithm for efficient human detection by a field-programmable gate array (FPGA). GMM-MRCoHOG is a HOG-based human detection method in which the computation of angles is quantized to 36 directions and 2D Gaussian distribution computation causes a decrease in processing speed and an increase in hardware resource usage. We propose a hardware-oriented algorithm to solve these problems. First, we propose a rough angle computation method of comparison with a tangent table. Second, we propose a bit-shifting-based Gaussian distribution computation method. Experimental results show that the proposed hardware-oriented algorithm does not significantly reduce the detection accuracy of GMM-MRCoHOG. High-level synthesis results of the FPGA implementation show that fast, low-resource processing is possible.

DOI： 10.1117/12.2591024

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Deep learning technology has made remarkable progress in recent years and has been applied to a variety of applications such as smartphones and cloud servers. These systems employ dedicated processors to save power consumptions and process massive data. In this paper, we introduce a hardware-oriented restricted Boltzmann machine and propose a field-programmable gate array (FPGA) infrastructure for easy verification of user circuits. The infrastructure makes it easy to communicate and control between the host PC and the user circuit.

DOI： 10.5954/ICAROB.2021.OS19-3

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We propose a convolutional network with sub-networks (CNSN), a convolutional neural network (CNN) that can be detached into sub-models on fly. Due to a conventional design of CNN, shapes of feature map are varied throughout the model. Therefore, the hidden layer within CNN may not directly process the input image without any modifications. To address this problem, we propose a step-down convolutional layer, a convolutional layer which acts as an input layer for the sub-model. The step-down convolutional layer reshapes the input image to a preferred representation to the sub-model. To train CNSN, we treat the base-model and sub-models as different models. We separately forward-and back-propagate each model. By using multi-model loss, a linear combination of losses from base-and sub-models, we can update weights that can be utilized in both base-and sub-models.

DOI： 10.5954/ICAROB.2021.OS19-1

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

DOI： 10.1109/ACCESS.2020.3047619

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1007/978-981-15-8269-1_6

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2020, Springer Nature Switzerland AG. Reservoir computing (RC) has been viewed as a model of a neurological system. The RC framework constructs a recurrent neural network, which mimics parts of the brain, to solve temporal problems. To construct a neural network inside a reservoir, we adopt the pulse-coupled phase oscillator (PCPO) with neighbor topology connections on a field-programmable gate array (FPGA). Neural spikes for the PCPO are generated by the Winfree model. The low resource consumption of the proposed model in time-series generation tasks was confirmed in an evaluation study. We also demonstrate that on the FPGA, we can expand a 3 &#x0024;&#x0024;\times &#x0024;&#x0024; 3 PCPO into a 10 &#x0024;&#x0024;\times &#x0024;&#x0024; 10 PCPO, generate spike behavior, and predict the target signal with a maximum frequency of 418.796 MHz.

DOI： 10.1007/978-3-030-63823-8_39

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

This study develops an intelligent system for home service robots mimicking human brain function that can manage common knowledge applicable to any environment and local knowledge reflecting its specific environment. Deep learning is effective for acquiring common knowledge because the performance of deep learning relies on the amounts of training and big training data that can be accessed for such knowledge; however, deep learning is ineffective for acquiring local knowledge because no big training data for such knowledge exist. Thus, we propose a brain-inspired learning model and system for acquiring local knowledge using small training data. We focus on the amygdala because its classical fear conditioning is effective for training using small training data. We propose an amygdala-inspired classical conditioning model comprising multiple self-organizing maps (lateral nucleus) and a fully connected neural network (central nucleus), imitating the function and structure of the amygdala. The proposed model is applied to a task of a waiter robot in a restaurant, and the model can learn customers' preferences after only a few human-robot interactions. We accelerate the computation of the model and reduce its power consumption by proposing a hardware-oriented algorithm for the model and its digital hardware design and implement it in an XCZU9EG field programmable gate array. The hardware-oriented algorithm reduces the multiplication operations and exponential functions requiring huge hardware resources. The performance of the hardware operated at 150 MHz is 1,273 times faster than the software implementation on Arm Cortex-A53, and the power consumption of the chip is 5.009 W.

DOI： 10.1109/ACCESS.2020.3038161

Kyutacar

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

We propose a brain-inspired artificial intelligence model that acquires local knowledge from a small number of human-robot interactions, and uses this knowledge for future prediction. We focus on areas of the brain: the hippocampus, the amygdala, and the prefrontal cortex, thereby providing an internal representation of place and time, a value judgment, and a prediction. By integrating these functions, our model achieves local knowledge acquisition and future prediction. The proposed model is evaluated in a task for home service robots. In the experiment, the model learns local time-series events from a small number of interactions, and predicts the future events.

DOI： 10.34385/proc.74.a4l-c-4

CiNii Research

記述言語：英語   掲載種別：研究論文（学術雑誌）

We proposed reservoir models using chaotic Boltzmann machines (CBMs) based on pseudo-billiard dynamics in hypercube. In order to utilize CBMs as a reservoir, we must control the chaotic behavior and satisfy the echo state property. We added an external reference clock signal to control the CBM. In this paper, we demonstrate the effect of an external reference clock signal and show that our model works as a reservoir by using NARMA task.

DOI： 10.34385/proc.74.a4l-c-1

CiNii Research

記述言語：英語   掲載種別：研究論文（学術雑誌）

Reservoir computing (RC) is a framework that constructs recurrent neural networks that can be utilized for generation, prediction, and discrimination of complex time-series. The recurrent connection on the RC is sparse and fixed, and thus, the computational cost of learning is small. The pseudo-billiard dynamics in a hypercube is known to be applicable for various types of computation. This hypercube based computing is very efficient for hardware implementation. In this research, we implement the hypercube based RC model in a digital circuit with hardware-oriented algorithms and verify its performance and effectiveness as a new artificial intelligence platform.

DOI： 10.34385/proc.74.b4l-b-4

CiNii Research

記述言語：英語   掲載種別：研究論文（学術雑誌）

We propose a robot navigation system using reinforcement learning and reservoir computing. Reservoir computing is a framework for the processing of complex time series based on a recurrent neural network (RNN). The proposed system is trained by reinforcement learning, which is a framework that performs trial and error based on the rewards given by the environment. The trained network generates motor commands reflecting on action values obtained by the reinforcement learning and operates the autonomous mobile robot.

DOI： 10.34385/proc.74.b3l-b-5

CiNii Research

記述言語：英語   掲載種別：研究論文（学術雑誌）

Reservoir computing (RC) has received increasing attention as a computational framework for recurrent neural networks. As an implementation of reservoir, using a chaotic Boltzmann machine (CBM) was proposed, and we prototyped a CMOS CBM LSI chip controlled by an external reference clock (CBM-crc LSI) for working as a reservoir. We have developed a system using a System-on-Chip Field programmable gate array (SoC FPGA). In this paper, we propose a reservoir system that consists of a CBM-crc LSI controlled by an SoC FPGA and show the results of the system operations.

DOI： 10.34385/proc.74.a4l-c-3

CiNii Research

記述言語：英語   掲載種別：研究論文（学術雑誌）

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

DOI： 10.1109/ACCESS.2020.3036882

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1109/ISCAS45731.2020.9180685

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Service robots require an object recognition system to ensure their effective functioning in situations where Convolutional Neural Networks (CNN) are the mainstream machine learning technique employed by the system. Particularly, “Dual Stream VGG-16 (DS-VGG16),” which uses RGB and depth images, has been reported to have high accuracy for object recognition. However, it is difficult to implement CNN in robots, because it requires high computation power and consumes a huge amount of power. Although, implementing CNN with Field Programmable Gate Array (FPGA) solves the electric power problem, however it is difficult due to limited resources available. This paper proposes “Binarized Dual Stream VGG-16 (BDSVGG16),” which is Hardware-Oriented DS-VGG16. With the concept of Binarized Neural Networks (BNN), BDS-VGG16 is effective when implemented on FPGA. In results, the accuracy of BDS-VGG16 is 99.2%. It is higher than that of Eitel's model by 5.1 points. Further, we developed an object recognition system based on the Robot Operating System (ROS) which is a well-known middleware for robots, it uses our proposed method for service robot application.

DOI： 10.1109/ISCAS45731.2020.9180921

Scopus

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記述言語：日本語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

DOI： 10.3156/jsoft.32.3_54

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jsoft/32/3/32_54/_pdf

記述言語：英語   掲載種別：研究論文（学術雑誌）

© 2020, © 2020 Informa UK Limited, trading as Taylor & Francis Group and The Robotics Society of Japan. We present a method for implementing hardware intelligent processing accelerator on domestic service robots. These domestic service robots support human life; therefore, they are required to recognize environments using intelligent processing. Moreover, the intelligent processing requires large computational resources. Therefore, standard personal computers (PCs) with robot middleware on the robots do not have enough resources for this intelligent processing. We propose a ‘connective object for middleware to an accelerator (COMTA),’ which is a system that integrates hardware intelligent processing accelerators and robot middleware. Herein, by constructing dedicated architecture digital circuits, field-programmable gate arrays (FPGAs) accelerate intelligent processing. In addition, the system can configure and access applications on hardware accelerators via a robot middleware space; consequently, robotic engineers do not require the knowledge of FPGAs. We conducted an experiment on the proposed system by utilizing a human-following application with image processing, which is commonly applied in the robots. Experimental results demonstrated that the proposed system can be automatically constructed from a single-configuration file on the robot middleware and can execute the application 5.2 times more efficiently than an ordinary PC.

DOI： 10.1080/01691864.2020.1769726

Kyutacar

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

© 2020 The Authors. Published by Atlantis Press SARL. This is an open access article distributed under the CC BY-NC 4.0 license (http://creativecommons.org/licenses/by-nc/4.0/). This paper proposes implementation of an Echo State Network (ESN) to Field Programmable Gate Array (FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200 MHz of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit.

DOI： 10.2991/jrnal.k.200512.012

Kyutacar

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

© 2020 The Authors. Published by Atlantis Press SARL. This is an open access article distributed under the CC BY-NC 4.0 license (http://creativecommons.org/licenses/by-nc/4.0/). Autoencoders (AEs) have been applied in several applications such as anomaly detectors and object recognition systems. However, although the recent neural networks have relatively high accuracy but sometimes false detection may occur. This paper introduces AE as an anomaly detector. The proposed AE is trained using both normal and anomalous data based on convolutional neural network with three different color models Hue Saturation Value (HSV), Red Green Blue (RGB), and our own model (TUV). As a result, the trained AE reconstruct the normal images without change, whereas the anomalous image would be reconstructed reversely. The training and testing of the AE in case of RGB, HSV, and TUV color models were demonstrated and Cifar-10 dataset had been used for the evaluation process. It can be noticed that HSV color model has been more effective and achievable as an anomaly detector rather than other color models based on Z- and F-test analyses.

DOI： 10.2991/jrnal.k.200512.008

Kyutacar

Scopus

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記述言語：日本語   掲載種別：研究論文（学術雑誌）

DOI： 10.11517/jjsai.35.2_155

CiNii Article

CiNii Research

その他リンク： http://id.ndl.go.jp/bib/030297626

記述言語：日本語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

This paper proposes a method for the semi-automatic generation of a dataset for deep neural networks to perform end-to-end object detection and classification from images, which is expected to be applied to domestic service robots. In the proposed method, the background image of the floor or furniture is first captured. Subsequently, objects are captured from various viewpoints. Then, the background image and the object images are composited by the system (software) to generate images of the virtual scenes expected to be encountered by the robot. At this point, the annotation files, which will be used as teaching signals by the deep neural network, are automatically generated, as the region and category of the object composited with the background image are known. This reduces the human workload for dataset generation. Experiment results showed that the proposed method reduced the time taken to generate a data unit from 167 s, when performed manually, to 0.58 s, i.e., by a factor of approximately 1/287. The dataset generated using the proposed method was used to train a deep neural network, which was then applied to a domestic service robot for evaluation. The robot was entered into the World Robot Challenge, in which, out of ten trials, it succeeded in touching the target object eight times and grasping it four times.

DOI： 10.20965/jrm.2020.p0245

Kyutacar

Scopus

CiNii Article

CiNii Research

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Japan   Oita  

A semi-automatic dataset generation system is effective to prepare a training dataset for object recognition in a personal residence. However, a semi-automatic that method requires significant manual processing to capture images of household objects. Therefore, we apply three-dimensional object scanning to eliminate manual processing and speedup dataset generation. Experimental results demonstrate that the proposed method can generate the dataset 40 minutes faster than a comparable previous method that did not require manual processing.

DOI： 10.5954/ICAROB.2020.OS20-4

Scopus

CiNii Research

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Japan   Oita  

This paper proposes implementation of an echo state network (ESN) to field programmable gate array FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200[MHz] of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit.

DOI： 10.5954/ICAROB.2020.OS20-1

Scopus

CiNii Research

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記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>レザバー計算(RC)はリカレントニューラルネットワーク(RNN)の枠組みの1つで，時系列データの処理を目的に応用されている．機械学習モデルに対して，ディジタル回路実装を行うことで高速な演算速度を省電力で実現することが期待できる．香取らはディジタル回路との親和性が高いレザバー計算モデルを提案した．しかし，香取らのモデルをField Programmable Gate Array(FPGA)のようなディジタル回路に実装する場合，ニューロン数の変更に大きな制限が発生する．小規模な回路実装を行う手法として川嶋らがカオスボルツマンマシンのディジタル回路実装に用いたハードウェア指向アルゴリズムを提案している．本研究では川嶋らの提案したハードウェア指向アルゴリズムを基に対象のレザバー計算モデルを改良することで，ディジタル回路実装における回路リソースの消費を軽減可能なモデルを構築した．また，本研究のハードウェア指向アルゴリズムにより、レザバー計算の高速化の実現、人工知能構築のための新しいプラットフォームの確立が期待される．</p>

DOI： 10.11517/pjsai.jsai2020.0_3rin422

CiNii Article

CiNii Research

記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p> </p>

DOI： 10.14864/fss.36.0_149

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007957941

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

We introduce network with sub-networks, a neural network which it’s weight layers can be detached into sub-neural networks during inference phase. To develop trainable parameters which can be inserted into both base-and sub-models, firstly, the parameters of sub-models are duplicated to base-model. Each model is forward-propagated separately. All models are grouped into pairs. Gradients from selected pairs of networks are averaged and updated both networks. With MNIST dataset, our base-model achieves the identical test-accuracy to the regularly trained models. In other hand, the sub-models are suffered an extend of loss in test-accuracy, nevertheless the sub-models provide alternative approaches to be deployed with less parameters compare to the regular model.

DOI： 10.5954/ICAROB.2020.OS20-2

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Autoencoders (AEs) have been applied in several applications such as anomaly detectors and object recognition systems. However, although the recent neural networks have relatively high accuracy but sometimes false detection may occur. This paper introduces AE as an anomaly detector. The proposed AE is trained using both normal and anomalous data based on convolutional neural network (CNN) with three different color models HSV, RGB and TUV (own model). As a result, the trained AE reconstruct the normal images without change, whereas the anomalous image would be reconstructed reversely. The training and testing of the autoencoder in case of RGB, HSV, and TUV color models were demonstrated and Cifar-10 dataset had been used for the evaluation process. It can be noticed that HSV color model has been more effective and achievable as an anomaly detector rather than other color models based on Z-test and F-test analyses.

DOI： 10.5954/ICAROB.2020.OS20-5

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Home service robots have begun attracting attention due to decreasing birthrate and increasing aging population. The basic functions of home service robots are object recognition, picking and placing, recognition of people and environment, and interaction with peoples. In this paper, we focus on object picking and placing in the domestic environment. The pick-and-place task is a very important technique used for arrangement shelves and tidying up rooms. In order for the robot to operate smoothly, the movement to pick-and-place the object must be fast. Therefore, we develop a fast pick-and-place method using 3D point clouds. Regarding the picking, we describe a grasping-point estimation method. Regarding the placing, we describe a placeable position estimation method. These methods are used at RoboCup@Home, an international competition aimed at the practical application of home service robots, and their effectiveness and validity are verified.

DOI： 10.5954/ICAROB.2020.OS20-3

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Australia   Sydney  

This study proposes High-Speed Synchronization of Pulse-Coupled Phase Oscillators on multiple field-programmable-gate-array (FPGA). Winfree model is used for oscillators communication based and two FPGAs are connected by a gigabit transceiver (GTX). In order to verify the effect of communication delay and in-phase synchronization phenomenon between FPGAs, we implement various number of oscillators on the multi-FPGA platform. Four-oscillator network achieved first spike synchronization over two FPGAs within 12.47 (formula presented)s and datastream bitrate up tp 3.2 Gbps. We have successfully expanded the network from the previous study and verified that the 10 (formula presented) 10 pulse-coupled phase oscillators synchronized over two FPGAs via high-speed serial communication with a 0.1 (formula presented)s delay and the network reached a steady synchronization state after the spike-count reached 100 with a maximum frequency 298.014 MHz.

DOI： 10.1007/978-3-030-36802-9_34

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Autoencoders (AEs) are used in several applications, including dimension reducers and anomaly detectors. This paper introduces AEs as anomaly detectors. The proposed AEs are trained using both normal and anomalous data in a novel training manner. As a result, the trained AEs reconstruct normal input regularly and anomalous input irregularly, respectively. Consequently, reconstruction errors by anomalous input become increase and it is easy to detect as anomalous input. We implement anomaly detectors with the proposed AEs, and applying it to the MNIST and CIFAR10 datasets.

DOI： 10.1109/ISPACS.2018.8923117

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Malaysia   Kuala Lumpur  

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Thailand   Pattaya  

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Thailand   Pattaya  

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In this presentation, we report the results of applying a binarized Convolutional Neural Network (CNN) and a Field Programmable Gate Array (FPGA) for image-based object recognition. While the demand rises for robots with robust object recognition implemented with Neural Networks, a tradeoff between data processing rate and power consumption persists. Some applications utilise Graphics Processing Units (GPU), which results in high power consumption, thus undesirable for embedded systems, while the others communicate with cloud computers to minimise computational resources at the clients' side, i.e. robots, raising another concern that the robots are unable to perform object recognition without the servers and network connections. To overcome these difficulties, we propose an embedded object recognition system implemented with a binarized CNN and an FPGA. FPGAs consist of a matrix of reconfigurable logic gates allowing parallel computing which befit most image processing algorithms such as the CNN. We train the binarized CNN on one of our datasets that contain images of several kinds of food and beverages. The results of the experiments show that the binarized CNN with an FPGA maintains high accuracy as well as real-time computation, suggesting that the proposed system is suitable for robots to perform their tasks in a real-world environment without needing to communicate with a server.

DOI： 10.1109/ICSyS47076.2019.8982469

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Japan   Tokyo  

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Hungary   Budapest  

Reservoir computing is attracting great interest because of its high computing ability especially for time-series prediction, despite its simple structure and learning scheme. This paper proposes a reservoir computing hardware model using a chaotic Boltzmann machine (CBM) as the reservoir, which can achieve complex motion in a dynamical system on a high-dimensional hypercube. The CBM uses analog nonlinear dynamics, unlike the stochastic operation of the original Boltzmann machine model. To utilize CBMs as a reservoir, chaotic operation must be suppressed, and the echo state property should be satisfied. We modify the CBM model for simpler analog complementary metal-oxide-semiconductor very-large-scale integration (CMOS VLSI) implementation, and propose its use as a reservoir by adding an external reference clock signal. We then verify its proper operation by numerical simulation. We also refine the CMOS VLSI circuit design based on the proposed modified CBM model to improve power consumption and calculation precision.

DOI： 10.1109/IJCNN.2019.8852325

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Hungary   Budapest  

Reservoir computing (RC) is a framework for constructing recurrent neural networks with simple training rule and sparsely and randomly connected nonlinear units. The network (called reservoir) generates complex motion that can be used for many tasks including time series generation and prediction. We construct a reservoir based on the dynamics of the pseudo-billiard system that produce complex motion in a high-dimensional hypercube. In particular, we use the chaotic Boltzmann machine (CBM) whose units exhibit chaotic behavior in the hypercube. The units interact with each other in a time-domain manner through its binary state, and thus an efficient hardware implementation of the system is expected. In order to utilize the CBM as the reservoir, it is necessary to control its chaotic behavior for ensuring the echo state property of RC and establish encoding and decoding for input and output signal. For this purpose, we introduce a reference clock and analyze effects and properties of the reference input. We evaluate the proposed model on the time series generation tasks and show that the model works properly on a broad range of parameter values. Our approach presents a novel mechanism for time-domain information processing and a fundamental technology for a brain like artificial intelligence system.

DOI： 10.1109/IJCNN.2019.8852329

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Singapore  

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE Deep neural networks (DNNs) have achieved state-of-the-art results in several computing tasks. However, the performance of these DNNs is reliant on the availability of large amounts of training data, which is not always present. We approached this problem by developing a brain-inspired amygdala model to achieve computer learning based on limited training data. The amygdala is an area of the brain associated with classical fear conditioning. The proposed amygdala model is composed of a single layer of deep self-organizing map network (deep SOM network) and a fully-connected neural network (FCNN), which imitates the function and structure of an amygdala. We applied the proposed amygdala model to a robot waiter task in a restaurant. The experimental results show that the model learned a customer's preferences after only a few human robot interactions. To develop the digital hardware of the amygdala model, we designed hardware for the deep SOM network and the FCNN and implemented them in an XCZU9EG field programmable gate array (FPGA). Our FPGA implementation of a deep SOM network with 272 neurons and an FCNN with three output neurons outperformed a software implementation on an Intel Core i5-3470 CPU by over 600 times.

DOI： 10.1109/ISCAS.2019.8702430

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© COPYRIGHT SPIE. In this paper, we propose a land-cover classification method based on a modified hierarchical k-nearest neighbor (MHkNN) algorithm to achieve a high classification accuracy. The proposed method introduces a reliability measure for each training sample, which is defined as confidence in the sample belonging to each of the considered classes. The method performs the majority voting considering not only the number of the training samples, but also their reliabilities. The classification performance of the proposed method is compared to that of the conventional land-cover classification methods. The effectiveness of the proposed method is verified by applying it to real remote sensing images.

DOI： 10.1117/12.2521356

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© COPYRIGHT SPIE. In this paper, we propose a new color quantization method that can preserve infrequent salient colors of an original image. The infrequent salient colors mean that they are not dominant globally, but are dominant locally and are important to keep the impression of the original image. In the proposed method, color quantization is realized by k-means clustering and an input dataset for the clustering are adaptively and repeatedly modified based on local quantization errors to preserve the infrequent salient colors. The proposed method is implemented as an Android application to verify the feasibility of the use of the proposed method on mobile devices.

DOI： 10.1117/12.2521607

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2019 SPIE. In this study, we designed a digital hardware circuit for a field-programmable gate array (FPGA) to provide an effective contrast improvement algorithm for dichromats. The proposed method employs the Craik-O 'Brien (C-O) effect. The C-O effect is an optical illusion effect in which subjective contrast is created from contour information. In the proposed method, the contrast modification is only conducted around the contours of objects to apply the C-O effect for dichromats. To extract the contour information of objects, a T-model filter which only requires a one-line buffer is introduced. The proposed method can realize the C-O effect without using dividers and multipliers. Therefore, it is relatively simple to implement in the FPGA. Through experiments with software and logic simulation, the effectiveness and validity of the proposed method were evaluated.

DOI： 10.1117/12.2521580

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE This live demonstration presents a VLSI chip based on “Time-domain Analog Computing with Transient states (TACT)” approach for intelligent processing on robots. This TACT chip, fabricated using 250-nm CMOS technology, implements a time-domain analog weighted-sum calculation model with very high energy efficiency. We integrate the TACT chip into a robot via Robot Operating System (ROS) interfaces. A human tracking robot demonstration is performed by the TACT chip with energy efficiency of 300 TOPS/W.

DOI： 10.1109/ISCAS.2019.8702222

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE This live demonstration presents a brain-inspired amygdala model. Amygdala is an area of the brain that is associated with fear conditioning, which is a type of classical conditioning. The model can learn preferences through human-robot interactions by application of classical conditioning to the model. Additionally, to develop a high speed and low power system, we design a hardware of the amygdala model, and implemented the hardware into field programmable gate array.

DOI： 10.1109/ISCAS.2019.8702213

Scopus

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担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>In recent years, automated driving and AGVs are actively researched and developed. The important technique is Simultaneous Localization and Mapping (SLAM) which creates maps and self-location estimation at simultaneously. There are several kinds of SLAM depending on the sensor and algorithm used, ORB-SLAM uses only monocular camera. Since it is cheaper than other sensors, it is easy to board it into AGV etc. However, the calculation amount is large. Although high performance PCs is required, it is not able to board it into AGV etc., so we focused on FPGA. The FPGA development environment is also actively developed, and the development with high-level synthesis has become realistic. Therefore, in this research, in order to improve FPGA development efficiency, we implemented ORB-SLAM from open source software to FPGA.</p>

DOI： 10.1299/jsmermd.2019.1a1-f06

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jsmermd/2019/0/2019_1A1-F06/_pdf

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p> </p>

DOI： 10.14864/fss.35.0_715

CiNii Article

CiNii Research

その他リンク： http://id.ndl.go.jp/bib/029976312

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p> </p>

DOI： 10.14864/fss.35.0_722

CiNii Article

CiNii Research

その他リンク： http://id.ndl.go.jp/bib/029976316

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>Home service robots have begun attracting attention due to decreasing birthrate and increasing aging population. We,“Hibikino-Musashi@Home”team, develop home service robots, and participate international competitions; RoboCup@Home and World Robot Challenge (WRC), which are established to realize that robots will work and live with people in domestic environments. In this paper, we introduce our robots and technologies, especially an object recognition and manipulation system. We use You Only Look Once (YOLO) for object recognition. To train YOLO, a big dataset which is difficult to prepare in a short term is required. For this, we develop an automatic annotation system for YOLO which can generate 1.7 million training data, and we can complete training of YOLO in a day. To grasp objects, estimation of object orientations is required. Our system can detect the orientations by processing point clouds of objects. By using the system, we obtained about 30% of scores in Tidy Up Task in the WRC.</p>

DOI： 10.1299/jsmermd.2019.1p2-i02

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jsmermd/2019/0/2019_1P2-I02/_pdf

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Kyutacar

記述言語：日本語   掲載種別：記事・総説・解説・論説等（その他）

DOI： 10.1587/transfun.E101.A.1735

Scopus

CiNii Article

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In an aging society with fewer children, service robots are expected to play an increasingly important role in people's lives. To realize a future with service robots, a generic object recognition system is necessary to recognize a wide variety of objects with a high degree of accuracy. Therefore, this study employs deep convolutional neural networks for the generic object recognition system. To improve the accuracy of object recognition, both RGB images and depth images can be used effectively. In this paper, we propose a new architecture 'Dual Stream - VGG16 (DS-VGG16)' for a deep convolutional neural network to train both the RGB images and depth images, and we also present a new training method for the proposed architecture. The experimental results indicate that the proposed architecture and training method are effective. Finally, we develop an object recognition system based on the proposed method that has an interface of robot operating system for integrating the system into service robots.

DOI： 10.1109/ISPACS.2018.8923533

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

© 2018 The Author(s). In contrast to AI hardware, neuromorphic hardware is based on neuroscience, wherein constructing both spiking neurons and their dense and complex networks is essential to obtain intelligent abilities. However, the integration density of present neuromorphic devices is much less than that of human brains. In this report, we present molecular neuromorphic devices, composed of a dynamic and extremely dense network of single-walled carbon nanotubes (SWNTs) complexed with polyoxometalate (POM). We show experimentally that the SWNT/POM network generates spontaneous spikes and noise. We propose electron-cascading models of the network consisting of heterogeneous molecular junctions that yields results in good agreement with the experimental results. Rudimentary learning ability of the network is illustrated by introducing reservoir computing, which utilises spiking dynamics and a certain degree of network complexity. These results indicate the possibility that complex functional networks can be constructed using molecular devices, and contribute to the development of neuromorphic devices.

DOI： 10.1038/s41467-018-04886-2

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Italy   Florence   2018年05月27日  -  2018年05月30日

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Italy   Florence   2018年05月27日  -  2018年05月30日

Kyutacar

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>Danger forecast and its avoidance are highly important for the design of automated driving system and the function is expected to be solved by artificial intelligences (AIs). However the reasoning process is unclear in the conventional scheme such as machine learning and as deep neural network models. In this paper, we focus on the ability of the logical reasoning based on the Semantic Web techniques, which is called knowledge-based AI, and demonstrate successfully its implementation into a module of Robot Operating System (ROS) to control a real vehicle. The processing speed of proposed system is evaluated using the real vehicle in the situation of the pedestrian avoidance in the crossroad.</p>

DOI： 10.5687/iscie.31.191

CiNii Article

CiNii Research

その他リンク： http://hdl.handle.net/10228/00008368

記述言語：日本語   掲載種別：研究論文（学術雑誌）

Kyutacar

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. This live demonstration presents a 'connective object for middleware to accelerator (COMTA),' an intelligent processing system that uses hardware accelerators (i.e., field programmable gate arrays (FPGAs)) and robot middleware. The key idea of COMTA is to automatically generate the system via robot middleware interfaces. To realize the proposed system, we have developed a block of programs called an 'object' in a hardware/software complex system. We demonstrate an implementation of a human tracking image processing application on a vehicle robot accelerated by COMTA. The demonstration system achieved 3.3 times better power efficiency than a general PCs.

DOI： 10.1109/ISCAS.2018.8351837

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. Service robots require implementation of intelligent processing, e.g., image processing. However, the computational resources of standard PCs typically used in service robots are not sufficient for such processes. Furthermore, robot middleware is widely used in many robots because such systems facilitate integration and are suitable for rapid prototyping. We propose a 'connective object for middleware to accelerator (COMTA),' which is a processing system that uses hardware accelerators, i.e., field programmable gate arrays (FPGAs), and robot middleware. Users can access the FPGAs in the proposed system via middleware interfaces; thus, complex internal circuits are not required. For human tracking using image processing, the proposed system can automatically generate from a single configuration file. The proposed system performs 3.3 times more efficiently relative to computation than standard PCs in robots.

DOI： 10.1109/ISCAS.2018.8351722

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

Kyutacar

記述言語：英語   掲載種別：研究論文（学術雑誌）

Copyright: © 2018 Suzuki et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers’ units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

DOI： 10.1371/journal.pone.0194049

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2018, Springer Nature Switzerland AG. We propose Mixed Precision Weight Networks (MPWNs), neural networks that jointly utilize weights with varied precision in the layers. MPWNs constrain the weight layers to either 1-bit binary {-1,1}, 2-bit ternary {-1,0,1}, or the original 32-bit full precision weights. Each weight space contains unique properties for instance, high classification accuracy, small number of bit, and high sparsity. Hence, the properties of MPWNs can be adjusted by varying the combinations and orders of the weight layers. In this study, we identify three heuristic rules for effectively setting each of the weight layers. Therefore, MPWNs successfully utilize the robust properties from each weight space while avoiding their disadvantages. We evaluated MPWNs with MNIST, CIFAR-10, and CIFAR-100 training datasets. Our evaluation revealed that MPWNs models trained on CIFAR-10 and CIFAR-100 achieved the best overall properties comparing to conventional methods.

DOI： 10.1007/978-3-030-04179-3_54

Scopus

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担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>自動運転は，人工知能（AI）によってコンピュータ上で実行される． 事故が発生した場合，自動運転システムは事故の原因を分析するために意思決定の根拠を示すべきである． 本報告では，意思決定の根拠を示す知識ベースAIの統合シミュレータを提案する． シミュレータを構築するには，Autoware，Gazebo，知識ベースAIを組み合わせる． Autowareは自動運転用のオープンソースソフトウェアであり，Gazeboは任意の道路環境をシミュレートすることができる．提案シミュレータを用いて，自動運転のための知識ベースAIの実用性を何度も検証することができる．実験結果は，提案されたシミュレータが意思決定の根拠の提示に成功していることを示している．</p>

DOI： 10.14864/fss.34.0_450

CiNii Article

CiNii Research

その他リンク： http://id.ndl.go.jp/bib/029269004

記述言語：英語   掲載種別：研究論文（学術雑誌）

<p>We propose a coupled-map-lattice complementary-metal-oxide-semiconductor very-large-scale-integration (CMOS VLSI) circuit based on the threshold-coupled map (TCM) that has been proposed previously as a unidirectional connected network model exhibiting different spatiotemporal patterns according to its underlying nonlinear map and update scheme. We introduce mutual connections and arbitrarily valued connection weights into the TCM to realize cellular automata. In this study, we design, fabricate, and evaluate a CMOS integrated circuit with which to implement this extended TCM (ETCM). The ETCM is a universal Turing machine as confirmed in circuit experiments using the fabricated circuit, which can achieve Rule110 of a one-dimensional cellular automaton.</p>

DOI： 10.1587/nolta.9.268

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/nolta/9/2/9_268/_pdf

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>In recent years, robots has come to have useful, but high load functions, e.g. navigating automotive movement, image recognition by deep learning. Usually, these functions are executed by high-spec CPU or GPUs. However, in practical use these devices cannot be implemented into robot, because of the size or power consumption. So in this research we implemented image filter function on FPGA included in AP SoC as a sample of high load function. And we have also implemented RT-Middleware and some RT-Components as a sample robot system which includes a component handling FPGA on CPU included in AP SoC. We show the effectiveness of the collaboration with FPGA and RT-Middleware to develop robot system.</p>

DOI： 10.1299/jsmermd.2018.2a1-g10

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jsmermd/2018/0/2018_2A1-G10/_pdf

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>Service robots must assemble and execute its own action based on user’s voice instructions. Additionally, in order to assist human daily life, the service robots execute not a single action like an industrial robot but plurality of actions must be combined according to the situation. As the number of actions the robots can perform increases, phrase of the voice instructions increases to an enormous pattern. Therefore, the robots must understand the instructions by natural language processing. In this paper, we focus on general purpose service robot (GPSR) task of RoboCup@Home, which is a competition for performance of the service robots, and identify behavior of the robots from natural language by using word vectorization and machine learning.</p>

DOI： 10.1299/jsmermd.2018.2p1-b18

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jsmermd/2018/0/2018_2P1-B18/_pdf

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p>In real world applications of home service robots, they are required to be able to perform housekeeping or other tasks. “RoboCup@Home” is a competition for benchmarking home service robots. It includes tests to service robots for real world implementation. These tests require the combination of intelligent functions such as object detection and voice recognition. We have developed a home service robot “Exi@” and evaluated its performance by participating in RoboCup@Home. This paper describes real world implementation of robots and RoboCup@Home. The functions embedded in Exi@ and a task “Restaurant” are also explained.</p>

DOI： 10.1299/jsmermd.2018.2p2-e02

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jsmermd/2018/0/2018_2P2-E02/_pdf

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Japan   Dazaifu   2017年09月06日  -  2017年09月08日

記述言語：日本語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2017 IEEE. This paper proposes CMOS VLSI implementation of a chaotic Boltzmann machine (CBM) model, which uses analog nonlinear dynamics instead of stochastic operation as in the original Boltzmann machine model. The CBM model is suitable for efficient VLSI implementation of Boltzmann machines because it requires no random number generator circuits, which consume a considerable footprint on a VLSI chip as well as considerable power. We describe the design results of CMOS circuits of neuron and synapse units. The neuron circuit uses subthreshold operation of MOSFETs to realize the exponential function used in the CBM model. We also provide measurement results of a fabricated CMOS chip for single-neuron unit circuit operation and demonstrate chaotic behavior in a three-neuron network.

DOI： 10.1109/IJCNN.2017.7965991

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

Kyutacar

担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

This paper proposes an implementation of multi-Field Programmable Gate Array (FPGA) communication using pulse-coupled phase oscillators. At first, we construct a digital phase oscillator circuit with adjustable in-phase parameters. While performing the synchronization task, the oscillators are connected into the first input and first output (FIFO) interface. The communication in-between of FPGAs will occur by enabling the following inputs and outputs on the FIFO through the Gigabit Transceiver (GTX) clock domain. Pulse-coupled phase oscillators of Winfree's model are utilized as a spike generator and we expect the ideal of model circuit will synchronize. We employ two FPGA boards of Virtex6 ML605 and implement four oscillators on a hardware level. Experimental results show that first spike synchronizing over two FPGAs takes 12.47 μsec with data bit speed stream 3.2Gbps.

DOI： 10.5954/icarob.2017.os9-1

CiNii Research

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2017. We aim to develop a recognition system of high accuracy and low power consumption by designing a digital circuit for deep neural networks (DNNs), and by implementing the circuit on field programmable gate arrays (FPGAs). DNNs include numerous multiply operations, whereas FPGAs include a limited number of multipliers. We aim to reduce the number of multiply operations generated by the algorithms within DNNs. Deep self-organizing map networks (DSNs) [1] are DNNs comprising self-organizing maps (SOMs) [2] as shown in Fig. 1. A hardware-oriented algorithm for SOMs has been proposed herein [3]. The algorithm represents SOMs by replacing multiply operations with bitshift operations. DSNs that include only a few multiply operations can then be represented by employing the algorithm. In this paper, we propose a hardware-oriented algorithm and a hardware architecture for DSNs. The hardware-oriented algorithm reduces multiply operations and exponential functions in a computation of SOM Module as shown in Fig. 1. In addition, we confirm that the algorithm does not worsen performance of DSN by a software simulation. Figure 2 shows error rates of DSN during learning MNIST Dataset [4]. The performance of the proposed algorithm achieve comparable results to the conventional algorithm. We also describe a DSN comprising three layers by Verilog-HDL as shown in Fig. 1, and implement it on a Xilinx Vertex-6 XC6VLX240T FPGA. Experimental results showed that the proposed DSN circuit estimates a label of an input image in 2 µs while the software implemented using an Intel Core i5-3470 (3.20 GHz) CPU estimates it in about 1 ms. Thus the hardware is 500 times faster than the software. Its logic utilization is shown in Table 1.

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2017. This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

DOI： 10.1007/978-3-319-70136-3_87

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2017. We implement a digital spiking silicon neuron (DSSN) [1] in a single instruction multiple data (SIMD) processor. The SIMD processor is a scalable, reconfigurable, and real-time spiking neural network emulator based on field programmable gate arrays [2]. We implement the DSSN model in the SIMD processor for the first time. The behavior of the membrane potential of one neuron based on the DSSN model is shown in Fig. 1. The operation results of the SIMD processor with 16-bit fixed-point operation are compared with software simulation results based on 64-bit floating-point operation. From the results, it is concluded that the SIMD processor successfully emulated the behavior of the membrane potential. In addition, a full-connection network consisting of 100 neurons is simulated in a software using fixed-point binary numbers to evaluate the bit width for the SIMD processor. In this experiment, the network stores two patterns selected from [1]. In the recall phase, the first pattern with noise is given to this network to recall the pattern. Experimental results show that the network with 16-bit fixed-point numbers, each of which includes a 12-bit fraction, a 3-bit integer, and a 1-bit sign, successfully recalled the input pattern as shown in Fig. 2. Here, Muis a recall rate [1]. From this result, a large DSSN network simulation on the SIMD processor is promising.

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Copyright © 2017 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved. Human detection require high speed and high accuracy processing. One of the high performance techniques of the detection is multi-resolution co-occurrence histogram of oriented gradients (MRCoHOG). Since the calculation of co-occurrence requires a huge amount of processing resources, it is difficult to realize real-time human detection with MRCoHOG. Accordingly, hardware implementation is considered to be effective. In this paper, a hardware oriented MRCoHOG is proposed. In the proposed method, we simplify complicated calculation such as multiplications and square root operation for efficient hardware implementation. Experimental results show that the proposed method achieves better human detection rate than the ordinary method. Moreover, MRCoHOG is implemented in a digital circuit with the proposed method. According to logic simulation of the proposed circuit, the processing speed of the hardware implementation is 466 times higher than the software implementation.

Scopus

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記述言語：日本語   掲載種別：研究論文（学術雑誌）

The Joint Graduate School Intelligent Car and Robotics Course, called “Car-Robo Joint Graduate School” is an educational program that started in 2012 mainly at The Kitakyushu Science and Research Park (KSRP). Graduate schools of engineering in Kyushu Institute of Technology, the University of Kitakyushu, and Waseda University at KSRP participate in this program. The purpose of this program is to foster highly skilled personnel in technical fields on intelligent car and robot technology. They will gain practical ability as leaders, mastering their special fields, understanding the peripheral technologies, and leading research and development teams. The special-feature program of this course is seven comprehensive practicums as team learning. Internship students of national colleges of technology and other universities as well as master and PhD course students of these graduate schools participate in the practicums.

DOI： 10.4307/jsee.65.4_51

CiNii Article

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jsee/65/4/65_4_51/_pdf

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p> </p>

DOI： 10.14864/fss.33.0_681

CiNii Article

CiNii Research

その他リンク： http://id.ndl.go.jp/bib/029133349

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© 2016 IEEE. This paper proposes a visual-servoing method dedicated to grasping of daily-life objects. In order to obtain an affordable solution, we use a low-accurate robotic arm. Our method corrects errors by using an RGB-D sensor. It is based on SURF invariant features which allows us to perform object recognition at a high frame rate. We define regions of interest based on depth segmentation, and we use them to speed-up the recognition and to improve reliability. The system has been tested on a real-world scenario. In spite of the lack of accuracy of all the components and the uncontrolled environment, it grasps objects successfully on more than 95% of the trials.

DOI： 10.1109/SCIS-ISIS.2016.0116

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記述言語：英語   掲載種別：研究論文（学術雑誌）

Copyright © 2016 The Institute of Electronics, Information and Communication Engineers. Protanopes and deuteranopes are difficult to distinguish some color pairs. In this letter, a new lightness modification method which considers the Craik-O'Brien effect is proposed. The lightness modification is performed at parts which are difficult to distinguish in the protanopia or deuteranopia. Experiments show the validity of the proposed method.

DOI： 10.1587/transfun.E99.A.2008

Scopus

CiNii Article

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：日本語   掲載種別：研究論文（学術雑誌）

DOI： 10.11470/jsapmeeting.2016.1.0_2286

CiNii Research

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2016. Time-domain weighted-sum operation based on a spiking neuron model is discussed and evaluated from a VLSI implementation point of view. This calculation model is useful for extremely low-power operation because transition states in resistance and capacitance (RC) circuits can be used. Weighted summation is achieved with energy dissipation on the order of 1 fJ using the current CMOS VLSI technology if 1 GΩ order resistance can be used, where the number of inputs can be more than a hundred. This amount of energy is several orders of magnitude lower than that in conventional digital processors. In this paper, we show the software simulation results that verify the proposed calculation method for a 500-input neuron in a three-layer perceptron for digit character recognition.

DOI： 10.1007/978-3-319-46687-3_26

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2016. Boltzmann machines are a useful model for deep neural networks in artificial intelligence, but in their software or hardware implementation, they require random number generation for stochastic operation, which consumes considerable computational resources and power. Chaotic Boltzmann machines (CBMs) have been proposed as a model using chaotic dynamics instead of stochastic operation. They require no random number generation, and are suitable for analog VLSI implementation. In this paper, we describe software simulation results for CBM operation, and propose a CMOS circuit of CBMs using the subthreshold operation of MOSFETs.

DOI： 10.1007/978-3-319-46687-3_27

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2016. Deep neural networks (DNNs) are a state-of-the-art processing model in the field of machine learning. Implementation of DNNs into embedded systems is required to realize artificial intelligence on robots and automobiles. Embedded systems demand great processing speed and low power consumption, and DNNs require considerable processing resources. A field-programmable gate array (FPGA) is one of the most suitable devices for embedded systems because of their low power consumption, high speed processing, and reconfigurability. Autoencoders (AEs) are key parts of DNNs and comprise an input, a hidden, and an output layer. In this paper, we propose a novel hardware implementation of AEs having shared synapse architecture. In the proposed architecture, the value of each weight is shared in two interlayers between input-hidden layer and hidden-output layer. This architecture saves the limited resources of an FPGA, allowing a reduction of the synapse modules by half. Experimental results show that the proposed design can reconstruct input data and be stacked. Compared with the related works, the proposed design is register transfer level description, synthesizable, and estimated to decrease total processing time.

DOI： 10.1007/978-3-319-46687-3_25

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing Switzerland 2016. Restricted Boltzmann machines (RBMs) have actively been studied in the field of deep neural networks. RBMs are stochastic artificial neural networks that can learn a probability distribution of input datasets. However, they require considerable computational resources, long processing times and high power consumption due to huge number of random number generation to obtain stochastic behavior. Therefore, dedicated hardware implementation of RBMs is desired for consumer applications with low-power devices. To realize hardware implementation of RBMs in a massively parallel manner, each unit must include random number generators (RNGs), which occupy huge hardware resources. In this paper, we propose a hardware-oriented RBM algorithm that does not require RNGs. In the proposed method, as a random number, we employ underflow bits obtained from the calculation process of the firing probability. We have developed a software implementation of fixed-point RBMs to evaluate the proposed method. Experimental results show that a 16-bit fixed-point RBM can be trained by the proposed method, and the underflow bits can be used as random numbers in RBM training.

DOI： 10.1007/978-3-319-44778-0_46

Scopus

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担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p> </p>

DOI： 10.14864/fss.32.0_49

CiNii Article

CiNii Research

担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

<p> </p>

DOI： 10.14864/fss.32.0_53

CiNii Article

CiNii Research

その他リンク： http://id.ndl.go.jp/bib/027632005

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

United States of America   New York City  

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

China   Hong Kong  

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

NewZealand   Auckland  

In this paper, we propose a new color quantization method for generation of the color-reduced images. The proposed method employs a vector error diffusion (VED) method and a particle swarm optimization (PSO). VED method based on Floyd-Steinberg dithering is used for display of the color-reduced image. Furthermore, a color palette used in VED method is optimized by PSO. PSO generates the effective color palette with evaluating a human visibility of the color-reduced image on the display. The validity and the effectiveness of the proposed method are confirmed by some experiments.

DOI： 10.1007/978-3-319-29451-3_27

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Indonesia   Bali  

Dichromats is difficult to distinguish some color pairs. There is lightness modification method which considers the Craik-O'Brien effect. Although the method can obtain good results in many cases, there is a room for improvement. In this paper, a new lightness modification method which considers the Craik-O'Brien effect is proposed. In the proposed method, the lightness modification is mainly performed at parts which are difficult to distinguish for dichromats. The validity of the proposed method is shown by experiments using some images.

DOI： 10.1109/ISPACS.2015.7432741

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Japan   Sapporo  

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

DOI： 10.1016/j.neucom.2014.07.084

Scopus

記述言語：英語   掲載種別：研究論文（学術雑誌）

DOI： 10.1587/transinf.2014EDP7219

Scopus

CiNii Article

記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

In order to develop large-scale nonlinear dynamical systems using CMOS integrated circuits, we propose a core circuit for coupled map lattice (CML) models. The characteristics of the core circuits in the lattice on a chip are not generally equal, which is caused by CMOS device mismatches, including parasitic capacitance and wiring resistance. The proposed circuit solves this problem; it compensates for a DC offset voltage variation by holding it at a capacitor, and also for current variation by adjusting the bias voltage of a current source automatically so as to bring the current close to a target value. The proposed core circuit has been designed and fabricated using TSMC 0.25 µm CMOS technology. The measurement results using the fabricated circuit have shown that the bit precision is more than 8 bits, even if there is a DC offset voltage of 100 mV or a bias-voltage change of 100 mV in a switched current source.

DOI： 10.1587/nolta.6.570

CiNii Article

その他リンク： http://ci.nii.ac.jp/naid/130005102329

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing Switzerland 2014. The morphological associative memory (MAM) has advantages of large memory capacity and high perfect recall rate in comparison with other associative memory models. However, the MAM cannot store a large data in memory matrices M and W because the space complexity of the ordinary method is O(n 2 ) when the dimension of input data is n. In this paperCwe propose a MAM employing a split store method. The proposed method splits a given stored pattern into √n sub-pattern, then memory matrices are independently generated for each sub-pattern. Experimental results show that the perfect recall rate and CPU time of the proposed method are nearly equal to the ordinary method while the proposed method reduces the space complexity to O(n 1.5 ).

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）

Particle swarm optimization (PSO), which is included in swarm intelligence, is a population-based stochastic optimization technique. The motivation of the PSO is based on social behavior of fish schooling or bird flocking. The PSO is attractive due to the simplicity of its concept and the facility for the applications to diverse optimization problems. However, the traditional PSO cannot work in high dimensional searching space effectively. In this paper, we propose a new PSO considering a combined component, which is obtained from the personal best positions of the particles in the searching space. The present PSO first calculates a center of the personal best positions weighted by their fitness values, and uses it for the update of the particle position. The effectiveness and the validity of the proposed PSO are verified by applying it to some benchmarks of the continuous variable optimization problems. © 2014 ICIC International.

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a fuzzy-rule-embedded reduction image construction method for image enlargement. A fuzzy rule is generated by considering distribution of pixel value around a target pixel. The generated rule is embedded into the target pixel in a reduction image. The embedded fuzzy rule is used in a fuzzy inference to generate a highly magnified image from the reduction image. Experimental results, which scale factors are three and four, show that the proposed method realizes high-quality image enlargement in terms of both objective and subjective evaluations in comparison with conventional methods. Copyright © 2014 SCITEPRESS - Science and Technology Publications. All rights reserved.

Scopus

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担当区分：責任著者   記述言語：日本語   掲載種別：記事・総説・解説・論説等（その他）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1109/IECON.2013.6699481

Scopus

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1007/978-3-642-42051-1_3

Scopus

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

High-quality image enlargement is achieved by the augmentation of the high-frequency components that deteriorate as a result of image enlargement. A codebook-based method, which utilizes the relationship of the low- and high-frequency image components, is a proven method of high-quality image enlargement. However, this method requires a significant calculation time to be employed for a codebook search process, and thus is not suitable for real-time processing. In this paper, we propose a fast image-enlargement algorithm that includes a hierarchical predefined codebook and a fast edge-patch detection rule. A hierarchical codebook search reduces the number of comparisons that need to be made in comparison with a conventional full codebook search. In addition, applying the augmentation of the high-frequency components to only the edge patches detected under the proposed rule reduces the calculation time. The experimental results show that the calculation time of the proposed method is around 180 times faster than that of the fastest existing codebook-based method. The proposed method realizes high-quality image enlargement in terms of both objective and subjective evaluations in comparison with conventional methods. © 2013 ICIC International.

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：日本語   掲載種別：記事・総説・解説・論説等（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

Indonesia   Jakarta   2012年10月24日  -  2012年10月25日

DOI： 10.1016/j.proeng.2012.10.030

Scopus

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

This live demonstration presents an Internet Booster (IB) which is a novel WEB application platform accelerated by virtual hardware circuits. Akey-idea of IB is obtaining relevant WEB applications virtual hardware circuit through the Internet. The downloaded virtual hardware circuit is dynamically reconfigured into an FPGA and cooperates with software and network to accelerate WEB application. In order to realize the concept of IB, we develop a hwModule VC FPGA Cardbus board and a networked hw/sw complex system to access virtual hardware circiuts via the Internet. Furthermore, we also develop a virtual hardware video codec and a TCP/IP hardware stack to construct a demonstration system. In the live demonstration, we show a WEB streaming application accelerated by IB on the local area network environment. The demonstration system achieves full-color VGA size (24 bits RGB, 640 × 480 pixels) video streaming with around 20 frames per second. © 2012 IEEE.

DOI： 10.1109/ISCAS.2012.6272135

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84866605736&origin=inward

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1109/ICNC.2012.6234717

Scopus

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

In this paper, we propose a hardware oriented vector quantization algorithm employing rough-winner-take-all neural network. The proposed algorithm is almost same as K-means clustering which is the simplest vector quantization. The only different point is that the proposed method employs rough-winner-take-all as the substitute of ordinary winner-take-all. In a rough-winner-take-all strategy, the winner is roughly selected in the early learning stage and is strictly assigned in the later stage. The simulation results show that the quantization performance of the proposed method is nearly equal to Neural Gas which is an excellent vector quantization. Besides, the proposed method can be realized as an extra mode of existing K-means or Self- Organizing Map hardware by changing its winner-take-all controlling. © IEICE 2011.

DOI： 10.1587/elex.8.773

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

An internet booster (IB) based on a networked hw/sw complex system is presented. The key-idea of IB is obtaining relevant WEB applications virtual hardware circuit through internet; just as same as downloading general WEB applications specific software from the server. The downloaded virtual hardware circuit is realized into an FPGA and cooperates with server's application which is also constructed with FPGA. In order to realize IB, the networked hw/sw complex system is proposed which provides remote FPGA reconfiguration and handshake mechanism between FPGAs over the internet. In this paper, we implement WEB application as IB; where the WEB application performs real time compression, transferring and extension of video. Experimental results show that we succeed in downloading virtual hardware circuit, dynamic reconfiguration and remote operation over the internet. Besides, we also achieved full-color VGA size (24bits RGB, 640x480 pixels) video streaming with 20 frames per second using a wavelet transfer based virtual video codec. The result leads that the proposed networked hw/sw complex system and IB can provide a new WEB application program environment which features both the hispeed of hardware and the flexibility of software. © 2010 TSI Press.

Scopus

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1007/978-3-642-17534-3_54

Scopus

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

DOI： 10.1109/PSIVT.2010.56

Scopus

記述言語：英語   掲載種別：研究論文（学術雑誌）

DOI： 10.1007/s10043-010-0082-8

Scopus

担当区分：責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

CiNii Article

記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：日本語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：日本語   掲載種別：記事・総説・解説・論説等（商業誌、新聞、ウェブメディア）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

記述言語：英語   掲載種別：研究論文（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

開催期間： 2022年09月20日 - 2022年09月23日   記述言語：日本語  

開催期間： 2022年09月05日 - 2022年09月09日   記述言語：日本語  

開催期間： 2022年08月31日 - 2022年09月03日   記述言語：日本語  

開催期間： 2022年06月09日 - 2022年06月10日   記述言語：日本語  

開催期間： 2022年06月09日 - 2022年06月10日   記述言語：日本語  

開催期間： 2022年03月24日   記述言語：日本語  

開催期間： 2022年03月22日 - 2022年03月26日   記述言語：日本語  

開催期間： 2022年03月22日 - 2022年03月26日   記述言語：日本語  

開催期間： 2022年03月22日 - 2022年03月26日   記述言語：日本語  

開催期間： 2022年02月18日 - 2022年02月19日   記述言語：日本語  

開催期間： 2022年02月18日 - 2022年02月19日   記述言語：日本語  

開催期間： 2022年02月18日 - 2022年02月19日   記述言語：日本語  

開催期間： 2021年12月05日 - 2021年12月08日   記述言語：英語  

開催期間： 2021年12月05日 - 2021年12月08日   記述言語：英語  

開催期間： 2021年12月05日 - 2021年12月08日   記述言語：英語  

開催期間： 2021年12月05日 - 2021年12月08日   記述言語：英語  

開催期間： 2021年12月05日 - 2021年12月08日   記述言語：英語  

開催期間： 2021年12月05日 - 2021年12月08日   記述言語：英語  

開催期間： 2021年12月05日 - 2021年12月08日   記述言語：英語  

開催期間： 2021年12月03日   記述言語：日本語  

開催期間： 2021年10月07日 - 2021年10月08日   記述言語：日本語  

開催期間： 2021年09月23日   記述言語：日本語  

開催期間： 2021年09月23日   記述言語：日本語  

開催期間： 2021年09月10日 - 2021年09月13日   記述言語：日本語  

開催期間： 2021年09月08日 - 2021年09月11日   記述言語：日本語  

開催期間： 2021年03月04日 - 2021年03月05日   記述言語：日本語  

開催期間： 2020年12月25日 - 2020年12月27日   記述言語：日本語   開催地：福岡市科学館  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月12日 - 2020年12月19日   記述言語：英語   開催地：Online  

開催期間： 2020年12月01日   記述言語：日本語   開催地：オンライン開催  

開催期間： 2020年10月09日 - 2020年10月11日   記述言語：日本語   開催地：オンライン開催  

開催期間： 2020年10月09日 - 2020年10月11日   記述言語：日本語   開催地：オンライン開催  

開催期間： 2020年10月09日 - 2020年10月11日   記述言語：日本語   開催地：オンライン開催  

開催期間： 2020年10月01日 - 2020年10月02日   記述言語：日本語   開催地：オンライン開催  

開催期間： 2020年06月03日 - 2020年06月04日   記述言語：日本語   開催地：オンライン開催  

開催期間： 2020年05月13日 - 2020年05月14日   記述言語：日本語   開催地：東京, 東京大学  

開催期間： 2020年03月05日 - 2020年03月06日   記述言語：日本語   開催地：オンライン開催  

開催期間： 2020年03月03日 - 2020年03月05日   記述言語：日本語  

開催期間： 2019年12月18日 - 2019年12月19日   記述言語：日本語   開催地：東京, 日本大学  

開催期間： 2019年12月12日 - 2019年12月19日   記述言語：日本語   開催地：香川，サンポート高松  

開催期間： 2019年11月11日 - 2019年11月12日   記述言語：英語   開催地：Malaysia  

開催期間： 2019年11月11日 - 2019年11月12日   記述言語：英語   開催地：Malaysia  

開催期間： 2019年11月11日 - 2019年11月12日   記述言語：英語   開催地：Malaysia  

開催期間： 2019年11月11日 - 2019年11月12日   記述言語：英語   開催地：Malaysia  

開催期間： 2019年09月04日 - 2019年09月06日   記述言語：日本語   開催地：東京，東京工業大学  

開催期間： 2019年09月03日 - 2019年09月07日   記述言語：日本語   開催地：東京，早稲田大学早稲田キャンパス  

開催期間： 2019年09月03日 - 2019年09月07日   記述言語：日本語   開催地：東京，早稲田大学早稲田キャンパス  

開催期間： 2019年09月03日 - 2019年09月07日   記述言語：日本語   開催地：東京，早稲田大学早稲田キャンパス  

開催期間： 2019年08月29日 - 2019年08月31日   記述言語：日本語   開催地：大阪，大阪大学  

開催期間： 2019年08月29日 - 2019年08月31日   記述言語：日本語   開催地：大阪，大阪大学  

開催期間： 2019年08月27日   記述言語：日本語   開催地：大手町サンケイプラザ