Affiliation
Faculty of Computer Science and Systems Engineering Department of Computer Science and Networks
Job
Associate Professor
External link
HOLST Stefan
Scopus Paper Info
Total Paper Count: 0 Total Citation Count: 0 h-index: 8
Research Interests
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Logic Diagnosis
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Logic Simulation
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VLSI Testing
Undergraduate Education
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2005.11 University of Stuttgart Computer Science, Electrical Engineering and Information Technology Computer Science Graduated Germany
Post Graduate Education
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2012.09 University of Stuttgart Institute of Computer Architecture and Computer Engineering Computer Engineering Doctoral Program Completed Germany
Degree
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University of Stuttgart - Doctor of Science 2012.09
Biography in Kyutech
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2021.04
Kyushu Institute of Technology Faculty of Computer Science and Systems Engineering Department of Computer Science and Networks Associate Professor
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2019.04-2021.03
Kyushu Institute of Technology Faculty of Computer Science and Systems Engineering Department of Computer Science and Networks Assistant Professor
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2013.04-2019.03
Kyushu Institute of Technology Faculty of Computer Science and Systems Engineering Department of Creative Informatics Assistant Professor
Academic Society Memberships
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2006.01 IEEE United States
Papers
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ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits Reviewed
Reimer J.D., Holst S., Sadeghi-Kohan S., Wunderlich H.J., Hellebrand S.
2025 International Symposium of Electronics Design Automation Iseda 2025 502 - 507 2025.01
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Motion Classification by Utilizing Machine Learning for Acceleration Data Reviewed
Ishizu K., Honda T., Miyase K., Holst S., Ishikawa S., Sengupta R., Polian I.
Digest of Technical Papers IEEE International Conference on Consumer Electronics 2025.01
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Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design Reviewed
Ma R., Holst S., Xu H., Wen X., Wang S., Li J., Yan A.
IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 2 ) 449 - 461 2025.01
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GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting Reviewed
SHI Shiling, HOLST Stefan, WEN Xiaoqing
IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E106.D ( 10 ) 1694 - 1704 2023.10
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Stock price movement prediction based on Stocktwits investor sentiment using FinBERT and ensemble SVM Reviewed International journal
Liu J.X., Leu J.S., Holst S.
PeerJ Computer Science 9 2023.01
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BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell Reviewed International journal
Holst S., Ma R., Wen X., Yan A., Xu H.
Proceedings of the European Test Workshop 2023-May 2023.01
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Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling Reviewed
Shi S., Holst S., Wen X.
Proceedings 2023 16th IEEE International Symposium on Embedded Multicore Many Core Systems on Chip Mcsoc 2023 501 - 507 2023.01
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Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm Reviewed
Lylina N., Holst S., Jafarzadeh H., Kourfali A., Wunderlich H.J.
Proceedings 53rd Annual IEEE IFIP International Conference on Dependable Systems and Networks Workshops Volume Dsn W 2023 195 - 198 2023.01
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Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization Reviewed
Lylina N., Holst S., Jafarzadeh H., Kourfali A., Wunderlich H.J.
Proceedings 2023 IEEE 29th International Symposium on on Line Testing and Robust System Design Iolts 2023 2023.01
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On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks Reviewed International journal
Neugebauer F., Holst S., Polian I.
Proceedings of the European Test Workshop 2022-May 2022.01
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Evaluation and Test of Production Defects in Hardened Latches Reviewed International journal
MA Ruijun, HOLST Stefan, WEN Xiaoqing, YAN Aibin, XU Hui
IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E105D ( 5 ) 996 - 1009 2022.01
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Power and Energy Safe Real-Time Multi-Core Task Scheduling Reviewed
Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.
Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 16 - 21 2022.01
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On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption Reviewed International journal
Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.
IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E104D ( 6 ) 816 - 827 2021.01
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GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators Reviewed International journal
Holst S., Bumun L., Wen X.
Proceedings of the Asian Test Symposium 2021-November 127 - 132 2021.01
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Logic Fault Diagnosis of Hidden Delay Defects Reviewed
Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.
Proceedings International Test Conference 2020-November 2020.11
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Targeted partial-shift for mitigating shift switching activity hot-spots during scan test Reviewed
Holst S., Shi S., Wen X.
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing Prdc 2019-December 124 - 129 2019.12
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Variation-aware small delay fault diagnosis on compressed test responses Reviewed
Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.
Proceedings International Test Conference 2019-November 2019.11
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A fault-tolerant MPSoC for CubeSats Reviewed
Fuchs C.M., Chou P., Wen X., Murillo N.M., Furano G., Holst S., Tavoularis A., Lu S.K., Plaat A., Marinis K.
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems Dft 2019 2019.10
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STAHL: A novel scan-test-aware hardened latch design Reviewed
Ma R., Holst S., Wen X., Yan A., Xu H.
Proceedings of the European Test Symposium 2019-May 2019.05
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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed International journal
Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.
Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018.12
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The impact of production defects on the soft-error tolerance of hardened latches Reviewed International journal
Holst S., Ma R., Wen X.
Proceedings of the European Test Workshop 2018-May 1 - 6 2018.06
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Scan chain grouping for mitigating ir-drop-induced test data corruption Reviewed International journal
Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.
Proceedings of the Asian Test Symposium Part F134421 140 - 145 2018.01
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Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors Reviewed International journal
Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
IEEE International Test Conference 2017-December 1 - 8 2017.10
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GPU-Accelerated Simulation of Small Delay Faults Reviewed International journal
Schneider E., Kochte M., Holst S., Wen X., Wunderlich H.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 ( 5 ) 829 - 841 2017.05
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Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test Reviewed International journal
Eggersglub S., Holst S., Tille D., Miyase K., Wen X.
Proceedings of the Asian Test Symposium 173 - 178 2016.12
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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed International journal
Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.
Proceedings of the Asian Test Symposium 19 - 24 2016.12
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Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Reviewed International journal
LI Fuqiang, WEN Xiaoqing, MIYASE Kohei, HOLST Stefan, KAJIHARA Seiji
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( The Institute of Electronics, Information and Communication Engineers ) E99A ( 12 ) 2310 - 2319 2016.12
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Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch Reviewed International journal
Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian
IEEE Asian Test Symposium 2016-February 103 - 108 2015.11
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High-Throughput Logic Timing Simulation on GPGPUs Reviewed International journal
S. Holst, M. E. Imhof, H.-J. Wunderlich
ACM Transactions on Design Automation of Electronic Systems 20 ( 3 ) Article No. 37 2015.06
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A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys Reviewed International journal
I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase
IEEE European Test Symposium 2015.05
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GPU-Accelerated Small Delay Fault Simulation Reviewed
E. Schneider, S. Holst, M. A. Kochte, X. Wen, H.-J. Wunderlich
Design and Test in Europe 1174 - 1179 2015.03
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GPU-accelerated small delay fault simulation Reviewed International journal
Schneider E., Holst S., Kochte M.A., Wen X., Wunderlich H.J.
Proceedings -Design, Automation and Test in Europe, DATE 2015-April 1174 - 1179 2015.01
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Soft-Error Tolerant TCAMs for High-Reliability Packet Classifications Reviewed International journal
I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase
IEEE Asia Pacific Conference on Circuits and Systems 2015-February ( February ) 471 - 474 2014.11
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Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal
E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich
International Conference on Computer-Aided Design 2015-January ( January ) 17 - 23 2014.11
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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed
Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
IEICE Transactions on Information and Systems E97-D ( 10 ) 2706 - 2718 2014.10
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Scan test power simulation on GPGPUs Reviewed
155 - 160 2012.12
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Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures Reviewed
207 - 212 2012.12
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Structural Test and Diagnosis for Graceful Degradation of NoC Switches Reviewed
28 ( 6 ) 831 - 841 2012.10
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Embedded test for highly accurate defect localization Reviewed
213 - 218 2011.12
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Structural test for graceful degradation of NoC switches Reviewed
183 - 188 2011.08
Conference Prsentations (Oral, Poster)
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Stochastic Computing based Neural Networks on Unreliable Hardware
FTC
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Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses
South European Test Seminar (SETS) 2020
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Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses
FTC
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Accelerated Timing Simulation and Its Application Invited
Dagstuhl Workshop "Intelligent Methods for Test and Reliability"
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Logic Fault Diagnosis of Hidden Delay Defects
FTC
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Small Delay Fault Diagnosis with Compacted Responses
Design Automation Conference 2019
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Small Delay Fault Diagnosis with Compacted Responses
South European Test Seminar (SETS) 2019
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Small Delay Fault Diagnosis on Compacted Responses
FTC
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Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits Invited
International Joint Workshop on Kyutech Research Centers
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Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits
DA Symposium 2018
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Logic Diagnosis - How to Find Unknown Defects Invited
Joint NTUST/Kyutech Seminar
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Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits
FTC
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Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors
South European Test Seminar (SETS) 2017
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The AR/VR Revolution and Its Implications for EDA Tools
FTC
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Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
South European Test Seminar (SETS) 2016
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On the Stability of Systems in Changing Environments
South European Test Seminar (SETS) 2015
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Big Data and Small Transistors High-Performance VLSI Simulation Invited
Joint NTUST/Kyutech Seminar
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Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
FTC
Honors and Awards
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Best Paper of Asian Test Symposium 2021
Program Committee of ATS 2021 2022.11
S. Holst, B. Lim, X. Wen
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Distinquished Paper of International Test Conference 2017
Program Committee of ITC 2017 2017.10
Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
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Best Paper of Asian Test Symposium 2015
Program Committee of ATS 2015 2016.11
K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, H. Furukawa
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Best Paper of European Test Symposium 2007
Program Committee of ETS 2007 2008.05
Stefan Holst, Hans-Joachim Wunderlich
Career of Research abroad
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Research Collaboration With Prof. Krishnendu Chakrabarty
Duke University, Durham, North Carolina Project Year: 2015.09 - 2015.11
Social activity outside the university
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Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize
Role(s)：Lecturer
Ehime University, Matsuyama 2019.08.02
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Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize
Role(s)：Lecturer
Ehime University, Matsuyama 2018.08.03
Citation count denotes the number of citations in papers published for a particular year.