Faculty Profiles - HOLST Stefan

HOLST Stefan

Scopus Paper Info

Total Paper Count: 0 Total Citation Count: 0 h-index: 8

Citation count denotes the number of citations in papers published for a particular year.

Affiliation

Faculty of Computer Science and Systems Engineering Department of Computer Science and Networks

Job

Associate Professor

External link

Research Interests

Logic Diagnosis
Logic Simulation
VLSI Testing

Undergraduate Education

2005.11 University of Stuttgart Computer Science, Electrical Engineering and Information Technology Computer Science Graduated Germany

Post Graduate Education

2012.09 University of Stuttgart Institute of Computer Architecture and Computer Engineering Computer Engineering Doctoral Program Completed Germany

Degree

University of Stuttgart - Doctor of Science 2012.09

Biography in Kyutech

2021.04

Kyushu Institute of Technology Faculty of Computer Science and Systems Engineering Department of Computer Science and Networks Associate Professor
2019.04

-

2021.03

Kyushu Institute of Technology Faculty of Computer Science and Systems Engineering Department of Computer Science and Networks Assistant Professor
2013.04

-

2019.03

Kyushu Institute of Technology Faculty of Computer Science and Systems Engineering Department of Creative Informatics Assistant Professor

Academic Society Memberships

2006.01 IEEE United States

Papers

Stock price movement prediction based on Stocktwits investor sentiment using FinBERT and ensemble SVM Reviewed International journal

Liu J.X., Leu J.S., Holst S.

PeerJ Computer Science 9 2023.01

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Authorship：Last author Language：English Publishing type：Research paper (scientific journal)

DOI： 10.7717/peerj-cs.1403

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BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell Reviewed International journal

Holst S., Ma R., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2023-May 2023.01

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Authorship：Lead author,　Corresponding author Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ETS56758.2023.10174154

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On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks Reviewed International journal

Neugebauer F., Holst S., Polian I.

Proceedings of the European Test Workshop 2022-May 2022.01

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ETS54262.2022.9810429

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Evaluation and Test of Production Defects in Hardened Latches Reviewed International journal

MA Ruijun, HOLST Stefan, WEN Xiaoqing, YAN Aibin, XU Hui

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E105D ( 5 ) 996 - 1009 2022.01

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As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (PTVF), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed PTVF metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.

DOI： 10.1587/transinf.2021EDP7216

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Power and Energy Safe Real-Time Multi-Core Task Scheduling Reviewed

Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 16 - 21 2022.01

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/VLSID2022.2022.00016

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On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption Reviewed International journal

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E104D ( 6 ) 816 - 827 2021.01

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Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

DOI： 10.1587/transinf.2020EDP7042

Scopus

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GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators Reviewed International journal

Holst S., Bumun L., Wen X.

Proceedings of the Asian Test Symposium 2021-November 127 - 132 2021.01

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Authorship：Lead author Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ATS52891.2021.00034

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Logic Fault Diagnosis of Hidden Delay Defects Reviewed

Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

Proceedings - International Test Conference 2020-November 2020.11

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Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

DOI： 10.1109/ITC44778.2020.9325234

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Targeted partial-shift for mitigating shift switching activity hot-spots during scan test Reviewed

Holst S., Shi S., Wen X.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2019-December 124 - 129 2019.12

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Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

DOI： 10.1109/PRDC47002.2019.00042

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Variation-aware small delay fault diagnosis on compressed test responses Reviewed

Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings - International Test Conference 2019-November 2019.11

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With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

DOI： 10.1109/ITC44170.2019.9000143

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A fault-tolerant MPSoC for CubeSats Reviewed

Fuchs C.M., Chou P., Wen X., Murillo N.M., Furano G., Holst S., Tavoularis A., Lu S.K., Plaat A., Marinis K.

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 2019.10

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We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

DOI： 10.1109/DFT.2019.8875417

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STAHL: A novel scan-test-aware hardened latch design Reviewed

Ma R., Holst S., Wen X., Yan A., Xu H.

Proceedings of the European Test Symposium 2019-May 2019.05

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Germany Baden-Baden

As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulner-ability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode.

DOI： 10.1109/ETS.2019.8791544

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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed International journal

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018.12

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ATS.2018.00037

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The impact of production defects on the soft-error tolerance of hardened latches Reviewed International journal

Holst S., Ma R., Wen X.

Proceedings of the European Test Workshop 2018-May 1 - 6 2018.06

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Authorship：Lead author Language：English Publishing type：Research paper (international conference proceedings)

Germany Bremen

DOI： 10.1109/ETS.2018.8400694

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Scan chain grouping for mitigating ir-drop-induced test data corruption Reviewed International journal

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

Proceedings of the Asian Test Symposium Part F134421 140 - 145 2018.01

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ATS.2017.37

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Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors Reviewed International journal

Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

IEEE International Test Conference 2017-December 1 - 8 2017.10

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Authorship：Lead author,　Corresponding author Language：English Publishing type：Research paper (international conference proceedings)

United States Fort Worth 2017.10.31 - 2017.11.02

DOI： 10.1109/TEST.2017.8242055

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GPU-Accelerated Simulation of Small Delay Faults Reviewed International journal

Schneider E., Kochte M., Holst S., Wen X., Wunderlich H.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 ( 5 ) 829 - 841 2017.05

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Language：English Publishing type：Research paper (scientific journal)

DOI： 10.1109/TCAD.2016.2598560

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Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test Reviewed International journal

Eggersglub S., Holst S., Tille D., Miyase K., Wen X.

Proceedings of the Asian Test Symposium 173 - 178 2016.12

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ATS.2016.41

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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed International journal

Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.

Proceedings of the Asian Test Symposium 19 - 24 2016.12

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Authorship：Lead author Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ATS.2016.49

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Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Reviewed International journal

LI Fuqiang, WEN Xiaoqing, MIYASE Kohei, HOLST Stefan, KAJIHARA Seiji

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( The Institute of Electronics, Information and Communication Engineers ) E99A ( 12 ) 2310 - 2319 2016.12

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Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power-safety without significant test vector count inflation and test quality loss.

DOI： 10.1587/transfun.E99.A.2310

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Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch Reviewed International journal

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

IEEE Asian Test Symposium 2016-February 103 - 108 2015.11

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India Mumbai 2015.11.22 - 2015.11.25

DOI： 10.1109/ATS.2015.25

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High-Throughput Logic Timing Simulation on GPGPUs Reviewed International journal

S. Holst, M. E. Imhof, H.-J. Wunderlich

ACM Transactions on Design Automation of Electronic Systems 20 ( 3 ) Article No. 37 2015.06

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Authorship：Lead author,　Corresponding author Language：English Publishing type：Research paper (scientific journal)

DOI： 10.1145/2714564

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A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys Reviewed International journal

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE European Test Symposium 2015.05

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Language：English Publishing type：Research paper (international conference proceedings)

Romania Cluj-Napoca 2015.05.25 - 2015.05.29

DOI： 10.1109/ETS.2015.7138743

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GPU-Accelerated Small Delay Fault Simulation Reviewed

E. Schneider, S. Holst, M. A. Kochte, X. Wen, H.-J. Wunderlich

Design and Test in Europe 1174 - 1179 2015.03

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France Grenoble 2015.03.09 - 2015.03.13
GPU-accelerated small delay fault simulation Reviewed International journal

Schneider E., Holst S., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings -Design, Automation and Test in Europe, DATE 2015-April 1174 - 1179 2015.01

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.7873/date.2015.0077

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Soft-Error Tolerant TCAMs for High-Reliability Packet Classifications Reviewed International journal

I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase

IEEE Asia Pacific Conference on Circuits and Systems 2015-February ( February ) 471 - 474 2014.11

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Language：English Publishing type：Research paper (international conference proceedings)

Japan Ishigaki 2014.11.17 - 2014.11.20

DOI： 10.1109/APCCAS.2014.7032821

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Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal

E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

International Conference on Computer-Aided Design 2015-January ( January ) 17 - 23 2014.11

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Language：English Publishing type：Research paper (international conference proceedings)

USA San Jose 2014.11.03 - 2014.11.06

DOI： 10.1109/ICCAD.2014.7001324

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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

IEICE Transactions on Information and Systems E97-D ( 10 ) 2706 - 2718 2014.10

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Language：English Publishing type：Research paper (scientific journal)

DOI： 10.1587/transinf.2014EDP7039

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Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures Reviewed

207 - 212 2012.12

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ICCD.2012.6378642

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Scan test power simulation on GPGPUs Reviewed

155 - 160 2012.12

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ATS.2012.23

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Structural Test and Diagnosis for Graceful Degradation of NoC Switches Reviewed

28 ( 6 ) 831 - 841 2012.10

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Language：English Publishing type：Research paper (scientific journal)

DOI： 10.1007/s10836-012-5329-9

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Embedded test for highly accurate defect localization Reviewed

213 - 218 2011.12

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ATS.2011.60

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Structural test for graceful degradation of NoC switches Reviewed

183 - 188 2011.08

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Language：English Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/ETS.2011.33

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Conference Prsentations (Oral, Poster)

Stochastic Computing based Neural Networks on Unreliable Hardware

FTC

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Event date： 2021.07.16 Language：English
Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

South European Test Seminar (SETS) 2020

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Event date： 2020.03.03 - 2020.03.06 Language：English
Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

FTC

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Event date： 2020.01.23 - 2020.01.25 Language：English
Accelerated Timing Simulation and Its Application Invited

Dagstuhl Workshop "Intelligent Methods for Test and Reliability"

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Event date： 2019.09.11 - 2019.09.13 Language：English
Logic Fault Diagnosis of Hidden Delay Defects

FTC

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Event date： 2019.07.18 - 2019.07.20 Language：English
Small Delay Fault Diagnosis with Compacted Responses

Design Automation Conference 2019

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Event date： 2019.06.02 - 2019.06.06 Language：English
Small Delay Fault Diagnosis with Compacted Responses

South European Test Seminar (SETS) 2019

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Event date： 2019.03.11 - 2019.03.15 Language：English
Small Delay Fault Diagnosis on Compacted Responses

FTC

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Event date： 2019.01.24 - 2019.01.26 Language：English
Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits Invited

International Joint Workshop on Kyutech Research Centers

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Event date： 2018.11.06 - 2018.11.07 Language：English
Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits

DA Symposium 2018

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Event date： 2018.08.29 - 2018.08.30 Language：English
Logic Diagnosis - How to Find Unknown Defects Invited

Joint NTUST/Kyutech Seminar

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Event date： 2018.08.21 Language：English
Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits

FTC

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Event date： 2018.07.19 - 2018.07.21 Language：English
Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors

South European Test Seminar (SETS) 2017

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Event date： 2017.03.20 - 2017.03.24 Language：English
The AR/VR Revolution and Its Implications for EDA Tools

FTC

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Event date： 2017.01.19 - 2017.01.21 Language：English
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation

South European Test Seminar (SETS) 2016

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Event date： 2016.03.07 - 2016.03.11 Language：English
On the Stability of Systems in Changing Environments

South European Test Seminar (SETS) 2015

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Event date： 2015.03.16 - 2015.03.20 Language：English
Big Data and Small Transistors High-Performance VLSI Simulation Invited

Joint NTUST/Kyutech Seminar

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Event date： 2015.03.05 Language：English
Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits

FTC

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Event date： 2014.01.23 - 2014.01.24 Language：English

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Honors and Awards

Best Paper of Asian Test Symposium 2021

Program Committee of ATS 2021 2022.11

S. Holst, B. Lim, X. Wen

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Country：Japan
Distinquished Paper of International Test Conference 2017

Program Committee of ITC 2017 2017.10

Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

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Country：Japan
Best Paper of Asian Test Symposium 2015

Program Committee of ATS 2015 2016.11

K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, H. Furukawa

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Country：Japan
Best Paper of European Test Symposium 2007

Program Committee of ETS 2007 2008.05

Stefan Holst, Hans-Joachim Wunderlich

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Country：Germany

Career of Research abroad

Research Collaboration With Prof. Krishnendu Chakrabarty

Duke University, Durham, North Carolina Project Year: 2015.09 - 2015.11

Social activity outside the university

Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize

Role(s)：Lecturer

Ehime University, Matsuyama 2019.08.02

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Audience： College students

Type：Visiting lecture
Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize

Role(s)：Lecturer

Ehime University, Matsuyama 2018.08.03

　More details

Audience： College students

Type：Visiting lecture