HOLST Stefan



Associate Professor


680-4 Kawazu, Iizuka-shi, Fukuoka

Research Fields, Keywords

VLSI Testing, Logic Diagnosis, Logic Simulation



Special Affairs

Dr. rer. nat.

Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 7

Citation count denotes the number of citations in papers published for a particular year.

Undergraduate Education 【 display / non-display

  • 2005.11   University of Stuttgart   Computer Science, Electrical Engineering and Information Technology   Computer Science   Graduated   GERMANY

Post Graduate Education 【 display / non-display

  • 2012.09  University of Stuttgart   Institute of Computer Architecture and Computer Engineering  Computer Engineering  Doctoral Program  Completed  GERMANY

Degree 【 display / non-display

  • University of Stuttgart  -  Doctor of Science  2012.09

Biography in Kyutech 【 display / non-display

  • 2021.04

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Associate Professor  

  • 2019.04

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Assistant Professor  

  • 2013.04

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Creative Informatics   Assistant Professor  

Academic Society Memberships 【 display / non-display

  • 2006.01



Publications (Article) 【 display / non-display

  • On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    IEICE Transactions on Information and Systems    E104D ( 6 ) 816 - 827   2021.01  [Refereed]

     View Summary

    Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

    DOI Scopus CiNii

  • Logic Fault Diagnosis of Hidden Delay Defects

    Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

    Proceedings - International Test Conference    2020-November   2020.11  [Refereed]

     View Summary

    Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

    DOI Scopus

  • Targeted partial-shift for mitigating shift switching activity hot-spots during scan test

    Holst S., Shi S., Wen X.

    Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC    2019-December   124 - 129   2019.12  [Refereed]

     View Summary

    Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

    DOI Scopus

  • Variation-aware small delay fault diagnosis on compressed test responses

    Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

    Proceedings - International Test Conference    2019-November   2019.11  [Refereed]

     View Summary

    With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

    DOI Scopus

  • A fault-tolerant MPSoC for CubeSats

    Fuchs C.M., Chou P., Wen X., Murillo N.M., Furano G., Holst S., Tavoularis A., Lu S.K., Plaat A., Marinis K.

    2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019      2019.10  [Refereed]

     View Summary

    We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

    DOI Scopus

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Conference Prsentations (Oral, Poster) 【 display / non-display

  • Stochastic Computing based Neural Networks on Unreliable Hardware

    FTC  2021.07  -  2021.07 

  • Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

    South European Test Seminar (SETS) 2020  2020.03  -  2020.03 

  • Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

    FTC  2020.01  -  2020.01 

  • Accelerated Timing Simulation and Its Application


    Dagstuhl Workshop "Intelligent Methods for Test and Reliability"  2019.09  -  2019.09 

  • Logic Fault Diagnosis of Hidden Delay Defects

    FTC  2019.07  -  2019.07 

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Grants-in-Aid for Scientific Research 【 display / non-display

  • Research on Defect-Aware Soft-Error Mitigation for Reliable LSIs

    Grant-in-Aid for Scientific Research(B)

    Project Year:  2021.04  -  2025.03

    Project Number:  21H03411

  • Research on Design and Test for Radiation-Hardened Storage-Cells

    JSPS Bilateral Joint Research Project (NSFC)

    Project Year:  2021.04  -  2023.12

    Project Number:  20217409