HOLST Stefan (ホルスト シュテファン)

HOLST Stefan

写真a

職名

准教授

研究室住所

福岡県飯塚市川津680-4

研究分野・キーワード

VLSIテスト、故障診断、回路シムレーション

ホームページ

http://www.s-holst.de/lab

特記事項

Dr. rer. nat.

Scopus 論文情報  
総論文数: 0  総Citation: 0  h-index: 7

Citation Countは当該年に発表した論文の被引用数

出身大学 【 表示 / 非表示

  • 2005年11月   シュトゥットガルト大学   計算機科学・電気工学・情報技術分野   情報工学   卒業   ドイツ連邦共和国

出身大学院 【 表示 / 非表示

  • 2012年09月  シュトゥットガルト大学   計算機アーキテクチャ研究所  情報工学  博士課程・博士後期課程  修了  ドイツ連邦共和国

取得学位 【 表示 / 非表示

  • シュトゥトッガルト大学 -  博士(理学)  2012年09月

学内職務経歴 【 表示 / 非表示

  • 2021年04月
    -
    継続中

    九州工業大学   大学院情報工学研究院   情報・通信工学研究系   准教授  

  • 2019年04月
    -
    2021年03月

    九州工業大学   大学院情報工学研究院   情報・通信工学研究系   助教  

  • 2013年04月
    -
    2019年03月

    九州工業大学   大学院情報工学研究院   情報創成工学研究系   助教  

所属学会・委員会 【 表示 / 非表示

  • 2006年01月
    -
    継続中
     

    IEEE  アメリカ合衆国

 

論文 【 表示 / 非表示

  • On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    IEICE Transactions on Information and Systems  ( 一般社団法人 電子情報通信学会 )  E104D ( 6 ) 816 - 827   2021年01月  [査読有り]

     概要を見る

    Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

    DOI Scopus CiNii

  • Logic Fault Diagnosis of Hidden Delay Defects

    Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

    Proceedings - International Test Conference    2020-November   2020年11月  [査読有り]

     概要を見る

    Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

    DOI Scopus

  • Targeted partial-shift for mitigating shift switching activity hot-spots during scan test

    Holst S., Shi S., Wen X.

    Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC    2019-December   124 - 129   2019年12月  [査読有り]

     概要を見る

    Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

    DOI Scopus

  • Variation-aware small delay fault diagnosis on compressed test responses

    Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

    Proceedings - International Test Conference    2019-November   2019年11月  [査読有り]

     概要を見る

    With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

    DOI Scopus

  • A fault-tolerant MPSoC for CubeSats

    Fuchs C.M., Chou P., Wen X., Murillo N.M., Furano G., Holst S., Tavoularis A., Lu S.K., Plaat A., Marinis K.

    2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019      2019年10月  [査読有り]

     概要を見る

    We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

    DOI Scopus

全件表示 >>

口頭発表・ポスター発表等 【 表示 / 非表示

  • Stochastic Computing based Neural Networks on Unreliable Hardware

    Stefan Holst

    FTC  2021年07月  -  2021年07月   

  • Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

    Stefan Holst

    South European Test Seminar (SETS) 2020  (Obergurgl, Austria)  2020年03月  -  2020年03月   

  • Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

    Stefan Holst

    FTC  2020年01月  -  2020年01月   

  • Accelerated Timing Simulation and Its Application

    Stefan Holst  [招待有り]

    Dagstuhl Workshop "Intelligent Methods for Test and Reliability"  (Dagstuhl, Germany)  2019年09月  -  2019年09月   

  • Logic Fault Diagnosis of Hidden Delay Defects

    Stefan Holst

    FTC  2019年07月  -  2019年07月   

全件表示 >>

学術関係受賞 【 表示 / 非表示

  • Distinquished Paper of International Test Conference 2017

    2017年10月   Program Committee of ITC 2017   日本国

    受賞者:  Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

  • Best Paper of Asian Test Symposium 2015

    2016年11月   Program Committee of ATS 2015   日本国

    受賞者:  K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, H. Furukawa

  • Best Paper of European Test Symposium 2007

    2008年05月   Program Committee of ETS 2007   ドイツ連邦共和国

    受賞者:  Stefan Holst, Hans-Joachim Wunderlich

科研費獲得実績 【 表示 / 非表示

  • 高信頼LSI創出のための欠陥考慮型耐ソフトエラー技術に関する研究

    基盤研究(B)

    研究期間:  2021年04月  -  2025年03月

    研究課題番号:  21H03411

  • 耐放射線記憶素子の設計とテストに関する研究

    二国間交流事業 共同研究(NSFC)

    研究期間:  2021年04月  -  2023年12月

    研究課題番号:  20217409

海外研究歴 【 表示 / 非表示

  • Research Collaboration With Prof. Krishnendu Chakrabarty

    Duke University, Durham, North Carolina  アメリカ合衆国  研究期間:  2015年09月  -  2015年11月

 

担当授業科目 【 表示 / 非表示

  • 2020年度  情報通信工学実験Ⅲ(1Q)

 

社会貢献活動(講演会・出前講義等) 【 表示 / 非表示

  • Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize

    2019年08月
     
     
  • Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize

    2018年08月
     
     
 

国際会議の開催 【 表示 / 非表示

  • IEEE Asian Test Symposium 2021

    Matsuyama, Japan  2021年11月22日  -  2021年11月25日  Yukiya Miura, Satoshi Ohtake

  • IEEE Latin-American Test Symposium 2021

    Punta del Este, Uruguay  2021年10月27日  -  2021年10月29日  Raoul Velazco, Yervant Zorian

  • IEEE European Test Symposium 2020

    Tallinn, Estonia  2020年05月25日  -  2020年06月01日  Artur Jutman, Jaan Raik

  • IEEE Latin-American Test Symposium 2020

    Jatiúca (Maceió), Brazil  2020年03月30日  -  2020年04月02日  Letícia Maria Bolzani Poehls, Yervant Zorian

  • IEEE Asian Test Symposium 2019

    Kolkata, India  2019年12月10日  -  2019年12月13日  Hafizur Rahaman, Krishnendu Chakrabarty

全件表示 >>

その他国際交流活動 【 表示 / 非表示

  • Student Internship Program - University of Stuttgart

    活動期間:  2019年12月  -  2019年12月

     概要を見る

    Organize a 2-week travel of 6 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間:  2018年12月  -  2018年12月

     概要を見る

    Organize a 2-week travel of 6 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間:  2017年12月  -  2017年12月

     概要を見る

    Organize a 2-week travel of 6 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間:  2016年12月  -  2016年12月

     概要を見る

    Organize a 2-week travel of 4 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間:  2016年03月  -  2016年03月

     概要を見る

    Organize a 1-week travel of 4 Kyutech students to Germany for academic and cultural exchange.