2024/05/14 更新

ホルスト シュテファン
HOLST Stefan
HOLST Stefan
Scopus 論文情報  
総論文数: 0  総Citation: 0  h-index: 8

Citation Countは当該年に発表した論文の被引用数

所属
大学院情報工学研究院 情報・通信工学研究系
職名
准教授
外部リンク

研究キーワード

  • 故障診断

  • 回路シミュレーション

  • VLSIテスト

出身学校

  • 2005年11月   シュトゥットガルト大学   計算機科学・電気工学・情報技術分野   情報工学   卒業   ドイツ連邦共和国

出身大学院

  • 2012年09月   シュトゥットガルト大学   計算機アーキテクチャ研究所   情報工学   博士課程・博士後期課程   修了   ドイツ連邦共和国

取得学位

  • シュトゥトッガルト大学  -  博士(理学)   2012年09月

学内職務経歴

  • 2021年04月 - 現在   九州工業大学   大学院情報工学研究院   情報・通信工学研究系     准教授

  • 2019年04月 - 2021年03月   九州工業大学   大学院情報工学研究院   情報・通信工学研究系     助教

  • 2013年04月 - 2019年03月   九州工業大学   大学院情報工学研究院   情報創成工学研究系     助教

所属学会・委員会

  • 2006年01月 - 現在   IEEE   アメリカ合衆国

論文

  • Stock price movement prediction based on Stocktwits investor sentiment using FinBERT and ensemble SVM 査読有り 国際誌

    Liu J.X., Leu J.S., Holst S.

    PeerJ Computer Science   9   2023年01月

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    担当区分:最終著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    Investor sentiment plays a crucial role in the stock market, and in recent years, numerous studies have aimed to predict future stock prices by analyzing market sentiment obtained from social media or news. This study investigates the use of investor sentiment from social media, with a focus on Stocktwits, a social media platform for investors. However, using investor sentiment on Stocktwits to predict stock price movements may be challenging due to a lack of user-initiated sentiment data and the limitations of existing sentiment analyzers, which may inaccurately classify neutral comments. To overcome these challenges, this study proposes an alternative approach using FinBERT, a pre-trained language model specifically designed to analyze the sentiment of financial text. This study proposes an ensemble support vector machine for improving the accuracy of stock price movement predictions. Then, it predicts the future movement of SPDR S&P 500 Index Exchange Traded Funds using the rolling window approach to prevent look-ahead bias. Through comparing various techniques for generating sentiment, our results show that using the FinBERT model for sentiment analysis yields the best results, with an F1-score that is 4-5% higher than other techniques. Additionally, the proposed ensemble support vector machine improves the accuracy of stock price movement predictions when compared to the original support vector machine in a series of experiments.

    DOI: 10.7717/peerj-cs.1403

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85162079723&origin=inward

  • BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell 査読有り 国際誌

    Holst S., Ma R., Wen X., Yan A., Xu H.

    Proceedings of the European Test Workshop   2023-May   2023年01月

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    担当区分:筆頭著者, 責任著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Ensuring the correct operation of modern VLSI circuits within safety-critical systems is essential since modern technology nodes are more susceptible to Early-Life Failures (ELFs) and radiation-induced Soft-Errors (SEs). Tackling both of these challenges leads to contradicting design requirements: Effective in-field ELF detection requires online-monitoring or periodic built-in self-Testing with excellent cell-internal defect coverage. SE-hardened latch designs, however, are less testable because they are designed to mask cell-internal failures. We propose BiSTAHL, a new SE-hardened scan-cell design that is fully built-in self-Testable for both production defects and ELFs.

    DOI: 10.1109/ETS56758.2023.10174154

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85166195402&origin=inward

  • On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks 査読有り 国際誌

    Neugebauer F., Holst S., Polian I.

    Proceedings of the European Test Workshop   2022-May   2022年01月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Stochastic computing (SC) with its stream-based, probabilistic number representation promises large area and power benefits as well as increased error tolerance compared to conventional binary computing. While SC is less precise, it is considered a promising option for implementing neural network inferencing in ultra-low-power edge devices. SC-based Neural Networks (SCNNs) typically combine stochastic and binary components for interfacing and to alleviate certain SC limitations. Moreover, ultra-low-power VLSI for edge computing is often less reliable due to noisy environments or deliberate power-reliability trade-offs. In this work, we present the first detailed investigation of the behavior of an SCNN and its individual components on hardware prone to timing errors. Our results show that robustness of SC is highly dependent on specific design choices and that biases in the error distributions may even cause SCNNs to perform worse under certain circumstances than comparable binary implementations. It shows that robustness should be treated as a design goal in SC rather than taken for granted.

    DOI: 10.1109/ETS54262.2022.9810429

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85134240649&origin=inward

  • Evaluation and Test of Production Defects in Hardened Latches 査読有り 国際誌

    Ma R., Holst S., Wen X., Yan A., Xu H.

    IEICE Transactions on Information and Systems ( 一般社団法人 電子情報通信学会 )   E105D ( 5 )   996 - 1009   2022年01月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)

    As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (PTVF), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed PTVF metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.

    DOI: 10.1587/transinf.2021EDP7216

    Scopus

    CiNii Research

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85131218056&origin=inward

  • Power and Energy Safe Real-Time Multi-Core Task Scheduling 査読有り

    Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

    Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022   16 - 21   2022年01月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Scheduling tasks in multi-core real-time systems (e.g. low power devices/appliances) while keeping energy in mind is a difficult design challenge. Extensive work has been done to overcome this issue, in which task instances (jobs) have varying levels of operation power. Different combinations of system energy (SE) and subsequent minimal SE have been attained based on the power levels. However, both system power (SP) and system energy (SE) are expensive to operate. As a result, task scheduling for multi-core systems based on balancing both the SP and the SE (referred to as feasible SP and feasible SE, respectively) to achieve the lowest system cost is an issue that has not been adequately addressed in the literature. The states or zones of feasible SP (FSP) and feasible SE (FSE) are thought to be possible zones/states of the system where the system's power configuration provides lowered SE with increased job accommodation, lowering the system's cost. We offer a unique scheduling approach in which we identify numerous FSP and FSE zones (feasible zones/states) to fit all jobs to cores while minimising system cost (including optimum cost) and meeting deadlines. By giving weights to the FSP and FSE, we present a mechanism for ranking the many viable system states. The model is tested using produced task sets (low power task sets), and the results reveal that our approach effectively finds feasible zones, including the best one.

    DOI: 10.1109/VLSID2022.2022.00016

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85139217781&origin=inward

  • On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption 査読有り 国際誌

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    IEICE Transactions on Information and Systems ( 一般社団法人 電子情報通信学会 )   E104D ( 6 )   816 - 827   2021年01月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)

    Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

    DOI: 10.1587/transinf.2020EDP7042

    Scopus

    CiNii Article

    CiNii Research

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85107932665&origin=inward

  • GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators 査読有り 国際誌

    Holst S., Bumun L., Wen X.

    Proceedings of the Asian Test Symposium   2021-November   127 - 132   2021年01月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Systolic arrays are currently used in autonomous systems such as self-driving cars to accelerate the enormous amount of matrix operations necessary for DNN inference. The reliability of such accelerators are of utmost importance since any loss in DNN accuracy due to erroneous calculations can have dire consequences. We propose a novel method to measure accuracy losses caused by arbitrary timing faults in systolic arrays. Our GPU-based simulation system enables for the first time a complete and accurate timing simulation of all inference-related matrix operations on large systolic arrays. A single consumer-grade GPU can simulate a LeNet-5 at a throughput of about 13s per inference. Furthermore, our simulation approach readily scales to larger DNNs and multiple GPUs.

    DOI: 10.1109/ATS52891.2021.00034

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85124705512&origin=inward

  • Logic Fault Diagnosis of Hidden Delay Defects 査読有り

    Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

    Proceedings - International Test Conference   2020-November   2020年11月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

    DOI: 10.1109/ITC44778.2020.9325234

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85100182545&origin=inward

  • Targeted partial-shift for mitigating shift switching activity hot-spots during scan test 査読有り

    Holst S., Shi S., Wen X.

    Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC   2019-December   124 - 129   2019年12月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

    DOI: 10.1109/PRDC47002.2019.00042

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85078466669&origin=inward

  • Variation-aware small delay fault diagnosis on compressed test responses 査読有り

    Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

    Proceedings - International Test Conference   2019-November   2019年11月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

    DOI: 10.1109/ITC44170.2019.9000143

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85081599098&origin=inward

  • A fault-tolerant MPSoC for CubeSats 査読有り

    Fuchs C.M., Chou P., Wen X., Murillo N.M., Furano G., Holst S., Tavoularis A., Lu S.K., Plaat A., Marinis K.

    2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019   2019年10月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

    DOI: 10.1109/DFT.2019.8875417

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85074436279&origin=inward

  • STAHL: A novel scan-test-aware hardened latch design 査読有り

    Ma R., Holst S., Wen X., Yan A., Xu H.

    Proceedings of the European Test Symposium   2019-May   2019年05月

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    担当区分:責任著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Germany   Baden-Baden  

    As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulner-ability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode.

    DOI: 10.1109/ETS.2019.8791544

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85071198489&origin=inward

  • Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing 査読有り 国際誌

    Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

    Proceedings of the Asian Test Symposium   2018-October   149 - 154   2018年12月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    © 2018 IEEE. High scan shift power often leads to excessive heat as well as shift timing failures. Partial shift (shifting a subset of scan chains at a time) is a widely adopted approach for avoiding excessive heat by reducing global switching activity, we show for the first time that it may actually cause excessive IR-drop on some clock buffers and worsen shift clock skews, thus increasing the risk of shift timing failures. This paper addresses this problem with an innovative method, namely Clock-Skew-Aware Scan Chain Grouping (CSA-SCG). CSA-SCG properly groups scan chains to be shifted simultaneously so as to reduce the imbalance of switching activity around the clock paths for neighboring scan flip-flops in scan chains. Experiments on large ITC'99 benchmark circuits demonstrate the effectiveness of CSA-SCG for reducing scan shift clock skews to lower the risk of shift timing failures in partial shift.

    DOI: 10.1109/ATS.2018.00037

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85060029684&origin=inward

  • The impact of production defects on the soft-error tolerance of hardened latches 査読有り 国際誌

    Holst S., Ma R., Wen X.

    Proceedings of the European Test Symposium   2018-May   1 - 6   2018年06月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Germany   Bremen  

    © 2018 IEEE. As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces the test coverage of cell-internal production defects. Moreover, the test escapes reduce the soft-error tolerance of the defective latches. This work introduces a new soft-error vulnerability metric called Post Test Vulnerability Factor that correctly measures the added vulnerability to transiant frults such as particle strikes caused by undiscovered production defects within hardened latches.

    DOI: 10.1109/ETS.2018.8400694

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85050003309&origin=inward

  • Scan chain grouping for mitigating ir-drop-induced test data corruption 査読有り 国際誌

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    Proceedings of the Asian Test Symposium   Part F134421   140 - 145   2018年01月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    © 2017 IEEE. Loading and unloading test patterns during scan testing causes many scan flip-flops to trigger simultaneously. This instantaneous switching activity during shift in turn may cause excessive IR-drop that can disrupt the states of some scan flip-flops and corrupt test stimuli or responses. A common design technique to even out these instantaneous power surges is to design multiple scan chains and shift only a group of the scan chains at a same time. This paper introduces a novel algorithm to optimally group scan chains so as to minimize the probability of test data corruption caused by excessive instantaneous IR-drop on scan flip-flops. The experiments show optimal results on all large ITC'99 benchmark circuits.

    DOI: 10.1109/ATS.2017.37

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85045207810&origin=inward

  • Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors 査読有り 国際誌

    Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

    IEEE International Test Conference   2017-December   1 - 8   2017年10月

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    担当区分:筆頭著者, 責任著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    United States   Fort Worth   2017年10月31日  -  2017年11月02日

    Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases of test data corruption are mitigated in a non-intrusive way by selective test data manipulation and masking of affected responses. Evaluation results show the computational feasibility of our method for large benchmark circuits, and demonstrate that a few targeted pattern changes provide large potential gains in shift safety and test time with negligible cost in fault coverage.

    DOI: 10.1109/TEST.2017.8242055

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85046442899&origin=inward

  • GPU-Accelerated Simulation of Small Delay Faults 査読有り 国際誌

    Schneider E., Kochte M., Holst S., Wen X., Wunderlich H.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   36 ( 5 )   829 - 841   2017年05月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)

    © 1982-2012 IEEE. Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs toward even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this paper, we present a method for fast and waveform-accurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms, and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.

    DOI: 10.1109/TCAD.2016.2598560

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85027524817&origin=inward

  • Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test 査読有り 国際誌

    Eggersglub S., Eggersglub S., Holst S., Tille D., Miyase K., Wen X.

    Proceedings of the Asian Test Symposium   173 - 178   2016年12月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    © 2016 IEEE. Launch-Switching-Activity (LSA) is a serious problem during at-speed testing of integrated circuits, since localized LSA may lead to severe IR-drop and thus failures. The excessive LSA is conventionally mitigated by reducing the switching activity through special low-power test generation techniques, typically resulting in severe test pattern inflation and high test costs. This work introduces a novel concept of Low-Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power (HCP) regions. LCP-TPs also help in retaining high test compaction capability. An optimization- SAT based procedure is proposed to compute a small set of optimal LCP-TP locations for compact at-speed test sets with effective capture power reduction. Experimental results clearly demonstrate the advantages of LCP-TP insertion.

    DOI: 10.1109/ATS.2016.41

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85010207621&origin=inward

  • Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test 査読有り 国際誌

    Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.

    Proceedings of the Asian Test Symposium   19 - 24   2016年12月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    © 2016 IEEE. IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.

    DOI: 10.1109/ATS.2016.49

    Scopus

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  • Logic-path-and-clock-path-aware at-speed scan test generation 査読有り 国際誌

    Li F., Wen X., Miyase K., Holst S., Kajihara S.

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人 電子情報通信学会 )   E99A ( 12 )   2310 - 2319   2016年12月

     詳細を見る

    記述言語:英語   掲載種別:研究論文(学術雑誌)

    Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power- safety without significant test vector count inflation and test quality loss.

    DOI: 10.1587/transfun.E99.A.2310

    Scopus

    CiNii Article

    CiNii Research

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84999232940&origin=inward

  • Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch 査読有り 国際誌

    Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

    IEEE Asian Test Symposium   2016-February   103 - 108   2015年11月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    India   Mumbai   2015年11月22日  -  2015年11月25日

    IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.

    DOI: 10.1109/ATS.2015.25

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84963582651&origin=inward

  • High-Throughput Logic Timing Simulation on GPGPUs 査読有り 国際誌

    S. Holst, M. E. Imhof, H.-J. Wunderlich

    ACM Transactions on Design Automation of Electronic Systems   20 ( 3 )   Article No. 37   2015年06月

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    担当区分:筆頭著者, 責任著者   記述言語:英語   掲載種別:研究論文(学術雑誌)

    Many EDA tasks such as test set characterization or the precise estimation of power consumption, power droop and temperature development, require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. The new simulation system presented here is able to accelerate such tasks by more than two orders of magnitude and provides for the first time fast and comprehensive timing simulations for industrialsized designs. Hazards, pulse-filtering, and pin-to-pin delay are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more realistic delay models and further applications. A sophisticated mapping with efficient memory utilization and access patterns as well as minimal synchronizations and control flow divergence is able to use the full potential of GPGPU architectures. To provide such a mapping, we combine for the first time the versatility of event-based timing simulation and multidimensional parallelism used in GPU-based gate-level simulators. The result is a throughput-optimized timing simulation algorithm, which runs many simulation instances in parallel and at the same time fully exploits gate-parallelism within the circuit.

    DOI: 10.1145/2714564

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84934760432&origin=inward

  • A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys 査読有り 国際誌

    I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

    IEEE European Test Symposium   2015年05月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Romania   Cluj-Napoca   2015年05月25日  -  2015年05月29日

    This paper proposes a novel soft-error tolerant TCAM using partial don't-care keys (X-keys), namely TX, which significantly enhances the tolerance of the TCAM against soft errors. Experimental results show that the soft-error tolerance of the TX outperforms existing schemes. Moreover, the overhead of the TX is very small.

    DOI: 10.1109/ETS.2015.7138743

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84942548945&origin=inward

  • GPU-Accelerated Small Delay Fault Simulation 査読有り

    E. Schneider, S. Holst, M. A. Kochte, X. Wen, H.-J. Wunderlich

    Design and Test in Europe   1174 - 1179   2015年03月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    France   Grenoble   2015年03月09日  -  2015年03月13日

  • GPU-accelerated small delay fault simulation 査読有り 国際誌

    Schneider E., Holst S., Kochte M., Wen X., Wunderlich H.

    Proc. Design, Automation and Test in Europe (DATE)   2015-April   1174 - 1179   2015年01月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    © 2015 EDAA. The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multimillion gate designs without fault dropping for the first time.

    DOI: 10.7873/date.2015.0077

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84945918312&origin=inward

  • Soft-Error Tolerant TCAMs for High-Reliability Packet Classifications 査読有り 国際誌

    I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase

    IEEE Asia Pacific Conference on Circuits and Systems   2015-February ( February )   471 - 474   2014年11月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Japan   Ishigaki   2014年11月17日  -  2014年11月20日

    In the internet, packets are classified by source and destination addresses, ports, and protocol type. Ternary content addressable memories (TCAMs) are often used to perform this operation. However, high-reliability packet classifiers in aerospace network applications require soft-error tolerant TCAMs to prevent system from errors caused by environmental factors such as high-energy radiations. This paper shows a soft-error tolerant TCAM (STTCAM), which enhances the reliability of TCAMs for soft-errors. The STTCAM randomly selects a search key to be evaluated. Then, parallel TCAMs detect single-bit flip errors. When the search key matches the last word, the STTCAM calculates the similarity of the search key to the TCAM word. If 99% of similarity is detected, then a suspected error is found and the STTCAM refreshes the TCAM words by using a backup ECC-SRAM. Experimental results show that the STTCAM improves TCAMs reliability significantly than the existing scheme. The STTCAM can be easily implemented and is useful for fault-tolerant packet classifiers.

    DOI: 10.1109/APCCAS.2014.7032821

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84937926775&origin=inward

  • Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り 国際誌

    E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

    International Conference on Computer-Aided Design   2015-January ( January )   17 - 23   2014年11月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    USA   San Jose   2014年11月03日  -  2014年11月06日

    Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate timesimulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.

    DOI: 10.1109/ICCAD.2014.7001324

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84936860899&origin=inward

  • On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り

    Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

    IEICE Transactions on Information and Systems   E97-D ( 10 )   2706 - 2718   2014年10月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)

    DOI: 10.1587/transinf.2014EDP7039

    Scopus

    CiNii Article

  • Scan test power simulation on GPGPUs 査読有り

    Holst S., Schneider E., Wunderlich H.

    Proceedings of the Asian Test Symposium   155 - 160   2012年12月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models. © 2012 IEEE.

    DOI: 10.1109/ATS.2012.23

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84872571782&origin=inward

  • Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures 査読有り

    Braun C., Holst S., Wunderlich H., Castillo J., Gross J.

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors   207 - 212   2012年12月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Markov-Chain Monte-Carlo (MCMC) methods are an important class of simulation techniques, which execute a sequence of simulation steps, where each new step depends on the previous ones. Due to this fundamental dependency, MCMC methods are inherently hard to parallelize on any architecture. The upcoming generations of hybrid CPU/GPGPU architectures with their multi-core CPUs and tightly coupled many-core GPGPUs provide new acceleration opportunities especially for MCMC methods, if the new degrees of freedom are exploited correctly. In this paper, the outcomes of an interdisciplinary collaboration are presented, which focused on the parallel mapping of a MCMC molecular simulation from thermodynamics to hybrid CPU/GPGPU computing systems. While the mapping is designed for upcoming hybrid architectures, the implementation of this approach on an NVIDIA Tesla system already leads to a substantial speedup of more than 87x despite the additional communication overheads. © 2012 IEEE.

    DOI: 10.1109/ICCD.2012.6378642

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84872089667&origin=inward

  • Structural Test and Diagnosis for Graceful Degradation of NoC Switches 査読有り

    Dalirsani A., Holst S., Elm M., Wunderlich H.

    Journal of Electronic Testing: Theory and Applications (JETTA)   28 ( 6 )   831 - 841   2012年10月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)

    Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86 % and 72.42 % of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs. © 2012 Springer Science+Business Media, LLC.

    DOI: 10.1007/s10836-012-5329-9

    Scopus

    その他リンク: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84878487809&origin=inward

  • Embedded test for highly accurate defect localization 査読有り

    Mumtaz A., Imhof M., Holst S., Wunderlich H.

    Proceedings of the Asian Test Symposium   213 - 218   2011年12月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Modern diagnosis algorithms are able to identify the defective circuit structure directly from existing fail data without being limited to any specialized fault models. Such algorithms however require test patterns with a high defect coverage, posing a major challenge particularly for embedded testing. In mixed-mode embedded test, a large amount of pseudo-random(PR) patterns are applied prior to deterministic test pattern. Partial Pseudo-Exhaustive Testing (P-PET)replaces these pseudo-random patterns during embedded testing by partial pseudo-exhaustive patterns to test a large portion of a circuit fault-model independently. The overall defect coverage is optimized compared to random testing or deterministic tests using the stuck-at fault model while maintaining a comparable hardware overhead and the same test application time. This work for the first time combines P-PET with a fault model independent diagnosis algorithm and shows that arbitrary defects can be diagnosed on average much more precisely than with standard embedded testing. The results are compared to random pattern testing and deterministic testing targeting stuck-at faults. © 2011 IEEE.

    DOI: 10.1109/ATS.2011.60

    Scopus

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  • Structural test for graceful degradation of NoC switches 査読有り

    Dalirsani A., Holst S., Elm M., Wunderlic H.

    Proceedings - 16th IEEE European Test Symposium, ETS 2011   183 - 188   2011年08月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)

    Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is increased at the cost of reduced performability. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions rather than providing only a pass/fail result for the complete switch. The new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects to determine the unaffected switch functions and use partially defective NoC switches. According to the experimental results, this improves the performability of NoCs as more than 61% of defects only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with any switch design. © 2011 IEEE.

    DOI: 10.1109/ETS.2011.33

    Scopus

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▼全件表示

口頭発表・ポスター発表等

  • Stochastic Computing based Neural Networks on Unreliable Hardware

    Stefan Holst

    FTC 

     詳細を見る

    開催期間: 2021年07月16日   記述言語:英語  

  • Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

    Stefan Holst

    South European Test Seminar (SETS) 2020 

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    開催期間: 2020年03月03日 - 2020年03月06日   記述言語:英語   開催地:Obergurgl, Austria  

  • Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses

    Stefan Holst

    FTC 

     詳細を見る

    開催期間: 2020年01月23日 - 2020年01月25日   記述言語:英語  

  • Accelerated Timing Simulation and Its Application 招待有り

    Stefan Holst

    Dagstuhl Workshop "Intelligent Methods for Test and Reliability" 

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    開催期間: 2019年09月11日 - 2019年09月13日   記述言語:英語   開催地:Dagstuhl, Germany  

  • Logic Fault Diagnosis of Hidden Delay Defects

    Stefan Holst

    FTC 

     詳細を見る

    開催期間: 2019年07月18日 - 2019年07月20日   記述言語:英語  

  • Small Delay Fault Diagnosis with Compacted Responses

    Stefan Holst

    Design Automation Conference 2019 

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    開催期間: 2019年06月02日 - 2019年06月06日   記述言語:英語   開催地:Las Vegas, USA  

  • Small Delay Fault Diagnosis with Compacted Responses

    Stefan Holst

    South European Test Seminar (SETS) 2019 

     詳細を見る

    開催期間: 2019年03月11日 - 2019年03月15日   記述言語:英語  

  • Small Delay Fault Diagnosis on Compacted Responses

    Stefan Holst

    FTC 

     詳細を見る

    開催期間: 2019年01月24日 - 2019年01月26日   記述言語:英語  

  • Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits 招待有り

    Stefan Holst

    九州工業大学 重点プロジェクトセンター合同ワークショップ 

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    開催期間: 2018年11月06日 - 2018年11月07日   記述言語:英語  

  • Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits

    Stefan Holst

    DAシンポジウム2018 

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    開催期間: 2018年08月29日 - 2018年08月30日   記述言語:英語  

  • Logic Diagnosis - How to Find Unknown Defects 招待有り

    Stefan Holst

    Joint NTUST/Kyutech Seminar 

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    開催期間: 2018年08月21日   記述言語:英語  

  • Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits

    Stefan Holst

    FTC 

     詳細を見る

    開催期間: 2018年07月19日 - 2018年07月21日   記述言語:英語  

  • Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors

    Stefan Holst

    South European Test Seminar (SETS) 2017 

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    開催期間: 2017年03月20日 - 2017年03月24日   記述言語:英語  

  • The AR/VR Revolution and Its Implications for EDA Tools

    Stefan Holst

    FTC 

     詳細を見る

    開催期間: 2017年01月19日 - 2017年01月21日   記述言語:英語  

  • Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation

    Stefan Holst

    South European Test Seminar (SETS) 2016 

     詳細を見る

    開催期間: 2016年03月07日 - 2016年03月11日   記述言語:英語  

  • On the Stability of Systems in Changing Environments

    Stefan Holst

    South European Test Seminar (SETS) 2015 

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    開催期間: 2015年03月16日 - 2015年03月20日   記述言語:英語  

  • Big Data and Small Transistors High-Performance VLSI Simulation 招待有り

    Stefan Holst

    Joint NTUST/Kyutech Seminar 

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    開催期間: 2015年03月05日   記述言語:英語  

  • Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits

    Stefan Holst

    FTC 

     詳細を見る

    開催期間: 2014年01月23日 - 2014年01月24日   記述言語:英語  

▼全件表示

学術関係受賞

  • Best Paper of Asian Test Symposium 2021

    Program Committee of ATS 2021   2022年11月

    S. Holst, B. Lim, X. Wen

     詳細を見る

    受賞国:日本国

  • Distinquished Paper of International Test Conference 2017

    Program Committee of ITC 2017   2017年10月

    Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

     詳細を見る

    受賞国:日本国

  • Best Paper of Asian Test Symposium 2015

    Program Committee of ATS 2015   2016年11月

    K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, H. Furukawa

     詳細を見る

    受賞国:日本国

  • Best Paper of European Test Symposium 2007

    Program Committee of ETS 2007   2008年05月

    Stefan Holst, Hans-Joachim Wunderlich

     詳細を見る

    受賞国:ドイツ連邦共和国

海外研究歴

  • Research Collaboration With Prof. Krishnendu Chakrabarty

    Duke University, Durham, North Carolina  アメリカ合衆国  研究期間:  2015年09月 - 2015年11月

担当授業科目(学内)

  • 2023年度   国際エンジニアリング共同講義Ⅳ

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  • 2022年度   高信頼LSI設計

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  • 2022年度   国際エンジニアリング共同講義Ⅲ

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  • 2022年度   情報通信工学実験Ⅱ

  • 2022年度   情報通信工学実験Ⅲ

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    科目区分:学部専門科目

  • 2021年度   情報通信工学実験Ⅲ

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    科目区分:学部専門科目

  • 2020年度   情報通信工学実験Ⅲ(1Q)

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社会貢献活動(講演会・出前講義等)

  • Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize

    役割:講師

    Ehime University, Matsuyama  2019年08月02日

     詳細を見る

    対象: 大学生

    種別:出前授業

  • Inside the Mind of a Researcher - A Practical Guide to the Nobel Prize

    役割:講師

    Ehime University, Matsuyama  2018年08月03日

     詳細を見る

    対象: 大学生

    種別:出前授業

国際会議開催(学会主催除く)

  • IEEE Asian Test Symposium 2021

    Yukiya Miura, Satoshi Ohtake  Matsuyama, Japan  2021年11月22日 - 2021年11月25日

  • IEEE Latin-American Test Symposium 2021

    Raoul Velazco, Yervant Zorian  Punta del Este, Uruguay  2021年10月27日 - 2021年10月29日

  • IEEE European Test Symposium 2020

    Artur Jutman, Jaan Raik  Tallinn, Estonia  2020年05月25日 - 2020年06月01日

  • IEEE Latin-American Test Symposium 2020

    Letícia Maria Bolzani Poehls, Yervant Zorian  Jatiúca (Maceió), Brazil  2020年03月30日 - 2020年04月02日

  • IEEE Asian Test Symposium 2019

    Hafizur Rahaman, Krishnendu Chakrabarty  Kolkata, India  2019年12月10日 - 2019年12月13日

  • IEEE Asian Test Symposium 2016

    Tomoo Inoue, Hiroshi Takahashi  Hiroshima, Japan  2016年11月21日 - 2016年11月24日

▼全件表示

その他国際交流活動

  • Student Internship Program - University of Stuttgart

    活動期間: 2019年12月

     詳細を見る

    Organize a 2-week travel of 6 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間: 2018年12月

     詳細を見る

    Organize a 2-week travel of 6 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間: 2017年12月

     詳細を見る

    Organize a 2-week travel of 6 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間: 2016年12月

     詳細を見る

    Organize a 2-week travel of 4 Kyutech students to Germany for academic and cultural exchange.

  • Student Internship Program - University of Stuttgart

    活動期間: 2016年03月

     詳細を見る

    Organize a 1-week travel of 4 Kyutech students to Germany for academic and cultural exchange.