研究者詳細 - HOLST Stefan

論文 - HOLST Stefan

分割表示40 件中 1 - 20 件目／全件表示 >>

Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design 査読有り

Ma R., Holst S., Xu H., Wen X., Wang S., Li J., Yan A.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 2 ) 449 - 461 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Soft errors have been a severe threat to the reliability of modern integrated circuits (ICs), making hardened latch designs indispensable for masking soft errors with redundancy. However, the added redundancy also masks production defects as soft errors; this makes it hard to detect defects in hardened latches, thus significantly reducing their reliability. Our previous work proposed the scan-test-aware hardened latch (STAHL) design, the first for addressing the issue of low defect detectability of hardened latch designs. However, STAHL still suffers from two problems: 1) it is not self-resilient to soft errors and 2) a STAHL-based scan design requires one additional control signal. This article proposes a high defect detectable and single-event-upset (SEU)-resilient robust (HIDER) latch to address the issues of the low defect detectability of existing hardened latches and the STAHLs lack of SEU-resilient capability. Two scan designs [HIDER-based scan-cell-S (HIDER-SC-S) and HIDER-based scan-cell-F (HIDER-SC-F)], as well as two corresponding test procedures, are proposed to fully test HIDER latch with only one control signal. Simulation results show that the HIDER latch achieves the highest defect coverage (DC) in both single latch cell detection and scan tests among all existing hardened latch designs. In addition, the HIDER latch has much lower power and a smaller delay than STAHL.

DOI： 10.1109/TVLSI.2024.3467089

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ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits 査読有り

Reimer J.D., Holst S., Sadeghi-Kohan S., Wunderlich H.J., Hellebrand S.

2025 International Symposium of Electronics Design Automation Iseda 2025 502 - 507 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Accurate timing analysis is crucial for design and verification. In addition, high throughput and scalability are mandatory for simulation-based approaches, which must often cope with high input data volumes and a high number of large circuit instances. Existing approaches using a binary switch model offer an excellent trade-off between accurate SPICE and high-performance gate level simulation in planar CMOS. However, recent experiments have shown that the binary switch model is not accurate enough for FinFET technology. The new approach presented in this paper integrates an enhanced switch-level model into an efficient GPU-based simulation flow. A high throughput is achieved by avoiding event-driven control at the top level, enabling the thread-parallel processing of independent components and input patterns. Experimental results confirm that the new approach accurately predicts the timing of digital circuits in modern CMOS technologies and scales well to multi-million transistor designs.

DOI： 10.1109/ISEDA65950.2025.11101032

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Motion Classification by Utilizing Machine Learning for Acceleration Data 査読有り

Ishizu K., Honda T., Miyase K., Holst S., Ishikawa S., Sengupta R., Polian I.

Digest of Technical Papers IEEE International Conference on Consumer Electronics 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In recent years, professional athletes have utilized motion analysis to improve their performance and skill. However, since devices and systems used in motion analysis are very expensive, it is impossible for an athlete who does not have enough budget to use them. In this paper, we propose a motion analysis system using an inexpensive accelerometer controlled by Arduino and machine learning. The target motion in this work is bat swing in baseball. The acceleration from the target motion is measured and used to train a neural network. Users of this system can classify their motion into experienced one and inexperienced one, and then will be able to know the quality of their swing motion.

DOI： 10.1109/ICCE63647.2025.10929909

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GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting∗ 査読有り

Shi S., Holst S., Wen X.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E106.D ( 10 ) 1694 - 1704 2023年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC’99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

DOI： 10.1587/transinf.2023EDP7011

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Stock price movement prediction based on Stocktwits investor sentiment using FinBERT and ensemble SVM 査読有り国際誌

Liu J.X., Leu J.S., Holst S.

PeerJ Computer Science 9 2023年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

Investor sentiment plays a crucial role in the stock market, and in recent years, numerous studies have aimed to predict future stock prices by analyzing market sentiment obtained from social media or news. This study investigates the use of investor sentiment from social media, with a focus on Stocktwits, a social media platform for investors. However, using investor sentiment on Stocktwits to predict stock price movements may be challenging due to a lack of user-initiated sentiment data and the limitations of existing sentiment analyzers, which may inaccurately classify neutral comments. To overcome these challenges, this study proposes an alternative approach using FinBERT, a pre-trained language model specifically designed to analyze the sentiment of financial text. This study proposes an ensemble support vector machine for improving the accuracy of stock price movement predictions. Then, it predicts the future movement of SPDR S&P 500 Index Exchange Traded Funds using the rolling window approach to prevent look-ahead bias. Through comparing various techniques for generating sentiment, our results show that using the FinBERT model for sentiment analysis yields the best results, with an F1-score that is 4-5% higher than other techniques. Additionally, the proposed ensemble support vector machine improves the accuracy of stock price movement predictions when compared to the original support vector machine in a series of experiments.

DOI： 10.7717/peerj-cs.1403

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BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell 査読有り国際誌

Holst S., Ma R., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2023-May 2023年01月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Ensuring the correct operation of modern VLSI circuits within safety-critical systems is essential since modern technology nodes are more susceptible to Early-Life Failures (ELFs) and radiation-induced Soft-Errors (SEs). Tackling both of these challenges leads to contradicting design requirements: Effective in-field ELF detection requires online-monitoring or periodic built-in self-Testing with excellent cell-internal defect coverage. SE-hardened latch designs, however, are less testable because they are designed to mask cell-internal failures. We propose BiSTAHL, a new SE-hardened scan-cell design that is fully built-in self-Testable for both production defects and ELFs.

DOI： 10.1109/ETS56758.2023.10174154

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Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization 査読有り

Lylina N., Holst S., Jafarzadeh H., Kourfali A., Wunderlich H.J.

Proceedings 2023 IEEE 29th International Symposium on on Line Testing and Robust System Design Iolts 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The Preconditioned Conjugate Gradient (PCG) method is well-established for solving linear equations. Running the PCG method on a hardware accelerator ensures fast and efficient computation. At the same time, each hardware accelerator may be slightly different due to process variability or aging. To handle the variability, a rather pessimistic frequency selection for the whole population of accelerators is often utilized. Increasing the frequency may improve the performance but may also increase the risk of computational errors, affect the convergence of PCG or even corrupt the PCG results. In this paper, we present a method to determine the frequency for each hardware accelerator instance which optimizes the execution time and the energy efficiency of the PCG method. First, a technique is presented to analyze the error resilience of a PCG algorithm to overclocking. Based on the analysis results, we increase the frequency to speed up the convergence while keeping the error rate below the required threshold.

DOI： 10.1109/IOLTS59296.2023.10224885

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Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling 査読有り

Shi S., Holst S., Wen X.

Proceedings 2023 16th IEEE International Symposium on Embedded Multicore Many Core Systems on Chip Mcsoc 2023 501 - 507 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scan shift causes a lot of switching activity in the combinational logic that in turn can lead to high IR-drop. Excessive IR-drop may corrupt test vectors or responses during shifting, leading to test-induced yield-loss. Power-aware X-filling is a widely used method to reduce the overall switching activity during shifting without modifying the scan infrastructure. While such untargeted approaches help reduce the average IR-drop during shifting, some hot-spots of worst-case IR-drop still remain. Through an innovative in-depth IR-drop analysis of high-risk shift cycles, we discovered that these hot-spots are caused by a few High-Impact scan-cell Transitions (HITs). In this paper, we propose to reduce the peak IR-drop during scan shift by using a novel X-filling strategy that (1) identifies HITs through GPU-accelerated IR-drop estimation, and (2) adjusts the X-filling of test vectors to mitigate the remaining worst-case IR-drop hotspots. The results on ITC'99 benchmark circuits demonstrate a 26% peak IR-drop reduction on average without impact on fault coverage or test vector count.

DOI： 10.1109/MCSoC60832.2023.00080

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Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm 査読有り

Lylina N., Holst S., Jafarzadeh H., Kourfali A., Wunderlich H.J.

Proceedings 53rd Annual IEEE IFIP International Conference on Dependable Systems and Networks Workshops Volume Dsn W 2023 195 - 198 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Many applications from Artificial Intelligence (AI) and Scientific Computing rely on efficient algorithms for solving large systems of linear equations. The Preconditioned Conjugate Gradient (PCG) algorithm is a promising option and it is a perfect candidate to be executed on specialized hardware accelerators widely used in AI. Hardware accelerators, like other modern devices, are prone to process variations. A conventional approach to handle the variability is to use pessimistic guardbands for all the devices within the population, which implies that the best and even the average accelerators are slowed down significantly. Since the PCG algorithm is inherently error resilient to some extent, it may also tolerate an error rate increase due to overclocking. On another side, increasing the frequency may increase the total execution time if more arithmetic operations are needed until the convergence. This paper presents a method to ensure efficient computing on each hardware accelerator instance running the PCG algorithm. A cross-layer approach identifies an optimized frequency that minimizes the total time to complete the PCG algorithm. Simple high-level checks ensure the quality of the solution. Experimental results validate the feasibility of the developed approach for large systems of linear equations.

DOI： 10.1109/DSN-W58399.2023.00054

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Evaluation and Test of Production Defects in Hardened Latches 査読有り国際誌

Ma R., Holst S., Wen X., Yan A., Xu H.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E105D ( 5 ) 996 - 1009 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (PTVF), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed PTVF metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.

DOI： 10.1587/transinf.2021EDP7216

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On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks 査読有り国際誌

Neugebauer F., Holst S., Polian I.

Proceedings of the European Test Workshop 2022-May 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Stochastic computing (SC) with its stream-based, probabilistic number representation promises large area and power benefits as well as increased error tolerance compared to conventional binary computing. While SC is less precise, it is considered a promising option for implementing neural network inferencing in ultra-low-power edge devices. SC-based Neural Networks (SCNNs) typically combine stochastic and binary components for interfacing and to alleviate certain SC limitations. Moreover, ultra-low-power VLSI for edge computing is often less reliable due to noisy environments or deliberate power-reliability trade-offs. In this work, we present the first detailed investigation of the behavior of an SCNN and its individual components on hardware prone to timing errors. Our results show that robustness of SC is highly dependent on specific design choices and that biases in the error distributions may even cause SCNNs to perform worse under certain circumstances than comparable binary implementations. It shows that robustness should be treated as a design goal in SC rather than taken for granted.

DOI： 10.1109/ETS54262.2022.9810429

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Power and Energy Safe Real-Time Multi-Core Task Scheduling 査読有り

Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 16 - 21 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scheduling tasks in multi-core real-time systems (e.g. low power devices/appliances) while keeping energy in mind is a difficult design challenge. Extensive work has been done to overcome this issue, in which task instances (jobs) have varying levels of operation power. Different combinations of system energy (SE) and subsequent minimal SE have been attained based on the power levels. However, both system power (SP) and system energy (SE) are expensive to operate. As a result, task scheduling for multi-core systems based on balancing both the SP and the SE (referred to as feasible SP and feasible SE, respectively) to achieve the lowest system cost is an issue that has not been adequately addressed in the literature. The states or zones of feasible SP (FSP) and feasible SE (FSE) are thought to be possible zones/states of the system where the system's power configuration provides lowered SE with increased job accommodation, lowering the system's cost. We offer a unique scheduling approach in which we identify numerous FSP and FSE zones (feasible zones/states) to fit all jobs to cores while minimising system cost (including optimum cost) and meeting deadlines. By giving weights to the FSP and FSE, we present a mechanism for ranking the many viable system states. The model is tested using produced task sets (low power task sets), and the results reveal that our approach effectively finds feasible zones, including the best one.

DOI： 10.1109/VLSID2022.2022.00016

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On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption 査読有り国際誌

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E104D ( 6 ) 816 - 827 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

DOI： 10.1587/transinf.2020EDP7042

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GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators 査読有り国際誌

Holst S., Bumun L., Wen X.

Proceedings of the Asian Test Symposium 2021-November 127 - 132 2021年01月

担当区分：筆頭著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Systolic arrays are currently used in autonomous systems such as self-driving cars to accelerate the enormous amount of matrix operations necessary for DNN inference. The reliability of such accelerators are of utmost importance since any loss in DNN accuracy due to erroneous calculations can have dire consequences. We propose a novel method to measure accuracy losses caused by arbitrary timing faults in systolic arrays. Our GPU-based simulation system enables for the first time a complete and accurate timing simulation of all inference-related matrix operations on large systolic arrays. A single consumer-grade GPU can simulate a LeNet-5 at a throughput of about 13s per inference. Furthermore, our simulation approach readily scales to larger DNNs and multiple GPUs.

DOI： 10.1109/ATS52891.2021.00034

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Logic Fault Diagnosis of Hidden Delay Defects 査読有り

Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

Proceedings - International Test Conference 2020-November 2020年11月

担当区分：筆頭著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

DOI： 10.1109/ITC44778.2020.9325234

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Targeted partial-shift for mitigating shift switching activity hot-spots during scan test 査読有り

Holst S., Shi S., Wen X.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2019-December 124 - 129 2019年12月

担当区分：筆頭著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

DOI： 10.1109/PRDC47002.2019.00042

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Variation-aware small delay fault diagnosis on compressed test responses 査読有り

Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings - International Test Conference 2019-November 2019年11月

担当区分：筆頭著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

DOI： 10.1109/ITC44170.2019.9000143

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A fault-tolerant MPSoC for CubeSats 査読有り

Fuchs C.M., Chou P., Wen X., Murillo N.M., Furano G., Holst S., Tavoularis A., Lu S.K., Plaat A., Marinis K.

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 2019年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

DOI： 10.1109/DFT.2019.8875417

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STAHL: A novel scan-test-aware hardened latch design 査読有り

Ma R., Holst S., Wen X., Yan A., Xu H.

Proceedings of the European Test Symposium 2019-May 2019年05月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Germany Baden-Baden

As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulner-ability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode.

DOI： 10.1109/ETS.2019.8791544

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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing 査読有り国際誌

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. High scan shift power often leads to excessive heat as well as shift timing failures. Partial shift (shifting a subset of scan chains at a time) is a widely adopted approach for avoiding excessive heat by reducing global switching activity, we show for the first time that it may actually cause excessive IR-drop on some clock buffers and worsen shift clock skews, thus increasing the risk of shift timing failures. This paper addresses this problem with an innovative method, namely Clock-Skew-Aware Scan Chain Grouping (CSA-SCG). CSA-SCG properly groups scan chains to be shifted simultaneously so as to reduce the imbalance of switching activity around the clock paths for neighboring scan flip-flops in scan chains. Experiments on large ITC'99 benchmark circuits demonstrate the effectiveness of CSA-SCG for reducing scan shift clock skews to lower the risk of shift timing failures in partial shift.

DOI： 10.1109/ATS.2018.00037

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