研究者詳細 - HOLST Stefan

論文 - HOLST Stefan

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The impact of production defects on the soft-error tolerance of hardened latches 査読有り国際誌

Holst S., Ma R., Wen X.

Proceedings of the European Test Symposium 2018-May 1 - 6 2018年06月

担当区分：筆頭著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Germany Bremen

© 2018 IEEE. As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces the test coverage of cell-internal production defects. Moreover, the test escapes reduce the soft-error tolerance of the defective latches. This work introduces a new soft-error vulnerability metric called Post Test Vulnerability Factor that correctly measures the added vulnerability to transiant frults such as particle strikes caused by undiscovered production defects within hardened latches.

DOI： 10.1109/ETS.2018.8400694

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Scan chain grouping for mitigating ir-drop-induced test data corruption 査読有り国際誌

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

Proceedings of the Asian Test Symposium Part F134421 140 - 145 2018年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2017 IEEE. Loading and unloading test patterns during scan testing causes many scan flip-flops to trigger simultaneously. This instantaneous switching activity during shift in turn may cause excessive IR-drop that can disrupt the states of some scan flip-flops and corrupt test stimuli or responses. A common design technique to even out these instantaneous power surges is to design multiple scan chains and shift only a group of the scan chains at a same time. This paper introduces a novel algorithm to optimally group scan chains so as to minimize the probability of test data corruption caused by excessive instantaneous IR-drop on scan flip-flops. The experiments show optimal results on all large ITC'99 benchmark circuits.

DOI： 10.1109/ATS.2017.37

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Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors 査読有り国際誌

Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

IEEE International Test Conference 2017-December 1 - 8 2017年10月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

United States Fort Worth 2017年10月31日 - 2017年11月02日

Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases of test data corruption are mitigated in a non-intrusive way by selective test data manipulation and masking of affected responses. Evaluation results show the computational feasibility of our method for large benchmark circuits, and demonstrate that a few targeted pattern changes provide large potential gains in shift safety and test time with negligible cost in fault coverage.

DOI： 10.1109/TEST.2017.8242055

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GPU-Accelerated Simulation of Small Delay Faults 査読有り国際誌

Schneider E., Kochte M., Holst S., Wen X., Wunderlich H.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 ( 5 ) 829 - 841 2017年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE. Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs toward even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this paper, we present a method for fast and waveform-accurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms, and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.

DOI： 10.1109/TCAD.2016.2598560

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Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test 査読有り国際誌

Eggersglub S., Eggersglub S., Holst S., Tille D., Miyase K., Wen X.

Proceedings of the Asian Test Symposium 173 - 178 2016年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2016 IEEE. Launch-Switching-Activity (LSA) is a serious problem during at-speed testing of integrated circuits, since localized LSA may lead to severe IR-drop and thus failures. The excessive LSA is conventionally mitigated by reducing the switching activity through special low-power test generation techniques, typically resulting in severe test pattern inflation and high test costs. This work introduces a novel concept of Low-Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power (HCP) regions. LCP-TPs also help in retaining high test compaction capability. An optimization- SAT based procedure is proposed to compute a small set of optimal LCP-TP locations for compact at-speed test sets with effective capture power reduction. Experimental results clearly demonstrate the advantages of LCP-TP insertion.

DOI： 10.1109/ATS.2016.41

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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test 査読有り国際誌

Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.

Proceedings of the Asian Test Symposium 19 - 24 2016年12月

担当区分：筆頭著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2016 IEEE. IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.

DOI： 10.1109/ATS.2016.49

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Logic-path-and-clock-path-aware at-speed scan test generation 査読有り国際誌

Li F., Wen X., Miyase K., Holst S., Kajihara S.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人電子情報通信学会 ) E99A ( 12 ) 2310 - 2319 2016年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power- safety without significant test vector count inflation and test quality loss.

DOI： 10.1587/transfun.E99.A.2310

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Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch 査読有り国際誌

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

IEEE Asian Test Symposium 2016-February 103 - 108 2015年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

India Mumbai 2015年11月22日 - 2015年11月25日

IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.

DOI： 10.1109/ATS.2015.25

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High-Throughput Logic Timing Simulation on GPGPUs 査読有り国際誌

S. Holst, M. E. Imhof, H.-J. Wunderlich

ACM Transactions on Design Automation of Electronic Systems 20 ( 3 ) Article No. 37 2015年06月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

Many EDA tasks such as test set characterization or the precise estimation of power consumption, power droop and temperature development, require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. The new simulation system presented here is able to accelerate such tasks by more than two orders of magnitude and provides for the first time fast and comprehensive timing simulations for industrialsized designs. Hazards, pulse-filtering, and pin-to-pin delay are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more realistic delay models and further applications. A sophisticated mapping with efficient memory utilization and access patterns as well as minimal synchronizations and control flow divergence is able to use the full potential of GPGPU architectures. To provide such a mapping, we combine for the first time the versatility of event-based timing simulation and multidimensional parallelism used in GPU-based gate-level simulators. The result is a throughput-optimized timing simulation algorithm, which runs many simulation instances in parallel and at the same time fully exploits gate-parallelism within the circuit.

DOI： 10.1145/2714564

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A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE European Test Symposium 2015年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Romania Cluj-Napoca 2015年05月25日 - 2015年05月29日

This paper proposes a novel soft-error tolerant TCAM using partial don't-care keys (X-keys), namely TX, which significantly enhances the tolerance of the TCAM against soft errors. Experimental results show that the soft-error tolerance of the TX outperforms existing schemes. Moreover, the overhead of the TX is very small.

DOI： 10.1109/ETS.2015.7138743

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GPU-Accelerated Small Delay Fault Simulation 査読有り

E. Schneider, S. Holst, M. A. Kochte, X. Wen, H.-J. Wunderlich

Design and Test in Europe 1174 - 1179 2015年03月

GPU-accelerated small delay fault simulation 査読有り国際誌

Schneider E., Holst S., Kochte M., Wen X., Wunderlich H.

Proc. Design, Automation and Test in Europe (DATE) 2015-April 1174 - 1179 2015年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2015 EDAA. The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multimillion gate designs without fault dropping for the first time.

DOI： 10.7873/date.2015.0077

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Soft-Error Tolerant TCAMs for High-Reliability Packet Classifications 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, and K. Miyase

IEEE Asia Pacific Conference on Circuits and Systems 2015-February ( February ) 471 - 474 2014年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Ishigaki 2014年11月17日 - 2014年11月20日

In the internet, packets are classified by source and destination addresses, ports, and protocol type. Ternary content addressable memories (TCAMs) are often used to perform this operation. However, high-reliability packet classifiers in aerospace network applications require soft-error tolerant TCAMs to prevent system from errors caused by environmental factors such as high-energy radiations. This paper shows a soft-error tolerant TCAM (STTCAM), which enhances the reliability of TCAMs for soft-errors. The STTCAM randomly selects a search key to be evaluated. Then, parallel TCAMs detect single-bit flip errors. When the search key matches the last word, the STTCAM calculates the similarity of the search key to the TCAM word. If 99% of similarity is detected, then a suspected error is found and the STTCAM refreshes the TCAM words by using a backup ECC-SRAM. Experimental results show that the STTCAM improves TCAMs reliability significantly than the existing scheme. The STTCAM can be easily implemented and is useful for fault-tolerant packet classifiers.

DOI： 10.1109/APCCAS.2014.7032821

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Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り国際誌

E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

International Conference on Computer-Aided Design 2015-January ( January ) 17 - 23 2014年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA San Jose 2014年11月03日 - 2014年11月06日

Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate timesimulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.

DOI： 10.1109/ICCAD.2014.7001324

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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

IEICE Transactions on Information and Systems E97-D ( 10 ) 2706 - 2718 2014年10月

Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures 査読有り

Braun C., Holst S., Wunderlich H., Castillo J., Gross J.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors 207 - 212 2012年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Markov-Chain Monte-Carlo (MCMC) methods are an important class of simulation techniques, which execute a sequence of simulation steps, where each new step depends on the previous ones. Due to this fundamental dependency, MCMC methods are inherently hard to parallelize on any architecture. The upcoming generations of hybrid CPU/GPGPU architectures with their multi-core CPUs and tightly coupled many-core GPGPUs provide new acceleration opportunities especially for MCMC methods, if the new degrees of freedom are exploited correctly. In this paper, the outcomes of an interdisciplinary collaboration are presented, which focused on the parallel mapping of a MCMC molecular simulation from thermodynamics to hybrid CPU/GPGPU computing systems. While the mapping is designed for upcoming hybrid architectures, the implementation of this approach on an NVIDIA Tesla system already leads to a substantial speedup of more than 87x despite the additional communication overheads. © 2012 IEEE.

DOI： 10.1109/ICCD.2012.6378642

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Scan test power simulation on GPGPUs 査読有り

Holst S., Schneider E., Wunderlich H.

Proceedings of the Asian Test Symposium 155 - 160 2012年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models. © 2012 IEEE.

DOI： 10.1109/ATS.2012.23

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Structural Test and Diagnosis for Graceful Degradation of NoC Switches 査読有り

Dalirsani A., Holst S., Elm M., Wunderlich H.

Journal of Electronic Testing: Theory and Applications (JETTA) 28 ( 6 ) 831 - 841 2012年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86 % and 72.42 % of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs. © 2012 Springer Science+Business Media, LLC.

DOI： 10.1007/s10836-012-5329-9

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Embedded test for highly accurate defect localization 査読有り

Mumtaz A., Imhof M., Holst S., Wunderlich H.

Proceedings of the Asian Test Symposium 213 - 218 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Modern diagnosis algorithms are able to identify the defective circuit structure directly from existing fail data without being limited to any specialized fault models. Such algorithms however require test patterns with a high defect coverage, posing a major challenge particularly for embedded testing. In mixed-mode embedded test, a large amount of pseudo-random(PR) patterns are applied prior to deterministic test pattern. Partial Pseudo-Exhaustive Testing (P-PET)replaces these pseudo-random patterns during embedded testing by partial pseudo-exhaustive patterns to test a large portion of a circuit fault-model independently. The overall defect coverage is optimized compared to random testing or deterministic tests using the stuck-at fault model while maintaining a comparable hardware overhead and the same test application time. This work for the first time combines P-PET with a fault model independent diagnosis algorithm and shows that arbitrary defects can be diagnosed on average much more precisely than with standard embedded testing. The results are compared to random pattern testing and deterministic testing targeting stuck-at faults. © 2011 IEEE.

DOI： 10.1109/ATS.2011.60

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Structural test for graceful degradation of NoC switches 査読有り

Dalirsani A., Holst S., Elm M., Wunderlic H.

Proceedings - 16th IEEE European Test Symposium, ETS 2011 183 - 188 2011年08月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is increased at the cost of reduced performability. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions rather than providing only a pass/fail result for the complete switch. The new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects to determine the unaffected switch functions and use partially defective NoC switches. According to the experimental results, this improves the performability of NoCs as more than 61% of defects only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with any switch design. © 2011 IEEE.

DOI： 10.1109/ETS.2011.33

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