担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

The impact of combining epoxy-potting encapsulation with an insulated metal substrate (IMS) on the performance and reliability of SiC MOSFET modules was investigated. Static and dynamic characteristics, thermal resistance, and power cycle tolerance were measured, and a high-temperature bias test and a high-temperature humidity test were carried out. An IMS module with epoxy-potting encapsulation was compared with a conventional ceramic insulated substrate with silicone-gel encapsulation. The IMS module was found to have a higher thermal cycling tolerance, which allowed for a more flexible copper pattern layout. The optimized copper pattern layout enabled reduced conduction loss in the IMS module. In addition, the IMS module exhibited improved power cycling tolerance compared with the conventional ceramic insulated substrate. This improved performance and reliability are expected to contribute to the realization of higher-density power units.

DOI： 10.30420/566262283

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In SiC MOSFETs, the degradation of surge current capability when applying positive gate voltage has become a problem. To suppress the degradation of surge current capability, we conducted TCAD simulation to accurately understand the bipolar operation and heat generation inside the device during surge operation. Based on the results, we experimentally studied the improvement of device design and development of protection circuits. In device design, we showed that appropriate design of current spread resistance can improve surge current capability while minimizing the increase in on-resistance. We also studied protection circuits for surge operation by gate control and provided new guidelines for appropriate switching current and switching delay time.

DOI： 10.1109/ISPSD59661.2024.10579578

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In a power module with multiple MOSFETs connected in parallel, a type of current oscillation known as 'parasitic oscillation' can occur during switching. Parasitic oscillation can lead to module failure, so a means of mitigating parasitic oscillation is required. In this paper, we derived oscillation conditions using the Monte Carlo method as well as theoretical analysis of an equivalent circuit, using a simplified circuit model of two chips connected in parallel. Furthermore, we showed that it is possible to apply the oscillation condition to any number of parallel chips by considering them to be equivalent to a two-chip model by performing an appropriate equivalent-circuit transformation. According to these conditions, increasing the value of Lg/Lsis effective for mitigating parasitic oscillation. To verify the above considerations, we fabricated power modules with different L g/L svalues and performed switching measurements. The results revealed that the module with higher L g/L svalues mitigated oscillation without increasing switching loss. This novel approach might be useful in designing the wiring structure of power modules.

DOI： 10.1109/ISPSD59661.2024.10579559

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

When power semiconductor modules are connected in parallel, the switching characteristics and current imbalance of each device need to be aligned. This paper focuses on the mutual inductance between the gate driver and the main circuit and the stray inductance of the main circuit when a silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) module with a rating of 3.3 kV/800 A is operated in parallel, to examine the effect on the switching operation and describe the optimum method. First, the effect of mutual inductance between the gate wiring of devices in parallel and the main circuit was evaluated by performing actual measurements, and it was shown that gate voltage fluctuations could be suppressed by bringing the gate wiring of each device closer together. Next, when an external capacitor Cgs was inserted as a gate-noise countermeasure, it was shown that reducing the loop between the main circuit and the capacitor could decrease the mutual inductance and lessen the difference in switching characteristics. Finally, the difference in stray inductance of the main circuit of each device was evaluated. Differences in stray inductance of the main circuit cause current imbalance, resulting in differences in the loss of each device. As a result, there is a difference in the thermal fatigue life of each device, and the expected life of the system is shorter than anticipated. It is therefore important to match stray inductances of the main circuits within the range where turn-off surges are allowed.

DOI： 10.30420/566262284

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

The device structure of SBD-embedded MOSFET was investigated and the complicated tradeoff relationship of on-state resistance, short-circuit ruggedness, and diode conduction capability was improved. TCAD analysis indicated that bipolar conduction in body diode of MOSFET with deep p-shield can be suppressed by developing current spreading layer structure. The fabricated devices demonstrated adequate ruggedness in short-circuit operation and unipolar conduction capability in diode operation while obtaining low on-state resistance. The reduction in leakage by the developed structure enabled drift layer tuning and finally low on-resistance of 2.0 mΩ-cm2was demonstrated.

DOI： 10.1109/ISPSD59661.2024.10579582

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In SBD-embedded SiC MOSFETs, we attempted to improve the surge current capability while suppressing the bipolar operation that causes long-term reliability problems. By incorporating trigger p-n diodes that induce conductivity modulation, we expected that higher current could flow with a low voltage and the surge current capability would be improved. The effectiveness of the trigger diode was confirmed by preliminary TCAD simulation, and SBD-embedded SiC MOSFETs with trigger diodes were fabricated. By placing SBDs in the trigger diode region at the same intervals as in the cell region, maximum current density without bipolar operation was maintained. By distributing 3 to 4 adjacent trigger diodes over the entire chip, the conductivity modulation and heat generation were spread out over the entire chip, and the surge current capability was improved by 1.43 times compared with an SBD-embedded SiC MOSFET without trigger diodes.

DOI： 10.1109/ISPSD57135.2023.10147726

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

2200 V Schottky barrier diode (SBD)-embedded silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with optimization of the chip design for the drift layer and cell structure. The developed SiC MOSFETs not only suppressed bipolar operation but also achieved low on-resistance and a sufficiently high blocking voltage. We examined the effect of two-level 2200 V SiC MOSFET circuits on the conversion efficiency of a power converter specifically for photovoltaic systems. The power loss was reduced by 37% compared with three-level circuits composed of Si insulated-gate bipolar transistors (IGBTs).

DOI： 10.30420/566091078

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

The oscillation phenomenon of trench-type insulated gate bipolar transistors during short-circuit (SC) type II was investigated experimentally and theoretically. The gate resistance required to suppress oscillations decreased with an increasing collector voltage. The oscillation conditions were calculated from the signal flow graph model using the S-parameter based on a technology computer-aided design simulation. The calculation results reproduced the locus of the collector voltage dependence of the experimentally measured gate resistance. The oscillation mechanism was investigated using the device simulation. The response of carrier density modulation at the base-drift layer boundary was found to transmit to the collector side through the electron-hole plasma region during the oscillation, indicating that the transfer characteristics of the carrier density modulation in the drift region at the specific collector voltage influence the collector voltage dependence of the SC oscillation. The influence of circuit parameters on the oscillation was also investigated. An increase in the emitter inductance suppressed the oscillations, whereas an increase in gate inductance increases oscillations.

DOI： 10.1109/TED.2022.3202883

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記述言語：英語   掲載種別：研究論文（学術雑誌）

Schottky barrier diode (SBD)-embedded SiC MOSFETs can clamp the parasitic p-n diode that causes a lack of long-term stability and thus realize high reliability. However, the maximum current density at which the parasitic p-n diode does not operate (Jumax) decreases with increasing temperature. Therefore, further improvement of Jumax} and understanding the mechanism of the temperature dependence of Jumax} are urgent issues. We have developed an equivalent circuit model of SBD-embedded SiC MOSFETs and derived an analytical formula of Jumax. Based on the derived analytical formula of Jumax}, we have proposed guidelines for improving Jumax. Then, utilizing the guidelines, we have tried to improve Jumax experimentally. As a result, Jumax of 3.3 kV SBD-embedded SiC MOSFETs has been improved by 3.8 times. In addition, the mechanisms by which Jumax decreases in high blocking voltage devices and at high temperature have been investigated. We have found that the blocking voltage dependence of Jumax is caused by the change in the current distribution due to the difference in the drift resistance. On the other hand, it has also been confirmed that the decrease in Jumax is not necessarily a problem because the rated current density also decreases in high blocking voltage devices. From the partial differentiation of Jumax 's analytical formula with respect to temperature, it has been clarified that the decrease in Jumax is mainly due to the increase in the spread resistance and the JBS resistance.

DOI： 10.1109/TED.2022.3200917

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

The oscillation phenomenon of trench-type insulated gate bipolar transistors (IGBTs) during short-circuit type II was experimentally investigated. The gate resistance required for oscillation suppression decreased with increasing collector voltage. The oscillation conditions were calculated from the signal flow graph model using the S-parameter based on a technology computer-aided design (TCAD) simulation. The calculation results reproduced the locus of the collector voltage dependence of the gate resistance measured experimentally. The oscillation mechanism was investigated. The response of the discharged carriers at the base-drift layer boundary was found to transmit to the collector side through the electron-hole plasma region during the oscillation. These results indicated that the transfer characteristics of the carrier distribution caused a collector voltage dependence of the short-circuit oscillation conditions.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Toshiba’s third-generation silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) technology was initially developed for 3.3-kV class chips. That chip technology is adopted and optimized for 650-V and 1200-V class products. Compared with second-genera-tion SiC MOSFETs released in 2019 [2], R<inf>on</inf>A is reduced by 43% and R<inf>on</inf> × Q<inf>gd</inf> i s drastically reduced by 80%. In addition, Vth is designed at 4 V to ease gate driving and to prevent malfunctions due to high speed switching. Figure 1 shows a list of third-generation SiC MOSFETs in the 650-V and 1200-V classes that are scheduled for release. In addition, high reliability was realized by optimizing the gate process.

DOI： 10.30420/565822077

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

Schottky barrier diode (SBD) embedded planer gate metal-oxide-semiconductor field effect transistors (MOSFETs) are one of the most promising SiC switching devices owing to their well-established reliability. In this paper, an effective SBD distribution was proposed in order to achieve both low specific on-resistance (RonA) and sufficient diode conduction capability. The proposed checked pattern SBD structure exhibited a superior parasitic body p-n diode clamping effect 2 times better than did the conventional striped SBD pattern. Increased channel density due to small area penalty of embedding the SBD successfully contributed to a low RonA of 2.7 m Omega cm2 for a 1.2 kV-class SBD embedded MOSFET while improving diode conduction capability.

DOI： 10.1109/IEDM45625.2022.10019413

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

A 650-V/10-A-class SiC Schottky barrier diode is demonstrated that has low V<inf>F</inf> of 1.19 V while limiting I<inf>R</inf> to 1.6 μA. This outstanding trade-off is realized by developing the Schottky metal and optimizing the junction barrier structure. The fabricated device exhibits superior temperature stability with a small increase in V<inf>F</inf> under high-temperature operation, although the increase in I<inf>R</inf> is similar to that of conventional devices. No thermal runaway, or degradation of V<inf>F</inf> or I<inf>R</inf> is observed under high-temperature and high-voltage stress. The developed device improves the efficiency of electric energy conversion equipment by 0.1% when used in a power factor correction circuit.

DOI： 10.30420/565822041

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

The impact of cell size and JFET width reduction on static and dynamic device characteristics is investigated in 1.2-kV-class Schottky barrier diode (SBD)-embedded SiC metal-oxide-semiconductor field effect transistors (MOSFETs). We compare a conventional SBD-embedded MOSFET with improved SBD-embedded MOSFETs with smaller cell pitch and JFET width than the conventional SBD-embedded SiC MOSFET. The optimized SBD-embedded SiC MOSFETs achieve 39% lower on-resistance and 16% lower switching energy loss compared with the conventional design. We also investigate the tradeoff between RonA and short-circuit withstand time (tSC). Although RonA reduction generally causes a decrease in short circuit withstand capability and reverse conduction capability, we demonstrate that the optimized SBD-embedded SiC MOSFETs have a lower forward voltage drop and short circuit withstand capability. These results show that it is possible to simultaneously reduce RonA and improve tSC with adequate optimization.

DOI： 10.23919/ISPSD50666.2021.9452314

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

In the SBD-embedded SiC MOSFET, the operation of the parasitic PN diode that causes degradation of forward voltage of the diode is suppressed by the incorporated SBD. The aim of this study is to improve the maximum current at which the parasitic PN diode does not operate (Iumax). We confirmed the limitation of the existing equivalent circuit model used as a guideline to improve Iumax, and then developed a new circuit model. In addition, a new guideline to improve Iumax has been derived based on the equivalent circuit model. Utilizing this guideline, we have tried to improve Iumax of 3.3 kV SBD-embedded SiC MOSFET experimentally. Iumax at 200°C has been improved to 4.72 times that of the conventional device. Though it has been known that Iumax decreases with temperature, this significant improvement in Iumax is a promising result for future application of SBD-embedded SiC MOSFET above 175°C.

DOI： 10.23919/ISPSD50666.2021.9452280

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）

This study presents a novel method to evaluate oscillation condition by technology computer-aided design (TCAD) simulation and is based on a signal flow graph model and a scattering parameter (S-parameter) computed using the TCAD simulation result. The parasitic oscillation of Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) when a short circuit occurs has been investigated with the proposed method. The oscillation conditions of a circuit were computed with this technique and compared with those computed by TCAD transient simulation. The gate resistance to suppress oscillation is similar between these methods. Moreover, the method was also applied to estimate the stability of a circuit consisting of parallelly connected SiC MOSFETs. Two oscillation modes were taken into account. We demonstrated that the circuit parameters required to suppress parasitic oscillation can be computed using a simple calculation.

DOI： 10.1016/j.sse.2020.107884

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担当区分：筆頭著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

A 3.3-kV class third-generation silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) with an optimized cell structure consisting of a Schottky barrier diode (SBD) embedded in a SiC MOSFET is developed. The developed SiC MOSFET not only suppresses bipolar operation but also achieves 19% lower on-resistance compared with conventional SiC MOSFETs. We also develop a low-inductance package named iXPLV, whose stray inductance is reduced by 40% compared with conventional modules. We measure the switching losses of the developed MOSFET assembled in iXPLV and compare it with the switching loss of a silicon (Si) insulated gate bipolar transistor (IGBT) assembled in a conventional module. The switching loss of the developed module is 60% lower than the conventional Si IGBT with Si PiN diode and 43% lower than the Si IGBT with SiC SBD. We also estimate the effect of these loss reductions on the cooling unit volume, and the developed module is found to achieve a heatsink volume reduction of 40% compared with the module with a Si IGBT with Si PiN diode and 59% compared with the module with a Si IGBT with SiC SBD.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

One of the issues of SiC MOSFET is the reliability of its intrinsic body diode when used as a free-wheeling diode (FWD). The reverse current through the SiC MOSFET may cause R<inf>en</inf> degradation over time. A new structure of a SBD-embedded MOSFET has been proposed that prevents the current conduction through its intrinsic body diode. A low R<inf>en</inf>A 1.2kV class SBD-embedded SiC MOSFET has been realized that improves its reliability by optimizing the SBD structure.

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）

The neutron single-event effect (SEE) tolerance of SiC power MOSFETs with different drift region designs was evaluated. The failure rate was found to increase exponentially with increasing drain voltage above a specific SEE threshold voltage, VSEE. Devices with higher avalanche breakdown voltage showed higher SEE threshold voltage. The neutron SEE tolerance of MOSFETs and PiN diodes with the same epitaxial structure was also evaluated. There was no significant difference in neutron SEE tolerance between these devices.

DOI： 10.4028/www.scientific.net/MSF.963.738

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