MIYASE Kouhei

写真a

Title

Associate Professor

Laboratory

680-4 Kawazu, Iizuka-shi, Fukuoka

Research Fields, Keywords

LSI Testing,ATPG,Low Power Testing,Fault Diagnosis, Motion analysis for sports

Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 8

Citation count denotes the number of citations in papers published for a particular year.

Undergraduate Education 【 display / non-display

  • 2002.03   Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Computer Science and Electronics   Graduated   JAPAN

Post Graduate Education 【 display / non-display

  • 2005.03  Kyushu Institute of Technology  Graduate School, Division of Information Engineering  Doctoral Program  Completed  JAPAN

Degree 【 display / non-display

  • Kyushu Institute of Technology -  Doctor of Information Engineering  2005.03

Biography in Kyutech 【 display / non-display

  • 2019.04
    -
    Now

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Associate Professor  

  • 2016.04
    -
    2019.03

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Creative Informatics   Associate Professor  

  • 2014.04
    -
    2016.03

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Creative Informatics   Assistant Professor  

  • 2008.04
    -
    2014.03

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Electronics   Assistant Professor  

  • 2007.04
    -
    2008.03

    Kyushu Institute of TechnologySchool of Computer Science and Systems Engineering   Assistant Professor  

Biography before Kyutech 【 display / non-display

  • 2005.04
    -
    2007.03

      Researcher   JAPAN

Academic Society Memberships 【 display / non-display

  • 2007.04
    -
    Now
     

    The Institute of Electronics, Information and Communication Engineers  JAPAN

  • 2007.04
    -
    Now
     

    Information Processing Society of Japan  JAPAN

  • 2007.04
    -
    Now
     

    The Institute of Electrical and Electronics Engineers, Inc.  UNITED STATES

Specialized Field (scientific research fund) 【 display / non-display

  • Computer system

 

Research Career 【 display / non-display

  • On Application of Test Relaxation of Test Vectors

    LSI Testing,ATPG,X-Identification,Low Power Testing,Fault Diagnosis  

    Project Year: 2007.04  -  Now 

Publications (Article) 【 display / non-display

  • On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    IEICE Transactions on Information and Systems    E104D ( 6 ) 816 - 827   2021.01  [Refereed]

     View Summary

    Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

    DOI Scopus

  • Fault-Aware Dependability Enhancement Techniques for Phase Change Memory

    Lu S.K., Li H.P., Miyase K., Hsu C.L., Sun C.T.

    Journal of Electronic Testing: Theory and Applications (JETTA)      2021.01  [Refereed]

     View Summary

    A variety of resistive memories have been proposed in recent years. Among these emerging technologies, phase change memory (PCM) has received the most research attentions since it has the advantages of high scalability, non-volatility, fast access, strong data retention, low cost, and low power consumption. It is also considered as the most promising alternative of DRAM. In order to conquer the inevitable endurance problem of PCM cells which causes serious reliability and yield threats, hard repair and ECC (Error correction code) techniques are widely adopted. However, since soft errors are not a main threat for PCM, incorporating ECC for each data word is not a cost-effective technique since a lot of memory space is required for storing the check bits. In this paper, the progressive ECC techniques including the local progressive ECC (LPE) technique and the global progressive ECC (GPE) technique are proposed to solve this dilemma. The key innovation is to equip ECC for a data word when its first faulty cell is detected. In other words, we only equip fault detection code for data words such that the original code rate can be increased significantly. An ECC DRAM and an ECC CAM are used for storing check bits and accessing purposes, respectively. Hardware architectures for implementing the proposed GPE and LPE techniques are also provided. A simulator is developed for evaluating repair rate, reliability, yield, and hardware overhead. According to experimental results, the degradation of repair rate and reliability are almost negligible. However, the hardware overhead is at least 80% lower than the original ECC technique while maintaining the original reliability and yield levels.

    DOI Scopus

  • Probability of Switching Activity to Locate Hotspots in Logic Circuits

    Ryo Oba, Kohei Miyase, Ryu Hoshino, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

    IEEE Workshop on RTL and High Level Testing       2020.11  [Refereed]

    Virtual Workshop 

  • Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments

    Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

    IEEE Transactions on Aerospace and Electronic Systems    56 ( 2 ) 1163 - 1171   2020.04  [Refereed]

     View Summary

    © 1965-2011 IEEE. In harsh radiation environments, nanoscale CMOS latches have become more and more vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm CMOS technology. The proposed latch is mainly constructed from seven mutually feeding-back soft-error-interceptive modules (SIMs), any of which consists of two three-input C-elements and one two-input C-element. Due to the mutual feedback mechanism of SIMs and the dual-level soft-error interception of each SIM, the latch can self-recover from any possible TNU. Simulation results demonstrate the TNU self-recoverability from any key TNU for the proposed latch using redundant silicon area. Furthermore, using a high-speed path, the proposed latch saves about 95.45% transmission delay and 86.97% delay-power-area product, compared with the state-of-the-art TNU-tolerant latch that cannot provide complete TNU self-recoverability at all.

    DOI Scopus

  • Analyzing running form with acceleration sensor

    Koga C., Miyase K., Tokui M.

    Digest of Technical Papers - IEEE International Conference on Consumer Electronics    2020-January   2020.01  [Refereed]

     View Summary

    © 2020 IEEE. Recently, motion analysis really helps athletes improve their performance. Since the systems of motion analysis are expensive and expertise in biomechanics or kinematics is necessary, it is difficult for athletes themselves to use them. In this work, we propose a motion analysis system with acceleration sensor. The proposed system is inexpensive since the system consists of inexpensive components. Besides, only two devices for analysis are required by concentrating on analyzing the motions of arm swing and foot strike. Experimental results demonstrate that the proposed system is useful for athletes to analyze running form.

    DOI Scopus

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Publications (Books) 【 display / non-display

  • 情報工学基礎実験

    九州工業大学情報工学部情報工学基礎実験運営委員会 ( Joint Work )

    学術図書出版社  2019.09 ISBN: 978-4-7806-0781-9

Conference Prsentations (Oral, Poster) 【 display / non-display

  • メモリのサイズおよび形状に起因するロジック部の高消費電力エリア特定に関する研究

    高藤大輝, 星野龍, 宮瀬紘平, 温暁青, 梶原誠司

    電子情報通信学会技術研究報告, DC2020-72, pp. 18-23  2021.02  -  2021.02 

  • Evaluation of probability of switching activity for each area of logic circuit

    Ryo OBA, Ryu HOSHINO, Kohei MIYASE, Xiaoqing WEN, Seiji KAJIHARA

    (Virtual Workshop)  2020.11  -  2020.11 

  • メモリ搭載LSIに対するロジック部の消費電力解析に関する研究

    児玉優也, 宮瀬紘平, 高藤大輝, 温暁青, 梶原誠司

    電子情報通信学会技術研究報告, vol. 119, no. 420, DC2019-93  2020.02  -  2020.02 

  • LSIの高消費電力エリアに対する信号値遷移制御率向上に関する研究

    史傑, 宮瀬紘平, 温暁青, 梶原誠司

    電子情報通信学会技術研究報告, vol. 119, no. 420, DC2019-94  2020.02  -  2020.02 

  • 加速度センサーを用いたランニングフォームの解析に関する研究

    古賀千裕, ホルストシュテファン, 宮瀬紘平, 得居雅人

    第80回FTC研究会  2019.01  -  2019.01 

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Lectures 【 display / non-display

  • 加速度センサーを用いたアスリートの動作解析

    電子情報通信学会 機能集積情報システム研究会 ( 広島市立大学 サテライトキャンパス )  2020.10.30  電子情報通信学会・ディペンダブルコンピューティング研究専門委員会

  • Post-ATPG Test Modification

    Kolloquium Universitat Passau Fakultat fur Informatik und Mathematik   2012.05.25  Universitat Passau Fakultat fur Informatik und Mathematik

  • LSIの消費電力テスト

    日本大学生産工学部数理情報工学科 ( 千葉県習志野市 )  2010.10.22  日本大学生産工学部数理情報工学科

Contracts 【 display / non-display

  • High Dependable Design and Test Techniques for SoC including Embedded Flash Memory

    Other joint research

    Project Year:  2017.08  -  2018.03

  • High-Accuracy Power/Noise-Aware Test Generation

    Joint research

    Project Year:  2008.07  -  2009.03

 

Activities of Academic societies and Committees 【 display / non-display

  • 2021.03
    -
    2023.01

    The Institute of Electrical and Electronics Engineers, Inc.   Asia and South Pacific Design Automation Conference 2021, Publication co-chair

  • 2020.02
    -
    Now

    The Institute of Electrical and Electronics Engineers, Inc.   IEEE Fukuoka Chapter CAS Treasurer/Secretary

  • 2019.07
    -
    2020.01

    The Institute of Electrical and Electronics Engineers, Inc.   Asia and South Pacific Design Automation Conference 2020, TPC chair

  • 2019.03
    -
    2021.11

    The Institute of Electrical and Electronics Engineers, Inc.   IEEE Asian Test Symposium (2021) Secretary

  • 2019.03
    -
    2021.01

    The Institute of Electrical and Electronics Engineers, Inc.   Asia and South Pacific Design Automation Conference 2021, Publication co-chair

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