Faculty Profiles - MIYASE Kouhei

Papers - MIYASE Kouhei

Division display >> ／ All the affair displays1 - 72 of about 72

Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories Reviewed International journal

Lu S.K., Tseng S.C., Miyase K.

Proceedings - International Test Conference 2022-September 391 - 399 2022.09

A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications Reviewed International journal

Ioki K., Kai Y., Miyase K., Kajihara S.

Proceedings - International Test Conference 2022-September 63 - 72 2022.09

Fault Resilience Techniques for Flash Memory of DNN Accelerators Reviewed International journal

Lu S.K., Wu Y.S., Hong J.H., Miyase K.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 1 - 6 2022.08

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits Reviewed International journal

Utsunomiya T., Hoshino R., Miyase K., Lu S.K., Wen X., Kajihara S.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 43 - 48 2022.08

Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories Reviewed International journal

Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase and Xin Dung

Digest. of IEEE Workshop on RTL and High Level Testing ( Digest. of IEEE Workshop on RTL and High Level Testing ) Session 3-1 2021.11

Evaluation of Power Consumption with Logic Simulation and Placement Information for At-Speed Testing Reviewed International journal

Taiki Utsunomiya, Kohei Miyase, Ryu Hoshino, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

Digest. of IEEE Workshop on RTL and High Level Testing ( Digest. of IEEE Workshop on RTL and High Level Testing ) Session 2-2 2021.11

On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption Reviewed International journal

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems E104D ( 6 ) 816 - 827 2021.01

Fault-Aware Dependability Enhancement Techniques for Phase Change Memory Reviewed International journal

Lu S.K., Li H.P., Miyase K., Hsu C.L., Sun C.T.

Journal of Electronic Testing: Theory and Applications (JETTA) 2021.01

Probability of Switching Activity to Locate Hotspots in Logic Circuits Reviewed International journal

Ryo Oba, Kohei Miyase, Ryu Hoshino, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

IEEE Workshop on RTL and High Level Testing 2020.11

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments Reviewed

Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 2 ) 1163 - 1171 2020.04

Analyzing running form with acceleration sensor Reviewed

Koga C., Miyase K., Tokui M.

Digest of Technical Papers - IEEE International Conference on Consumer Electronics 2020-January 2020.01

A static method for analyzing hotspot distribution on the LSI Reviewed

Miyase K., Kawano Y., Lu S.K., Wen X., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 73 - 78 2019.09

Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM Reviewed

Lu S., Huang H., Hsu C., Sun C., Miyase K.

Journal of Electronic Testing: Theory and Applications (JETTA) 35 ( 4 ) 485 - 495 2019.08

Scrubbing-Based Reliability and Yield Enhancement Techniques for Flash Memory Reviewed International journal

S. K. Lu, W. C. Tsai, C. L. Hsu, C. T. Sun, and K. Miyase

Int'l Conf. on Advanced Technology Innovation 2019.07

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018.12

Progressive ECC Techniques for Phase Change Memory Reviewed

Lu S., Li H., Miyase K.

Proceedings of the Asian Test Symposium 2018-October 161 - 166 2018.12

Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory Reviewed

226 - 227 2018.09

Scan chain grouping for mitigating ir-drop-induced test data corruption Reviewed

140 - 145 2018.01

Analysis and mitigation or IR-Drop induced scan shift-errors Reviewed

2017-December 1 - 8 2017.12

Locating Hot Spot with Justification Techniques in a Layout Design Reviewed

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing 2017.11

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test Reviewed

173 - 178 2016.12

On Optimal Power-Aware Path Sensitization Reviewed

179 - 184 2016.12

Logic-path-and-clock-path-aware at-speed scan test generation Reviewed

E99A ( 12 ) 2310 - 2319 2016.12

SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation "jointly worked" Reviewed

Stephan Eggersgluss, Kohei Miyase, Xiaoqing Wen

European Test Symposium 2016.05

Logic/Clock-Path-Aware AtSpeed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch "jointly worked" Reviewed

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

Proc. Asian Test Symposium 1 - 6 Session 4A. 2015.11

A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys "jointly worked" Reviewed

Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase

European Test Symposium Poster Session #2 2015.05

Identification of High Power Consuming Areas with Gate Type and Logic Level Information "jointly worked" Reviewed

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Proc. European Test Symposium 1 - 6 Paper9.1-1 2015.05

Soft-error tolerant TCAMs for high-reliability packet classifications "jointly worked" Reviewed

Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase

2014 IEEE Asia Pacific Conference on Circuits and Systems 471 - 474 2014.11

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST "jointly worked" Reviewed

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

IEICE Transactions on Information and Systems 97-D ( 10 ) 2706 - 2718 2014.10

Search Space Reduction for Low-Power Test Generation "jointly worked" Reviewed

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Asian Test Symposium 171 - 176 2013.11

Scan-Out Power Reduction for Logic BIST "jointly worked" Reviewed

Senling Wang, Yasuo SATO, Seiji Kajihara, Kohei Miyase

IEICE Transactions on Information and Systems E96-D ( 9 ) 2012 - 2020 2013.09

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing "jointly worked" Reviewed

Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara

IEICE Transactions on Information and Systems E96-D ( 9 ) 2003 - 2011 2013.09

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing "jointly worked" Reviewed

Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte

IEEE Design & Test 30 ( 4 ) 60 - 70 2013.07

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression Reviewed

Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang

26th Intl. Conf. on VLSI Design 279 - 284 2013.01

A scan-out power reduction method for multi-cycle BIST Reviewed

272 - 277 2012.12

Estimating the number of Don't-Care Bits in Test Vectors "jointly worked" Reviewed

Kohei Miyase, Seiji Kajihara, Xiaoqing Wen

IEEE Workshop on RTL and High Level Testing 2012.11

On Pinpoint Capture Power Management in At-Speed Scan Test Generation Reviewed

Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

International Test Conference Paper 6.1 2012.11

Low Power BIST for Scan-Shift and Capture Power "jointly worked" Reviewed

Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara

Asian Test Symposium 173 - 178 2012.11

A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits "jointly worked" Reviewed

[28] Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara

VLSI Test Symposium 197 - 202 2012.04

Additional Path Delay Fault Detection with Adaptive Test Data "jointly worked" Reviewed

Kohei Miyase, Hiroaki Tanaka, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara

IEEE Workshop on RTL and High Level Testing 2011.11

Power-Aware Test Pattern Generation for At-Speed LOS Testing, "jointly worked" Reviewed

Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen

Asian Test Symposium 506 - 510 2011.11

Efficient BDD-based Fault Simulation in Presence of Unknown Values "jointly worked" Reviewed

Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich

Asian Test Symposium 383 - 388 2011.11

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling, "jointly worked" Reviewed

Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel

Asian Test Symposium 90 - 95 2011.11

A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing, "jointly worked" Reviewed

Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang

International Test Conference Paper 12.1 Paper 12.1 2011.09

SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures, "jointly worked" Reviewed

Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich

International Symposium on Low Power Electronics and Design 33 - 38 2011.08

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing, "jointly worked" Reviewed

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

IEICE Transactions on Information and Systems E94-D ( 6 ) 1216 - 1226 2011.06

Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme "jointly worked" Reviewed

F. Wu, L.. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen

IEEE International Workshop on Impact of Low-Power design on Test and Reliability 2011.05

Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing, "jointly worked" Reviewed

Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor

29th IEEE VLSI Test Symposium 166 - 171 2011.05

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing, "jointly worked" Reviewed

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

IEICE Transactions on Information and Systems E94-D ( 4 ) 833 - 840 2011.04

Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation Reviewed

Kohei Miyase,Xiaoqing Wen,Masao Aso,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara

Design Automation and Test in Europe 895 - 898 2011.03

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme "jointly worked" Reviewed

Kohei Miyase, F. Wu, L. Dilillo, A. Bosio, P. Girard, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing 2010.12

Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver "jointly worked" Reviewed

Kohei Miyase, Michael A. Kochte, Xiaoqing Wen, Seiji Kajihara, Hans-Joachim Wunderlich

IEEE International Workshop on Defect and Data Driven Testing 2010.11

On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test Reviewed

Seiji Kajihara,Makoto Matsuzono,Hisato Yamaguchi,Yasuo Sato,Kohei Miyase,Xiaoqing Wen

International Symposium on Communications and Information Technologies 723 - 726 2010.10

On Delay Test Quality for Test Cubes Reviewed

Shinji Oku,Seiji Kajihara,Yasuo Sato,Kohei Miyase,Xiqoqing Wen

IPSJ Transactions on System LSI Design Methodology 3 283 - 291 2010.08

A Study of Capture-Safe Test Generation Flow for At- Speed Testing Reviewed

Kohei Miyase,Xiaoqing Wen,Seiji Kajihara,Yuta Yamato,Atsushi Takashima,Hiroshi Furukawa,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Kewal K. Saluja

IEICE Transactions on Fundamentals of Electronics E93-A ( 7 ) 1309 - 1318 2010.07

Power Reduction Through X-filling of Transition Fault Test Vector for LOS Testing "jointly worked" Reviewed

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

International Workshop on the impact of Low-Power Design on Test and Reliability 2010.05

CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing Reviewed

X. Wen, K. Enokimoto, K. Miyase, S. Kajihara, M. Aso, and H. Furukawa

Symp. II (ISTC/CSTIC): Metrology, Reliability and Testing 197 - 202 2010.03

High Launch Switching Activity Reduction in At- Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Reviewed

Kohei Miyase,Xiaoqing Wen,Hiroshi Furukawa,Yuta Yamato,Seiji Kajihara,Patrick Girard,Laung-Terng Wang,Mohammad Tehranipoor

IEICE Transactions on Information and Systems E93-D ( 1 ) 2 - 9 2010.01

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-Speed Scan Testing Reviewed

Yuta Yamato,Xiaoqing Wen,Kohei Miyase,Hiroshi Furukawa,Seiji Kajihara

IEEE 15th Pacific Rim International Symposium on Dependable Computing 81 - 86 2009.11

A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment Reviewed

Kohei Miyase,Yuta Yamato,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Xiaoqing Wen,Seiji Kajihara

International Conference on Computer-Aided Design 97 - 104 2009.11

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing Reviewed

[17]Kazunari Enokimoto,Xiaoqing Wen,Yuta Yamato,Kohei Miyase,Hiroaki Sone,Seiji Kajihara,Masao Aso,Hiroshi Furukawa

Asian Test Symposium 99 - 104 2009.11

X-Identification According to Required Distribution for Industrial Circuits "jointly worked" Reviewed

Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara

IEEE Workshop on RTL and High Level Testing 2009.11

Optimizing the Percentage of X-Bits to Reduce Switching Activity "jointly worked" Reviewed

Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara

IEEE International Workshop on Defect and Data Driven Testing 2009.11

Effective IR-drop Reduction in At-speed Scan Testing using Distribution-Controlling X-Identification Reviewed

Kohei Miyase,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Yuta Yamato,Hiroshi Furukawa,Xiaoqing Wen,Seiji Kajihara

International Conference on Computer-Aided Design 52 - 58 2008.11

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing Reviewed

X. Wen,K. Miyase,S. Kajihara,H. Furukawa,Y. Yamato,A. Takashima,K. Noda,H. Ito,K. Hatayama,T. Aikyo,K.K. Saluja

European Test Symposium 55 - 60 2008.05

On Detection of Bridge Defects with Stuck-at Tests Reviewed

Kohei Miyase,Kenta Terashima,Xiaoqing Wen,Seiji Kajihara,Sudhakar M. Reddy

IEICE Transactions on Information and Systems E91 ( 3 ) 683 - 689 2008.03

A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Reviewed

Yuta Yamato,Yusuke Nakamura,Kohei Miyase,Xiaoqing Wen,Seiji Kajihara

IEICE Transactions on Information and Systems E91 ( 3 ) 667 - 674 2008.03

A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing Reviewed

Xiaoqing Wen,Kohei Miyase,Seiji Kajihara,Tatsuya Suzuki,Yuta Yamato,Patrick Girard,Yuji Ohsumi,Laung-Terng Wang

International Test Conference Paper25.1 2007.10

A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set "jointly worked" Reviewed

Kohei Miyase, Xiaoqing. Wen, Seiji. Kajihara, Masahiro Yamamoto, Hiroshi Furukawa

2007 IEEE International Workshop on Current & Defect Based Testing (DBT 2007) 2007.10

A Novel ATPG Method for Capture Power Reduction during Scan Testing Reviewed

Xiaoqing Wen,Seiji Kajihara,Kohei Miyase,Tatsuya Suzuki,Kewal K. Saluja,Laung-Terng Wang,Kozo Kinoshita

IEICE Transactions on Information and Systems E90-D ( 9 ) 1398 - 1405 2007.09

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing Reviewed

Xiaoqing Wen,Kohei Miyase,Tatsuya Suzuki,Seiji Kajihara,Yuji Ohsumi,Kewal K. Saluja

Design Automation Conference 527 - 532 2007.06

A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Reviewed

Yuta Yamato,Yusuke Nakamura,Kohei Miyase,Xiaoqing Wen,Seiji Kajihara

IEICE Transactions on Information and Systems E90 ( 9 ) 1398 - 1405 2007.03

　PREV-NEXT　

<MIYASE Kouhei>

Papers - MIYASE Kouhei