WEN Xiaoqing

写真a

Title

Professor

Laboratory

680-4 Kawazu, Iizuka-shi, Fukuoka

Research Fields, Keywords

LSI Test, Design for Testability, Fault Diagnosis, High-Reliability Design

Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 14

Citation count denotes the number of citations in papers published for a particular year.

Undergraduate Education 【 display / non-display

  • 1986.07   Tsinghua University     Computer Science and Technology   Graduated   CHINA

Post Graduate Education 【 display / non-display

  • 1993.03  Osaka University  Graduate School, Division of Engineering  Applied Physics  Doctoral Program  Completed  JAPAN

  • 1990.03  Hiroshima University  Graduate School, Division of Engineering  Information Engineering  Master's Course  Completed  JAPAN

Degree 【 display / non-display

  • Osaka University -  Doctor of Engineering  1993.03

  • Hiroshima University -  Master of Engineering  1990.03

  • Tsinghua University -  Bachelor of Engineering  1986.07

Biography in Kyutech 【 display / non-display

  • 2019.04
    -
    Now

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Professor  

  • 2017.04
    -
    2019.03

    Kyushu Institute of TechnologyGraduate School of Computer Science and Systems Engineering  

  • 2017.04
    -
    2019.03

    Kyushu Institute of TechnologyFaculty of Computer Science and Systems Engineering  

  • 2013.04
    -
    2017.03

    Kyushu Institute of TechnologyResearch Center for Dependable Integrated Systems   Director  

  • 2012.04
    -
    2013.03

    Kyushu Institute of TechnologyGraduate School of Computer Science and Systems Engineering   Department of Creative Informatics   Department Chair  

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Biography before Kyutech 【 display / non-display

  • 2016.01
    -
    Now

    Universiti Teknologi Malaysia (UTM)   Embedded System Research Laboratory   Asscociate Member   UNITED STATES

  • 1998.01
    -
    2003.12

    SynTest Techniologies, Inc.   Vice President (VP) and Chief Technoilogy Officer (CTO)   UNITED STATES

  • 1995.10
    -
    1996.03

    Department of Eletrical and Computer Engineering University of Wisconsin - Madison   Visiting Researcher   UNITED STATES

  • 1993.09
    -
    1997.12

    Department of Information Engineering Akita University   Lecturer   JAPAN

Academic Society Memberships 【 display / non-display

  • 1989.01
    -
    Now
     

    Institute of Electrical and Electronics Engineers (IEEE)  UNITED STATES

  • 2011.01
    -
    Now
     

    Technical Activity Committee on Power-Aware Testing, TTTC, IEEE Computer Society  UNITED STATES

  • 2007.01
    -
    Now
     

    Asian Subcommittee, IEEE International Test Conference  UNITED STATES

  • 2005.01
    -
    Now
     

    Institute of Electronic, Information and Communication Engineers (IEICE)  JAPAN

  • 2010.02
    -
    Now
     

    Information Processing Society of Japan (IPSJ)  JAPAN

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Specialized Field (scientific research fund) 【 display / non-display

  • Computer system

 

Research Career 【 display / non-display

  • Low-Power LSI Test

    Project Year: 2004.01  -  Now 

  • LSI High Reliability Design

    Project Year: 2014.04  -  Now 

  • LSI Test Generation

    Project Year: 1993.04  -  Now 

  • LSI Design for Testability

    Project Year: 1993.04  -  Now 

  • LSI Fault Diagnosis

    Project Year: 1993.04  -  Now 

Publications (Article) 【 display / non-display

  • A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments

    Yan A., Cao A., Fan Z., Xu Z., Ni T., Girard P., Wen X.

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI      301 - 306   2021.06  [Refereed]

     View Summary

    This paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state (HIS) insensitive latch design, namely QRHIL, for highly robust computing in harsh radiation environments. The latch mainly comprises a 5×5 looped C-element matrix to store values and provide complete 4NU recovery. Owing to the multiple-level error-interception of the 5×5 C-element matrix, the latch can recover from all possible 4NUs; thus, the latch is insensitive to HIS. Simulation results demonstrate the 4NU-recovery of the proposed latch. The results also show that the latch can approximately save 46% D-Q delay and 46% CLK-Q delay owing to the use of a high-speed D-Q path and clock-gating, compared with the state-of-the-art 3NU-recoverable latch (TNURL) that is not 4NU-recoverable.

    DOI Scopus

  • Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

    Yan A., He Z., Zhou J., Cui J., Ni T., Huang Z., Wen X., Girard P.

    Microelectronics Journal    111   2021.05  [Refereed]

     View Summary

    This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

    DOI Scopus

  • A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology

    Ni T., Yang Z., Chang H., Zhang X., Lu L., Yan A., Huang Z., Wen X.

    IEEE Transactions on Emerging Topics in Computing    9 ( 2 ) 724 - 734   2021.04  [Refereed]

     View Summary

    Through-silicon-vias (TSVs) are prone to defects during the manufacturing process, which pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is too great to be ignored, and in order to not use any redundant TSVs, a chain-type time division multiplexing access (TDMA)-based fault tolerance technique is proposed. However, a double-TSV structure is used per group, resulting in a significant TSV hardware overhead under a given large-scaled circuit design. Furthermore, it is impossible for the chain-TDMA scheme to plan the rerouting path for the right-hand-most TSV per group, resulting in a decrease in the repair rate per TSV group as well as in the whole TSV yield. In the proposed technique, we bundle six TSVs per group in a honeycomb pattern and the TSVs on the edges are connected to each other, enhancing the repair rate per group as well as the whole TSV yield. Subsequently, an architecture based on the proposed technique is designed, evaluated, and validated on logic-on-logic 3D IWLS'05 benchmark circuits using 45 nm TSMC technology. The proposed technique is found to reduce the area overhead by 87.95-90.42 percent, compared to the chain-TDMA scheme, which results in a yield of 96.90-99.09 percent.

    DOI Scopus

  • Reliability-Driven Neuromorphic Computing Systems Design

    Xu Q., Wang J., Geng H., Chen S., Wen X.

    Proceedings -Design, Automation and Test in Europe, DATE    2021-February   1586 - 1591   2021.02  [Refereed]

     View Summary

    In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have provided a promising solution to the acceleration of neural networks. However, stuck-at faults (SAFs) in the memristor devices significantly degrade the computing accuracy of NCS. Besides, memristors suffer from process variations, causing the deviation of actual programming resistance from its target resistance. In this paper, we propose a novel reliability-driven design framework for a memristive crossbar-based NCS in combination with general and chip-specific design optimizations. First, we design a general reliability-aware training scheme to enhance the robustness of NCS to SAFs and device variations; a dropout-inspired approach is developed to alleviate the impact of SAFs; a new weighted error function, including cross-entropy error (CEE), the l2-norm of weights, and the sum of squares of first-order derivatives of CEE with respect to weights, is proposed to obtain a smooth error curve, where the effects of variations are suppressed. Second, given the neural network model generated by the reliability-aware training scheme, we exploit chip-specific mapping and retraining to further reduce the computation accuracy loss incurred by SAFs. Experimental results clearly demonstrate that the proposed method can boost the computation accuracy of NCS and improve the NCS robustness.

    DOI Scopus

  • TPDICE and SIM based 4-node-upset completely hardened latch design for highly robust computing in harsh radiation

    Yan A., Ding L., Shan C., Cai H., Chen X., Wei Z., Huang Z., Wen X.

    Proceedings - IEEE International Symposium on Circuits and Systems    2021-May   2021.01  [Refereed]

     View Summary

    Technology scaling and charge-sharing make nano-scale CMOS latches become severely vulnerable to multiple-node upsets (MNUs). This paper proposes a triple-path dual-interlocked-storage-cell (TPDICE) and soft-error interceptive module (SIM) based 4-Node-Upset (4NU) completely hardened latch, namely 4NUHL latch, that can completely tolerate soft errors, such as 4NUs. The latch mainly consists of 2 TPDICEs and a 3-level SIM which comprises six 2-input C-elements. Owing to the single-node-upset self-recoverability and multiple storage nodes of TPDICEs and the soft-error interception capability of the SIM, the latch can provide complete 4NU tolerance. Simulation results demonstrate that the proposed 4NUHL latch is completely 4NU hardened. Furthermore, we use a high-speed path, clock-gating, and a few transistors to reduce overhead of the proposed latch. We compared the proposed latch with state-of-the-art hardened latches in terms of reliability and overhead to demonstrate the advantages of the proposed latch.

    DOI Scopus

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Publications (Books) 【 display / non-display

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 入門編(改訂版)

    温暁青、畠山一実 ( Joint Work )

    日経BPコンサルティング  2020.12 ISBN: 978-4864431361

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 応用編

    温暁青、畠山一実 ( Joint Work )

    日経BPコンサルティング  2019.04 ISBN: 978-4864431309

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 半導体テスト技術者検定3級 問題集

    温暁青、畠山一実 ( Joint Work )

    日経BPコンサルティング  2014.12 ISBN: 978-4-8644-3071-5

  • Chapter 9 "Low-Power Testing for 2D/3D Devices and Systems" in Design of 3D Integrated Circuits and Systems

    Rohit Sharma, et al. ( Joint Work )

    CRC Press  2014.11 ISBN: 9781466589407

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 入門編

    温暁青、畠山一実 ( Joint Work )

    日経BPコンサルティング  2013.05 ISBN: 978-4-8644-3039-5

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Conference Prsentations (Oral, Poster) 【 display / non-display

  • New Test Partition Approach for Rotating Test with Lower Rate

    S. Wang

    第66回 FTC 研究会  (日本 )  2012.01  -  2012.01 

  • 実速度スキャンテストにおける高品質なキャプチャ安全性保障型テスト生成について

    西田優一郎

    第66回 FTC 研究会  (日本 )  2012.01  -  2012.01 

  • テストベクトル変換手法を用いた低消費電力LOS実速度テスト

    宮瀬紘平

    電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング  (日本 )  2011.06  -  2011.06 

  • 実速度スキャンテストベクトルに対する遷移タイミング考慮キャプチャ安全性判定

    情報創成工学専攻, 武田敏秀

    電子情報通信学会技術研究報告  (日本 )  2011.02  -  2011.02 

  • 知識ベースシステムに基づいたLSIテスト不良原因解析について

    情報創成工学専攻, 武田敏秀

    電子情報通信学会技術研究報告  (日本 )  2010.11  -  2010.11 

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Industrial Property 【 display / non-display

  • MULTIPLE-CAPTURE DFT METHOD FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SELF-TEST OR SCAN-TEST

    Industrial Property No 20160512  Unexpectedly No 20160131707  UNITED STATES

    L.-T. Wang, P.-C. Hsu, X. Wen

  • COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL

    Industrial Property No 20130305200  UNITED STATES

    L.-T. WANG, .X. WEN

  • COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL

    Industrial Property No 20120246604  UNITED STATES

    L.-T. WANG, A. Kifli; Augusli, F.-S. Hsu, S.-C. Kao, X. Wen, S.-H. Lin, H.-P. Wang

  • GENERATION DEVICE, CLASSIFICATION METHOD, GENERATION METHOD, AND PROGRAM

    Industrial Property No 20110209024  UNITED STATES

    M.-F. Wu, J.-L. Huang, X. Wen, K. Miyase

  • COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL

    Industrial Property No 20110197171  UNITED STATES

    L.-T. Wang, X. Wen

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Lectures 【 display / non-display

  • LSI Testing: A Core Technology to a Successful Semiconductor Industry

    The 2021 IEEE International Conference on Electron Devices and Applications   2021.08.15 

  • Power-Aware Testing for Low-Power LSI Circuits

    The 9th IEEE International Symposium on Next-Generation Electronicserence   2021.07.10 

  • LSI Testing: A Core Technology to a Successful Semiconductor Industry

    The 2nd IEEE International Conference on Control, Measurement and Instrumentation   2021.01.09 

  • LSI Testing: A Core Technology to a Successful Semiconductor Industry

    The 8th IEEE International Symposium on Next-Generation Electronics   2019.10.09 

  • LSI Test: from Research to Business

    The 18th China Fault Tolerant Computing Conference   2019.08.15 

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Honors and Awards 【 display / non-display

  • Best Paper Award

    2018.08.15     CHINA

    Winner: A. Yan, Y. Ling, J. Cui, Z. Chen, X. Wen

  • Best Paper Award

    2016.11.22    

    Winner: K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian,

  • IEEE Fellow

    2012.01.01     UNITED STATES

    Winner: Xiaoqing Wen

  • Best Paper Award, Institute of Electronics, Information and Communication Engineers (IEICE) / Information and Systems Society (ISS)

    2009.11.26     JAPAN

    Winner: X. Wen,Y. Yamashita,S. Kajihara,L.-T. Wang,K. K. Saluja,K. Kinoshita,K. Miyase,T. Suzuki

  • Best Paper Award

    2007.10.12    

    Winner: X. Wen, Y. Yamato, K. Miyase, S. Kajihara, H. Furukawa, L.-T. Wang, K. K. Saluja, K. Kinoshita

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Grants-in-Aid for Scientific Research 【 display / non-display

  • High-Quality False-Test-Avoidance Test for Next-Generation Low-Power LSI Circuits

    Grant-in-Aid for challenging Exploratory Research

    Project Year:  2015.04  -  2018.03

    Project Number:  15K12003

  • Ultra-Low-Power Built-In Self-Test for LSIs in Implantable Medical Devices

    Grant-in-Aid for Scientific Research(B)

    Project Year:  2013.04  -  2018.03

    Project Number:  25280016

  • Research on Logic Switching Activity Balanced Test for High-Quality Low-Cost LSIs

    Grant-in-Aid for challenging Exploratory Research

    Project Year:  2012.04  -  2015.03

    Project Number:  24650022

  • Power-Adjustment-Based Testing for Next-Generation Low-Power LSI Circuits

    Grant-in-Aid for Scientific Research(B)

    Project Year:  2010.04  -  2013.03

    Project Number:  22300017

  • Test Technology for Avoiding Signal Degradation in Next-Generation LSI Circuis

    Grant-in-Aid for Scientific Research(C)

    Project Year:  2007.04  -  2010.03

    Project Number:  19500047

Contracts 【 display / non-display

  • Advanced Test Technology Development for Realizing Nano-CMOS LSI Circuits

    Consigned research

    Project Year:  2011.04  -  2015.03

  • Yield Improvement Platform for LSI Circuits

    Consigned research

    Project Year:  2007.06  -  2012.03

Other External Funds 【 display / non-display

  • Research on High-Quality LSI Test Methodology based on Checking and Removal of Test Clock Risks

    Project Year:  2015.04  -  2017.03

  • VLSI Automatic Fault Diagnosis System Research and Development

    Offer organization:  Local Government 

    Project Year:  2004.04  -  2005.03

Other Research Activities 【 display / non-display

  • Power-Aware Testing in the Era of IoT

    2020.07
     
     

  • Power-Aware Testing in the Era of IoT

    2019.11
     
     

  • Power-Aware LSI Testing ~ Challenges and Strategies ~

    2019.06
     
     

  • Power-Aware Testing in the Era of IoT

    2018.05
     
     

  • Power-Aware Testing in the Era of IoT

    2018.03
     
     

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Activities of Academic societies and Committees 【 display / non-display

  • 2019.01
    -
    2019.12

    International Conference on VLSI Design (VLSID)   Program Committee Member (2019)

  • 2019.01
    -
    2019.12

    IEEE European Test Symposium (ETS)   Program Committee Member (2019)

  • 2019.01
    -
    2019.12

    International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Program Committee Member (2019)

  • 2018.01
    -
    2018.12

    IEEE Latin-American Test Symposium (LATS)   Regional Publicity Co-Chair (2018)

  • 2018.01
    -
    2018.12

    IEEE Asian Test Symposium (ATS)   Program Committee Co-Chair (2018)

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