Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Creative Informatics   Professor  

Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering   Department of Creative Informatics   Department Chair  

Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering   Professor  

Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering   Associate Professor (as old post name)  

2005.04   Reliability Engineering Association of Japan   Japan

2015.10   Japan Micro-Nano Bubble Society Corporation   Japan

2017.12   日本学術振興会科学研究費委員会   Japan

2017.01   中国自然科学基金委員会   China

2014.04   国立研究開発法人科学技術振興機構「研究成果最適展開支援プログラム」   Japan

2015.04 - 2017.03   国立研究開発法人科学技術振興機構「マッチングプランナープログラム」   Japan

2017.04   国立研究開発法人科学技術振興機構「地域産学バリュープログラム」   Japan

2014.04   国立研究開発法人科学技術振興機構「研究成果最適展開支援プログラム」   Japan

2010.04   国立研究開発法人科学技術振興機構「A-STEP探索タイプ」   Japan

2004.01   IEEE Transactions on Computer-Aided Design   United States

2004.01   IEEE Transactions on VLSI Systems   United States

2004.01   Journal of Electronic Testing: Theory and Applications   United States

2009.01   Journal of Computer Science and Technology   China

2009.01   Indian Journal of VLSI and Electronic System Design   India

2017.01   IEEE International Test Conference in Asia (ITC-Asia)   Others

2017.01   International Conference on Intelligent Green Building and Smart Grid   Others

2016.01   International Doctoral Symposium on Applied Computation and Security Systems (ACSS)   Others

2015.01   IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)   Others

2015.01   IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)   Others

2015.01   International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Others

2014.01   IEEE Asia Pacific Conference on Circuits and Systms (APCCAS)   Others

2014.01   International Conference on VLSI Design (VLSID)   Others

2013.01   IEEE International Reliability Innovations Conference (IRIC)   Others

2013.01   International Conference on Advanced Technologies for Communications (ATC)   Others

2013.01   IEEE Latin-American Test Symposium (LATS)   Others

2012.01   IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Others

2010.06 - 2012.05   Association of Computing Machinery (ACM)   United States

2010.01   IEEE International Conference of Networking, Sensing and Control (ICNSC)   Others

2009.04   Design, Automation and Test in Europe Conference and Exhibition (DATE)   Others

2009.01   IEEE International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR)   Others

2009.01   IEEE/VSI VLSI Design And Test Symposium (VDAT)   Others

2009.01   IEEE International Conference on ASIC (ASICON)   Others

2009.01   IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)   Others

2008.04 - 2010.03   JST シーズ発掘試験査読評価委員会   Japan

2008.01   IEEE International Conference on Computer Design (ICCD)   Others

2008.01   IEEE European Test Symposium (ETS)   Others

2008.01   IEEE International Symposium on Electronic Design, Test and Applications (DFT)   Others

2007.04 - 2011.03   大分県 ＬＳＩクラスター形成推進会議   Japan

2007.01   IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Others

2006.04 - 2009.03   福岡県 FIBA (Fukuoa International Business Association)   Japan

2006.04 - 2007.03   経済産業省 産学連携製造中核人材育成事業   Japan

2006.04 - 2007.03   大分県産業創造機構 Ｈ18年度ジョブカフェモデル事業検討会議   Japan

2006.01   IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   United States

2005.04 - 2006.03   大分県半導体クラスター 未来を担う若い人材の養成（ジョブカフェ）協議会   Japan

2005.04 - 2006.03   経済産業省 平成17年度「半導体電子部品・装置・部材・解析等の製造現場のプロフェッショナル育成事業」   Japan

2005.04 - 2006.03   東アジア経済交流推進機構 ウェハテストビジネス可能性検討委員会   Japan

2004.04 - 2005.03   経済産業省 平成16年度製造現場の中核人材育成ＦＳ調査事業（半導体製造におけるテスト解析テクノロジストの育成）」の評価委員会   Japan

2004.01   Asian and South Pacific Design Automation Conference (ASP-DAC)   United States

2004.01   Design Automation Conference (DAC)   Others

2004.01   IEEE International Symposium on Electronic Design, Test and Applications (DELTA)   Others

2000.01   IEEE Workshop on RTL and High Level Testing (WRTLT)   Others

1997.01 - 1997.12   International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability   Others

1993.01   IEEE Great Lake Symposium on VLSI   Others

1993.01   IEEE International Test Conference (ITC)   United States

1993.01   IEEE Asian Test Symposium (ATS)   Others (Asian region)

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology Reviewed International journal

Yan A., Zhou Z., Ding L., Cui J., Huang Z., Wen X., Girard P.

Proceedings -Design, Automation and Test in Europe, DATE   2023-April   2023.01

Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates Reviewed International journal

Yan A., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland)   11 ( 10 )   2022.05

Evaluation and Test of Production Defects in Hardened Latches Reviewed International journal

MA Ruijun, HOLST Stefan, WEN Xiaoqing, YAN Aibin, XU Hui

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers )   E105D ( 5 )   996 - 1009   2022.01

MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator Reviewed International journal

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wen X.

Proceedings of the 2022 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2022   2022.01

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage Reviewed

Yan A., Dingl L., Zhou Z., Huang Z., Cui J., Girard P., Wen X.

Proceedings of the Asian Test Symposium   2022-November   1 - 6   2022.01

GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators Reviewed International journal

Holst S., Bumun L., Wen X.

Proceedings of the Asian Test Symposium   2021-November   127 - 132   2021.01

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications Reviewed International journal

Yan A., Wei S., Zhang J., Cui J., Song J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   167 - 171   2023.06

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications Reviewed International journal

Yan A., Chang Y., Xiang J., Luo H., Cui J., Huang Z., Ni T., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   293 - 298   2023.06

Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array Reviewed International journal

Chen N., Cheng F., Han C., Jiang J., Wen X.

Tsinghua Science and Technology   28 ( 2 )   330 - 343   2023.04

A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design Reviewed International journal

Yan A., Wei S., Chen Y., Fan Z., Huang Z., Cui J., Girard P., Wen X.

Micromachines   13 ( 11 )   2022.11

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications Reviewed International journal

Yan A., Qian K., Song T., Huang Z., Ni T., Chen Y., Wen X.

Integration   86   22 - 29   2022.09

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology Reviewed International journal

Yan A., Zhou Z., Wei S., Cui J., Zhou Y., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   255 - 260   2022.06

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications Reviewed International journal

Yan A., Chen Y., Song S., Zhai Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   333 - 338   2022.06

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications Reviewed International journal

Yan A., He Z., Xiang J., Cui J., Zhou Y., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   261 - 266   2022.06

A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center Reviewed International journal

Saxena D., Gupta I., Kumar J., Singh A.K., Wen X.

IEEE Systems Journal   16 ( 2 )   3163 - 3174   2022.06

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications Reviewed International journal

Yan A., Xiang J., Cao A., He Z., Cui J., Ni T., Huang Z., Wen X., Girard P.

IEEE Transactions on Device and Materials Reliability   22 ( 2 )   282 - 295   2022.06

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications Reviewed International journal

Yan A., Fan Z., Ding L., Cui J., Huang Z., Wang Q., Zheng H., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems   58 ( 1 )   517 - 529   2022.02

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications Reviewed International journal

Yan A., Qian K., Cui J., Cui N., Huang Z., Wen X., Girard P.

Proceedings of the IEEE VLSI Test Symposium   2022-April   2022.01

Broadcast-TDMA: A Cost-Effective Fault Tolerance Method for TSV Lifetime Reliability Enhancement Reviewed International journal

Ni T., Bian J., Yang Z., Nie M., Yao L., Huang Z., Yan A., Wen X.

IEEE Design and Test   2022.01

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments Reviewed International journal

Yan A., Li Z., Huang S., Zhai Z., Cheng X., Cui J., Ni T., Wen X., Girard P.

Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022   1257 - 1262   2022.01

Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments Reviewed International journal

Yan A., Xu Z., Feng X., Cui J., Chen Z., Ni T., Huang Z., Girard P., Wen X.

IEEE Transactions on Emerging Topics in Computing   10 ( 1 )   404 - 413   2022.01

Power-Aware Testing in the Era of IoT Reviewed International journal

Wen X.

Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022   2022.01

Power and Energy Safe Real-Time Multi-Core Task Scheduling Reviewed International journal

Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022   16 - 21   2022.01

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits Reviewed International journal

Utsunomiya T., Hoshino R., Miyase K., Lu S.K., Wen X., Kajihara S.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022   43 - 48   2022.01

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS Reviewed International journal

Yan A., Song S., Zhang J., Cui J., Huang Z., Ni T., Wen X., Girard P.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022   73 - 78   2022.01

A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters Reviewed International journal

Yan A., Song S., Chen Y., Cui J., Huang Z., Wen X.

Proceedings of the IEEE Conference on Nanotechnology   2022-July   215 - 218   2022.01

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC Reviewed International journal

Ni T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   40 ( 9 )   1952 - 1956   2021.09

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications Reviewed International journal

Yan A., Cao A., Xu Z., Cui J., Ni T., Girard P., Wen X.

Journal of Electronic Testing: Theory and Applications (JETTA)   37 ( 4 )   489 - 502   2021.08

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments Reviewed

Yan A., Cao A., Fan Z., Xu Z., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   301 - 306   2021.06

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications Reviewed

Yan A., He Z., Zhou J., Cui J., Ni T., Huang Z., Wen X., Girard P.

Microelectronics Journal   111   2021.05

A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology Reviewed

Ni T., Yang Z., Chang H., Zhang X., Lu L., Yan A., Huang Z., Wen X.

IEEE Transactions on Emerging Topics in Computing   9 ( 2 )   724 - 734   2021.04

Reliability-Driven Neuromorphic Computing Systems Design Reviewed

Xu Q., Wang J., Geng H., Chen S., Wen X.

Proceedings -Design, Automation and Test in Europe, DATE   2021-February   1586 - 1591   2021.02

TPDICE and SIM based 4-node-upset completely hardened latch design for highly robust computing in harsh radiation Reviewed

Yan A., Ding L., Shan C., Cai H., Chen X., Wei Z., Huang Z., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems   2021-May   2021.01

On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption Reviewed

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers )   E104D ( 6 )   816 - 827   2021.01

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS Reviewed

Yan A., Lai C., Zhang Y., Cui J., Huang Z., Song J., Guo J., Wen X.

IEEE Transactions on Emerging Topics in Computing   9 ( 1 )   520 - 533   2021.01

Cellular Structure Based Fault-Tolerance TSV Configuration in 3D-IC Reviewed

Xu Q., Sun W., Chen S., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   41 ( 5 )   1196 - 1208   2021.01

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch Reviewed International journal

Yan A., Qian K., Cui J., Cui N., Ni T., Huang Z., Wen X.

2021 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021   2021.01

A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets Reviewed International journal

Yan A., Cao A., Qian K., Ding L., He Z., Fan Z., Wen X.

Proceedings - 2021 8th International Conference on Dependable Systems and Their Applications, DSA 2021   734 - 736   2021.01

Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure Reviewed International journal

Xu Q., Ni T., Geng H., Chen S., Yu B., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   41 ( 10 )   3182 - 3187   2021.01

Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing Reviewed International journal

Yan A., Zhai Z., Wang L., Zhang J., Cui N., Ni T., Wen X.

Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021   2021.01

LSI Testing: A Core Technology to a Successful LSI Industry Invited Reviewed International journal

Wen X.

Proceedings of International Conference on ASIC   2021.01

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning Reviewed International journal

Xu Q., Geng H., Chen S., Yuan B., Zhuo C., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   41 ( 10 )   3492 - 3502   2021.01

Novel Speed-and-Power-Optimized SRAM Cell Designs with Enhanced Self-Recoverability from Single- And Double-Node Upsets Reviewed

Yan A., Chen Y., Hu Y., Zhou J., Ni T., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers   67 ( 12 )   4684 - 4695   2020.12

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets Reviewed

Yan A., Chen Y., Zhou J., Cui J., Ni T., Wen X., Girard P.

Proceedings of the Asian Test Symposium   2020-November   2020.11

Logic Fault Diagnosis of Hidden Delay Defects Reviewed

Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

Proceedings - International Test Conference   2020-November   2020.11

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC Reviewed

Ni T., Chang H., Song T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs   67 ( 11 )   2657 - 2661   2020.11

Design of double-upset recoverable and transient-pulse filterable latches for low-power and low-orbit aerospace applications Reviewed

Yan A., Chen Y., Xu Z., Chen Z., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems   56 ( 5 )   3931 - 3940   2020.10

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors Reviewed

Dou Z., Yan A., Zhou J., Hu Y., Chen Y., Ni T., Cui J., Girard P., Wen X.

Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020   35 - 40   2020.09

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications Reviewed

Yan A., Xu Z., Yang K., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems   56 ( 4 )   2666 - 2676   2020.08

HITTSFL: Design of a cost-effective HIS-Insensitive TNU-Tolerant and SET-Filterable latch for safety-critical applications Reviewed

Yan A., Feng X., Zhao X., Zhou H., Cui J., Ying Z., Girard P., Wen X.

Proceedings - Design Automation Conference   2020-July   2020.07

Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment Reviewed

Yan A., Hu Y., Cui J., Chen Z., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computers   69 ( 6 )   789 - 799   2020.06

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments Reviewed

Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

IEEE Transactions on Aerospace and Electronic Systems   56 ( 2 )   1163 - 1171   2020.04

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs Reviewed

Yan A., Ling Y., Cui J., Chen Z., Huang Z., Song J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers   67 ( 3 )   879 - 890   2020.03

Dual-interlocked-storage-cell-based double-node-upset self-recoverable flip-flop design for safety-critical applications Reviewed

Yan A., Xu Z., Cui J., Ying Z., Huang Z., Liang H., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems   2020-October   2020.01

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications Reviewed

Yan A., Wu Z., Zhou J., Hu Y., Chen Y., Ying Z., Wen X., Girard P.

Proceedings of the Asian Test Symposium   2019-December   55 - 60   2019.12

Targeted partial-shift for mitigating shift switching activity hot-spots during scan test Reviewed

Holst S., Shi S., Wen X.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC   2019-December   124 - 129   2019.12

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications Reviewed

Yan A., Wu Z., Lu L., Chen Z., Song J., Ying Z., Girard P., Wen X.

Proceedings of the Asian Test Symposium   2019-December   43 - 48   2019.12

Variation-aware small delay fault diagnosis on compressed test responses Reviewed

Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings - International Test Conference   2019-November   2019.11

A fault-tolerant MPSoC for CubeSats Reviewed International journal

Fuchs C., Chou P., Wen X., Murillo N., Furano G., Holst S., Tavoularis A., Lu S., Plaat A., Marinis K.

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019   2019.10

A static method for analyzing hotspot distribution on the LSI Reviewed

Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   73 - 78   2019.09

A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells Reviewed International journal

Song Z., Yan A., Cui J., Chen Z., Li X., Wen X., Lai C., Huang Z., Liang H.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   139 - 144   2019.09

Power-Aware Testing for Low-Power VLSI Circuits Invited Reviewed International journal

X. Wen

15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits   Paper S12-1   2019.06

Small Delay Fault Diagnosis with Compacted Responses Reviewed International journal

S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich

Poster at ACM Design Automation Conf.   2019.06

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications Reviewed International journal

Yan A., Hu Y., Song J., Wen X.

Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019   1679 - 1684   2019.05

STAHL: A novel scan-test-aware hardened latch design Reviewed International journal

Ma R., Holst S., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop   2019-May   2019.05

Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout Reviewed International journal

Yan A., Wu Z., Guo J., Song J., Wen X.

IEEE Transactions on Reliability   68 ( 1 )   354 - 363   2019.03

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults Reviewed International journal

Ni T., Yao Y., Chang H., Lu L., Liang H., Yan A., Huang Z., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   39 ( 10 )   2938 - 2951   2019.01

Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets Reviewed

Yan A., Zhou J., Hu Y., Cui J., Huang Z., Girard P., Wen X.

IEEE Access   7   176188 - 176196   2019.01

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed International journal

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium   2018-October   149 - 154   2018.12

The impact of production defects on the soft-error tolerance of hardened latches Reviewed International journal

Holst S., Ma R., Wen X.

Proceedings of the European Test Workshop   2018-May   1 - 6   2018.06

Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM Reviewed International journal

I. Syafalni, T. Sasao, X. Wen

Proceedings of the 27th International Workshop on Logic and Synthesis   124 - 131   2018.06

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application Reviewed International journal

A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

IEEE Transactions on Circuits and Systems II: Express Briefs   66 ( 2 )   287 - 291   Early Access   2018.06

A Method to Detect Bit Flips in a Soft-Error Resilient TCAM Reviewed International journal

I. Syafalni, T. Sasao, X. Wen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   37 ( 6 )   1185 - 1196   2018.06

The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches Reviewed International journal

S. Holst, R. Ma, X. Wen

Proceedings of IEEE European Test Symposium   Paper 7A-1   2018.05

Design Automation for Legacy Circuits Reviewed International journal

I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies   174 - 179   2018.03

Locating Hot Spot with Justification Techniques in a Layout Design Reviewed International journal

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

Proceedings of IEEE Workshop on RTL and High Level Testing   Paper S1.2   2017.11

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption Reviewed International journal

Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian

Proceedings of the Asian Test Symposium   140 - 145   2017.11

Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors Reviewed International journal

S. Holst, E. Schneider, H. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen

Proceedings - International Test Conference   2017-December   1 - 8   Paper 3.4   2017.10

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips Reviewed International journal

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Transactions on Emerging Topics in Computing   8 ( 3 )   591 - 601   Early Access   2017.10

Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs Reviewed International journal

T. Ni, M. Nie, H. Liang, J. Bian, X. Xu, X. Fang, Z. Huang, X. Wen

IEICE Electronics Express   18 ( 14 )   Letter 20170590   2017.10

GPU-Accelerated Simulation of Small Delay Faults Reviewed International journal

E. Schneider, M. Kochte, S. Holst, X. Wen, H. Wunderlich

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   36 ( 5 )   829 - 841   2017.05

On Optimal Power-Aware Path Sensitization Reviewed International journal

Workshop of Test and Reliability for Circuits and Systems   2017.03

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding Reviewed International journal

Xiang D., Wen X., Wang L.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   25 ( 3 )   942 - 953   2017.03

Vernier ring based pre-bond through silicon vias test in 3D ICs Reviewed International journal

Ni Tianming, Nie Mu, Liang Huaguo, Bian Jingchang, Xu Xiumin, Fang Xiangsheng, Huang Zhengfeng, Wen Xiaoqing

IEICE Electronics Express ( The Institute of Electronics, Information and Communication Engineers )   14 ( 18 )   20170590 - 20170590   2017.01

Logic-Path-and-Clock-Path-Aware at-Speed Scan Test Generation Reviewed International journal

F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara

2016.12

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Reviewed International journal

LI Fuqiang, WEN Xiaoqing, MIYASE Kohei, HOLST Stefan, KAJIHARA Seiji

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( The Institute of Electronics, Information and Communication Engineers )   E99A ( 12 )   2310 - 2319   2016.12

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST Reviewed International journal

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Asian Test Symposium   203 - 208   2016.11

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed International journal

Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.

IEEE Asian Test Symposium   19 - 24   2016.11

On Optimal Power-Aware Path Sensitization Reviewed International journal

Sauer M., Jiang J., Reimer S., Miyase K., Wen X., Becker B., Polian I.

IEEE Asian Test Symposium   179 - 184   2016.11

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test Reviewed International journal

Eggersglub S., Holst S., Tille D., Miyase K., Wen X.

Proceedings of the Asian Test Symposium   173 - 178   2016.11

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures Reviewed International journal

CHEN Tian, SHEN Dandan, YI Xin, LIANG Huaguo, WEN Xiaoqing, WANG Wei

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers )   E99D ( 11 )   2672 - 2681   2016.11

Power-Aware Testing For Low-Power VLSI Circuits Invited Reviewed International journal

X. Wen

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings   585 - 588   Paper S37-1   2016.10

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM Reviewed International journal

Syafalni I., Sasao T., Wen X.

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI   2016-September   679 - 684   2016.07

SAT-Based Post-Processing for Regional Capture Power Reduction in at-speed scan test generation Reviewed International journal

Eggersgluss S., Miyase K., Wen X.

IEEE European Test Symposium   2016-July   2016.05

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill Reviewed International journal

D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   35 ( 3 )   499 - 512   2016.03

Test Pattern Modification for Average IR-Drop Reduction Reviewed International journal

W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen

IEEE Transactions on VLSI Systems   24 ( 1 )   38 - 49   2016.01

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch Reviewed International journal

IEEE Asian Test Symposium   103 - 108   2015.11

Power Supply Noise and Its Reduction in At-Speed Scan Testing Invited Reviewed International journal

X. Wen

IEEE International Conference on ASIC   Paper B5-3   2015.11

A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys Reviewed International journal

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

24th International Workshop on Logic and Synthesis   2015.06

Identification of High Power Consuming Areas with Gate Type and Logic Level Information Reviewed International journal

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE European Test Symposium   Paper 9.1   2015.05

A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys Reviewed International journal

IEEE European Test Symposium   Poster 2.4   2015.05

GPU-Accelerated Small Delay Fault Simulation Reviewed International journal

E. Schneider, S. Holst, M.-A. Kochte, X. Wen, H.-J. Wunderlich

Design and Test in Europe   1174 - 1179   2015.03

Towards Memory-Aware VLSI Simulation Algorithms for Heterogeneous Architectures Reviewed International journal

S. Holst, J. Miyazaki, X. Wen

International Symposium on Applied Engineering and Sciences   2014.12

Soft-Error Tolerant TCAMs for High-Reliability Packet Classification Reviewed International journal

IEEE Asia Pacific Conference on Circuits and Systems   471 - 474   2014.11

Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal

E. Schneider, S. Holst, X. Wen, H. Wunderlich

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD   17 - 23   2014.11

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed International journal

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEICE Transactions on Information and Systems   E97 ( 10 )   2706 - 2718   2014.10

An X-Filling Method for Low-Capture-Power Scan Test Generation

Li Fuqiang, Wen Xiaoqing, Miyase Kohei, Holst Stefan, Kajihara Seiji

IEICE technical report. Dependable computing ( The Institute of Electronics, Information and Communication Engineers )   114 ( 99 )   15 - 20   2014.06

Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal

E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

ACM Design Automation Conference   Poster   2014.06

Low-power testing for 2D/3D devices and systems Reviewed International journal

235 - 277   2014.01

ATPG Enhancement Technology Reviewed International journal

IEEE Workshop on RTL and High Level Testing   Paper IV.5.S   2013.11

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed International journal

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE Asian Test Symposium   19 - 24   2013.11

Search Space Reduction for Low-Power Test Generation Reviewed International journal

IEEE Asian Test Symposium   171 - 176   2013.11

Test Pattern Modification for Average IR-drop Reduction Reviewed International journal

J. Li, W-S. Ding, H-Y. Hsieh, X. Wen

IEEE International Test Conference   Poster   2013.09

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Reviewed International journal

K. Miyase, R. Sakai, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

IEICE Transaction on Information and Systems   E96-D ( 9 )   2003 - 2011   2013.09

SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction Reviewed International journal

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop   Paper 4.4   2013.07

Controllability Analysis of Local Switching Activity for Layout Design Reviewed International journal

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

Workshop on Design and Test Methodologies for Emerging Technologies   Paper 2   2013.05

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing Reviewed International journal

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE Design & Test of Computers   30 ( 4 )   60 - 70   2013.04

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression Reviewed International journal

26th International Conference on VLSI Design   279 - 284   2013.01

Fault Detection with Optimum March Test Algorithm Reviewed International journal

N. Zakaria, W. Hassan, I. Halin, R. Sidek, X. Wen

Journal of Theoretical and Applied Information Technology   47 ( 1 )   18 - 27   2013.01

Estimation of the Amount of Don't-Care Bits in Test Vectors Reviewed International journal

K. Miyase, S. Kajihara, X. Wen

IEEE Workshop on RTL and High Level Testing   2012.11

A Transition Isolation Scan Cell Design for Low Shift and Capture Power Reviewed International journal

Y.-T. Lin, J.-L Huang, X. Wen

IEEE Asian Test Symposium   107 - 112   2012.11

On Pinpoint Capture Power Management in At-Speed Scan Test Generation Reviewed International journal

X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE International Test Conference   Paper 6.1   2012.11

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal

S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang

ACM Transactions on Design Automation of Electronic Systems   17 ( 4 )   Article No. 48   2012.10

A Transition Isolation Scan Cell Design for Low Shift and Capture Power Reviewed International journal

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop   2012.07

Power-Aware Testing: The Next Stage Invited Reviewed International journal

X. Wen

IEEE European Test Symposium   Invited Talk   2012.05

A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits Reviewed International journal

K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara

IEEE VLSI Test Symposium   197 - 202   2012.04

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns Reviewed International journal

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

ASP Journal of Lower Power Electronics   8 ( 2 )   248 - 258   2012.04

Fault Detection with Optimum March Test Algorithm Reviewed International journal

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE International Conference on Intelligent Systems, Modeling and Simulation   Paper S8   2012.02

Testing static single cell faults using static and dynamic data background Reviewed International journal

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE Student Conference on Research and Development   1 - 6   2011.12

Additional Path Delay Fault Detection with Adaptive Test Data Reviewed International journal

K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing   31 - 34   2011.11

Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling Reviewed International journal

K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard

IEEE Asian Test Symposium   90 - 95   2011.11

Power-Aware Test Pattern Generation for At-Speed LOS Testing Reviewed International journal

A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase, X. Wen

IEEE Asian Test Symposium   506 - 510   2011.11

Efficient BDD-based Fault Simulation in Presence of Unknown Values Reviewed International journal

M. A. Kochte, S. Kundu, K. Miyase, X. Wen, H.-J. Wunderlich

IEEE Asian Test Symposium   383 - 388   2011.11

Towards the Next Generation of Low-Power Test Technologies Reviewed International journal

X. Wen

IEEE International Conference on ASIC   Paper 1E-1   2011.10

Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing Reviewed International journal

L.-T. Wang, N. A. Touba, M. S. Hsiao, J.-L. Huang, C.-M. Li, S. Wu, X. Wen, M. Bhattarai, F. Li, Z. Jiang

IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits   Paper 5.4   2011.09

A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing Reviewed International journal

IEEE International Test Conference   Paper 12.1   2011.09

Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing Reviewed International journal

Y.-T. Lin, J.-L. Huang, X. Wen

IEEE International Test Conference   Paper 2.3   2011.09

SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures Reviewed International journal

M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enokimoto, H.-J. Wunderlich

IEEE International Symposium on Low Power Electronics and Design   33 - 38   2011.08

低消費電力LSIのための低消費電力テスト技術 Invited Reviewed

温暁青

情報・システムソサイエティ誌 ( 電子情報通信学会　情報・システムソサイエティ )   16 ( 2 )   10 - 11   2011.08

VLSI Testing and Test Power Reviewed International journal

X. Wen

Workshop on Low Power System on Chip   Paper 4.1   2011.07

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing Reviewed International journal

K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara

IEICE Transactions on Information and Systems   E94-D ( 6 )   1216 - 1226   2011.06

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns Reviewed International journal

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

IEEE International Workshop on Impact of Low-Power design on Test and Reliability   4 Pages   2011.05

Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme Reviewed International journal

F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Workshop on Impact of Low-Power design on Test and Reliability   4 Pages   2011.05

Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing Reviewed International journal

X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, M. Tehranipoor

IEEE VLSI Test Symposium   166 - 171   2011.05

Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing Reviewed International journal

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era   1 - 6   2011.04

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing Reviewed International journal

IEICE Transactions on Information and Systems   E94-D ( 4 )   833 - 840   2011.04

Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation Reviewed International journal

K. Miyase, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

Design, Automation and Test in Europe   895 - 898   2011.03

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal

S. Wu,L.-T. Wang,X. Wen,Z. Jiang,M. Hsiao,W.-B. Jone,L. Tan,Y. Zhang,Y. Hu,C.-M. Li,Member,J.-L. Huang,L. Yu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   30 ( 3 )   455 - 463   2011.03

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme Reviewed International journal

K. Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara

IEEE Workshop on RTL and High Level Testing   125 - 129   2010.12

Hybrid Memory Built-In Self-Test Architecture for Multi-port Static RAMs Reviewed International journal

L. Yu, J. Hung, B. Sheu, B. Huynh, L. Nguyen, S. Wu, L.-T. Wang, X. Wen

IEEE Int Symposium on Defect and Fault Tolerance in VLSI Systems   331 - 339   2010.11

Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver Reviewed International journal

K. Miyase,M. A. Kochte,X. Wen,S. Kajihara,H.-J. Wunderlich

IEEE Workshop on Defect and Date Driven Testing   4 Pages   2010.11

Is Test Power Reduction Through X-Filling Good Enough? Reviewed International journal

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Test Conference   805 - 805   Poster   2010.11

On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test Reviewed International journal

S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, X. Wen

10th International Symposium on Communications and Information Technologies   723 - 726   2010.10

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains Reviewed International journal

S. Wu,L.-T. Wang,L. Yu,H. Furukawa,X. Wen,W.-B. Jone,N. A. Touba,F. Zhao,J. Liu,H.-J. Chao,F. Li,Z. Jiang

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems   358 - 366   2010.10

Case Studies on Transition Fault Test Generation for At-Speed Scan Testing Reviewed International journal

N. A. Zakariz, E. V. Bautista, S. M. Jusoh, W. F. Lee, X. Wen

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems   180 - 188   2010.10

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes Reviewed International journal

F. Wu,L. Dilillo,A. Bosio,P. Girard,S. Pravossoudovitch,A. Virazel,M. Tehranipoor,X. Wen,N. Ahmed

ASP Journal of Lower Power Electronics   6 ( 2 )   359 - 374   2010.08

On Delay Test Quality for Test Cubes Reviewed International journal

S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen

IPSJ Transactions on System LSI Design Methodology   3   283 - 291   2010.08

A Study of Capture-Safe Test Generation Flow for At-Speed Testing Reviewed International journal

K. Miyase, X. Wen, S. Kajihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja

IEICE Transactions on Information and Systems   E93-A ( 7 )   1309 - 1318   2010.07

On Estimation of NBTI-Induced Delay Degradation Reviewed International journal

M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura

IEEE European Test Symposium   107 - 111   2010.05

Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes Reviewed International journal

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, X. Wen

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems   376 - 381   2010.04

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Reviewed International journal

K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L. Wang, M. Tehranipoor

IEICE Transactions on Information and Systems   E93-D ( 1 )   2 - 9   2010.04

CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing Invited Reviewed International journal

X. Wen, K. Enokimoto, K. Miyase, S. Kajihara, M. Aso, H. Furukawa

Symposium II (International Semiconductor Technology Conference & China Semiconductor Technology International Conference)   197 - 202   2010.03

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal

L.-T. Wang,X. Wen,S. Wu,H. Furukawa,H.-J. Chao,B. Sheu,J. Guo,and W.-B. Jone

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   29 ( 2 )   299 - 312   2010.02

A Path Selection Method for Delay Test Targeting Transistor Aging Reviewed International journal

M. Noda,S. Kajihara,Y. Sato,K. Miyase,X. Wen,and Y. Miura

IEEE International Workshop on Reliability Aware System Design and Test   57 - 61   2010.01

X-Identification According to Required Distribution for Industrial Circuits Reviewed International journal

I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

IEEE Workshop on RTL and High Level Testing   76 - 81   2009.11

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing Reviewed International journal

K. Enokimoto,X. Wen,Y. Yamato,K. Miyase,H. Sone,S. Kajihara,M. Aso,and H. Furukawa

IEEE Asian Test Symposium   99 - 104   2009.11

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing Reviewed International journal

Y. Yamato,X. Wen,K. Miyase,H. Furukawa,and S. Kajihara

IEEE 15th Pacific Rim International Symposium on Dependable Computing   81 - 86   2009.11

Optimizing the Percentage of X-Bits to Reduce Switching Activity Reviewed International journal

I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

IEEE Workshop on Defect and Date Driven Testing   4 Pages   2009.11

A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment Reviewed International journal

K. Miyase,K. Noda,H. Ito,K. Hatayama,T. Aikyo,Y. Yamato,X. Wen,and S. Kajihara

IEEE/ACM International Conference on Computer Aided Design   97 - 104   2009.11

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment Reviewed International journal

M.-F. Wu,J.-L. Huang,X. Wen,K. Miyase

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   28 ( 11 )   1767 - 1776   2009.11

シグナルインテグリティ考慮型LSIテストを目指して Invited Reviewed

温　暁青

信頼性学会誌   31 ( 7 )   498 - 505   2009.10

LSI回路の低キャプチャ電力テスト生成技術 Invited Reviewed

温暁青

情報・システムソサイエティ誌 ( 電子情報通信学会　情報・システムソサイエティ )   14 ( 2 )   16 - 16   2009.08

On Calculation of Delay Range in Fault Simulation for Test Cubes Reviewed International journal

S. Oku,S. Kajihara,K. Miyase,X. Wen,Y. Sato

International Symposium on VLSI Design, Automation, and Test   64 - 67   2009.04

Power-Aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing Invited Reviewed International journal

Y. Yamato,X. Wen,K. Miyase,H. Furukawa,S. Kajihara

Metrology, Reliability and Testing (International Semiconductor Technology Conference & China Semiconductor Technology International Conference)   231 - 236   2009.03

Turbo1500: Core-Based Design for Test and Diagnosis Using IEEE Std. 1500 Reviewed International journal

L..-T. Wang,R. Apte,S. Wu,B. Sheu,K.-J. Lee,X. Wen,W.-B. Jone,C.-H. Yeh,J. Guo,J. Liu,Y.-C. Sung

IEEE Design & Test of Computers   26 ( 1 )   26 - 35   2009.01

On Delay Calculation in 3-valued Fault Simulation Reviewed International journal

S. Oku,S. Kajihara,K. Miyase,X. Wen,Y. Sato

IEEE Workshop on RTL and High Level Testing   123 - 128   2008.11

Practical Challenges in Logic BIST Implementation  Case Studies Reviewed International journal

S. Wu,H. Furukawa,B. Sheu,L.-T. Wang,H.-J. Chao,L. Yu,X. Wen,M. Murakami

IEEE Asian Test Symposium   265 - 265   2008.11

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing Reviewed International journal

H. Furukawa,X. Wen,K. Miyase,Yuta Yamato,S. Kajihara,Patrick Girard,L.-T. Wang,M. Teharanipoor

IEEE Asian Test Symposium   397 - 402   2008.11

Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification Reviewed International journal

K. Miyase,K. Noda,H. Ito,K. Hatayama,T. Aikyo,Y. Yamato,H. Furukawa,X. Wen,S. Kajihara

IEEE/ACM International Conference on Computer Aided Design   52 - 58   2008.11

GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing Reviewed International journal

Y. Yamato,X. Wen,K. Miyase,H. Furukawa,S. Kajihara

IEEE Workshop on Defect and Date Driven Testing   4 Pages   2008.10

Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG Reviewed International journal

J. Ma,J. Lee,M. Tehranipoor,X. Wen,A. Crouch

IEEE Workshop on Defect and Date Driven Testing   7 Pages   2008.10

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing Reviewed International journal

M.-F. Wu,J.-L. Huang,X. Wen,K. Miyase

IEEE International Test Conference   Paper 13.1   2008.10

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using IEEE Std. 1500 Reviewed International journal

L.-T. Wang,R. Apte,S. Wu,B. Sheu,K.-J. Lee,X. Wen,W.-B. Jone,C.-H. Yeh,J. Guo,J. Liu,Y.-C. Sung

IEEE International Test Conference   Paper 29.3   2008.10

On Optimizing Pattern Count and ATPG Time Using A Hybrid Single-Capture Scheme for Testing Scan Designs Reviewed International journal

B. Sheu,L.-T. Wang,Z. Jiang,J. Soong,S. Wu,R. Apte,X. Wen,C.-M. Li

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems   143 - 151   2008.10

Test Strategies for Low-Power Devices Invited Reviewed International journal

C. P. Ravikumar,M. Hirech,X. Wen

Journal of Low Power Electronics   4 ( 2 )   127 - 138   2008.08

Estimation of Delay Test Quality and Its Application to Test Generation Reviewed International journal

S. Kajihara,S. Morishima,M. Yamamoto,X. Wen,M. Fukunaga,K. Hatayama,T. Aikyo

IPSJ Transaction of System LSI Design Methodology   1   104 - 115   2008.08

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing Reviewed International journal

X. Wen,K. Miyase,S. Kajihara,H. Furukawa,Y. Yamato,A. Takashima,K. Noda,H. Ito,K. Hatayama,T. Aikyo,K. K. Saluja

IEEE European Test Symposium   55 - 60   2008.05

Diagnosis of Realistic Defects Based on X-Fault Model Reviewed International journal

I. Polian,Y. Nakamura,P. Engelke,S. Spinner,K. Miyase,S. Kajihara,B. Becker,X. Wen

IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems   263 - 266   2008.04

Test Strategies for Low-Power Devices Invited Reviewed International journal

C. P. Ravikumar,M. Hirech,X. Wen

Design Automation, and Test in Europe   728 - 733   2008.03

VirtualScan: A Test Compression Technology Using Combinational Logic and One-Pass ATPG Reviewed International journal

L.-T. Wang,X. Wen,S. Wu,Z. Wang,Z. Jiang,B. Sheu,X. Gu

IEEE Design & Test of Computers   25 ( 2 )   122 - 130   2008.03

On Detection of Bridge Defects with Stuck-at Tests Reviewed International journal

K. Miyase,K. Terashima,X. Wen,S. Kajiihara,and S. M Reddy

IEICE Transactions on Information and Systems   E91-D ( 3 )   683 - 689   2008.03

A Novel Per-Test Fault Diagnosis Method Based On the Extended X-Fault Model for Deep-Submicron LSI Circuits Reviewed International journal

Y. Yamato,Y. Nakamura,K. Miyase,X. Wen,and S. Kajihara

IEICE Transactions on Information and Systems   E91-D ( 3 )   667 - 674   2008.03

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing Reviewed International journal

X. Wen,K. Miyase,T. Suzuki,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing   24 ( 4 )   379 - 391   2008.01

Estimation of Delay Test Quality and Its Application to Test Generation Reviewed International journal

S. Kajihara,S. Morishima,M. Yamamoto,X. Wen,M. Fukunaga,K. Hatayama,and T. Aikyo

IEEE/ACM International Conference on Computer Aided Design   413 - 417   2007.11

A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set Reviewed International journal

K. Miyase,X. Wen,S. Kajihara,M. Haraguchi,H. Furukawa

IEEE International Workshop on Defect Based Testing   51 - 56   2007.10

A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing Reviewed International journal

X. Wen,K. Miyase,S. Kajihara,T. Suzuki,Y. Yamato,P. Girard,Y. Ohsumi,and L.-T. Wang

IEEE International Test Conference   25.1   2007.10

A Novel ATPG Method for Capture Power Reduction During Scan Testing Reviewed International journal

X. Wen,S. Kajiihara,K. Miyase,T. Suzuki,K. K. Saluja,L.-T. Wang,K. Kinoshita

IEICE Transactions on Information and Systems   E90-D ( 9 )   1398 - 1405   2007.09

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing Reviewed International journal

X. Wen,K. Miyase,T. Suzuki,S. Kajihara,Y. Ohsumi,K. K. Saluja

IEEE/ACM Design Automation Conference   527 - 532   2007.06

An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits Reviewed International journal

X. Wen,Y. Yamato,K. Miyase,S. Kajihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE Workshop on RTL and High Level Testing   55 - 60   2006.11

Test Data Compression Based on Clustered Random Access Scan Reviewed International journal

Y. Hu,C. Li,J. Li,Y. Han,X. Li,W. Wang,H. Li,L.-T. Wang,X. Wen

IEEE Asian Test Symposium   231 - 236   2006.11

A Per-Test Fault Diagnosis Method Based on the X-Fault Model Reviewed International journal

X. Wen,S. Kajiihara,K. Miyase,Y. Yamato,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEICE Transactions on Information and System   E89-D ( 11 )   2756 - 2765   2006.11

A Framework of High-quality Transition Fault ATPG for Scan Circuits Reviewed International journal

S. Kajihara,S. Morishima,A. Takuma,X. Wen,T. Maeda,S. Hamada,Y. Sato

IEEE International Test Conference   Paper 2.1   2006.10

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing Reviewed International journal

H. Furukawa,X. Wen,L.-T. Wang,B. Sheu,Z. Jiang,S. Wu

IEEE International Test Conference   Paper 17.2   2006.10

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time Reviewed International journal

Y. Hu,Y. Han,X. Li,H. Li,X. Wen

IEICE Transactions on Information and Systems   E89-D ( 10 )   2616 - 2625   2006.10

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation Reviewed International journal

X. Wen,K. Miyase,T. Suzuki,Y. Yamato,S. Kajihara,L.-T. Wang,K. K. Saluja

IEEE International Conference on Computer Design   251 - 258   2006.10

Hybrid Fault Simulation with Compiled and Event-Driven Methods Reviewed International journal

K. Taniguchi,H. Fujii,S. Kajihara,X. Wen

IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology   240 - 243   2006.09

A New Method for Low-Capture-Power Test Generation for Scan Testing Reviewed International journal

X. Wen,Y. Yamashita,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEICE Transactions on Information and Systems   E89-D ( 5 )   1679 - 1686   2006.05

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing Reviewed International journal

X. Wen,S. Kajihara,K. Miyase,T. Suzuki,K. K. Saluja,L.-T. Wang,K. S. Abdel-Hafez,K. Kinoshita

IEEE VLSI Test Symposium   58 - 63   2006.04

A Dynamic Test Compaction Procedure for High-quality Path Delay Testing Reviewed International journal

M. Fukunaga,S. Kajihara,X. Wen,T. Maeda,S. Hamada,Y. Sato

IEEE/ACM Asian and South Pacific Design Automation Conference   348 - 353   2006.01

On Improving Defect Coverage of Stuck-at Fault Tests Reviewed International journal

K. Miyase, K. Terashima, S. Kajihara, X. Wen, S. M. Reddy

IEEE Asian Test Symposium   216 - 223   2005.12

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-In Power Dissipation and Test Application Time Reviewed International journal

Y. Hu, Y. Han, X. Li, H. Li, X. Wen

IEEE Pacific Rim International Symposium on Dependable Computing   8 - 8   2005.12

Efficient Test Set Modification for Capture Power Reduction Reviewed International journal

X. Wen,T. Suzuki,S. Kajihara,K. Miyase,Y. Minamoto,L.-T. Wang,K. K. Saluja

Jounal of Low Power Electrnics   1 ( 3 )   319 - 330   2005.12

Low-Capture-Power Test Generation for Scan-Based At-Speed Testing Reviewed International journal

X. Wen,Y. Yamashita,S. Morishima,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE International Test Conference   Paper 39.2   2005.11

UltraScan: Using Time-Division Demultiplexing/Multiplexing (TDDM/TDM) with VirtualScan for Test Cost Reduction Reviewed International journal

S. Wu,L.-T. Wang,K. S. Abdel-Hafez,B. Sheu,F. Hsu,S. Lin,M. Chang,X. Wen

IEEE International Test Conference   Paper 36.4   2005.11

At-Speed Logic BIST Archtecture for Multiple-Clock Circuits Reviewed International journal

IEEE International Conference on Computer Design   475 - 478   2005.10

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores Reviewed International journal

Y. Han, Y. Hu, X. Li, H. Li, A. Chandra, X. Wen

IEICE Transactions on Information and Syste   E88-D ( 9 )   2126 - 2134   2005.09

A Method for Low-Capture-Power At-Speed Test Generation Reviewed International journal

X. Wen,Y. Yamashita,S. Morishima,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE Workshop on RTL and High Level Testing   40 - 49   2005.07

On Quantifying Observability for Fault Diagnosis of VLSI Circuits Reviewed International journal

N. Toyota,X. Wen,S. Kajihara,M. Sanada

IEEE Workshop on RTL and High Level Testing   192 - 197   2005.07

Path Delay Test Compaction with Process Variation Tolerance Reviewed International journal

S. Kajihara,M. Fukunaga,X. Wen,T. Maeda,S. Hamada,Y. Sato

IEEE/ACM Design Automation Conference   845 - 850   2005.06

On the Extraction of a Minimum Cube to Justify Signal Line Values Reviewed International journal

K. Miyase,S. Nagayama,S. Kajihara,X. Wen,S. M. Reddy

IEEE European Test Symposium   79 - 84   2005.05

On Low-Capture-Power Test Generation for Scan Testing Reviewed International journal

X. Wen,Y. Yamashita,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE VLSI Test Symposium   265 - 270   2005.05

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Reviewed International journal

X. Wen,S. Kajihara,H. Tamamoto,K. K. Saluja,K. Kinoshita

IEICE Transactions on Information and Systems   E88-D ( 4 )   703 - 710   2005.04

On Speed-Up of Fault Simulation for Handling Intermediate Faulty Voltages Reviewed

X. Wen, S. kajihara, H. Tamamoto, K.K. Saluja, K. Kinoshita

J88-D-I ( 4 )   906 - 907   2005.04

At-Speed Logic BIST for IP Cores Reviewed International journal

B. Cheon,E. Lee,L.-T. Wang,X. Wen,P. Hsu,J. Cho,J. Park,H. Chao,S. Wu

Design Automation, and Test in Europe   860 - 861   2005.03

Fault Diagnosis for Physical Defects using Unknown Behavior Model Reviewed International journal

X. Wen,H. Tamamoto,K. K. Saluja,K. Kinoshita

Journal of Computer Science and Technology   20 ( 2 )   187 - 194   2005.03

Test Compression for Scan Circuits Using Scan Polarity Adjustment and Pinpoint Test Relaxation Reviewed International journal

Y. Doi,S. Kajihara,X. Wen,L. Li,and K. Chakrabarty

ACM Asian and South Pacific Design Automation Conference   59 - 64   2005.01

On Extraction of a Cube with the Minimum Number of Literals from a Given Input Vector Reviewed International journal

K. Miyase,S. Nagayama,S. Kajihara,X. Wen,and S. M. Reddy

IEEE Workshop on RTL and High Level Testing   71 - 76   2004.11

On Per-Test Fault Diagnosis Using the X-Fault Model Reviewed International journal

X. Wen,T. Miyoshi,S. Kajiihara,L. Wang,K. K. Saluja,and K. Kinoshita

IEEE/ACM International Conference on Computer Aided Design   633 - 640   2004.11

VirtualScan: A New Compressed Scan Technology for Test Cost Reduction Reviewed International journal

L.-T. Wang,X. Wen,H. Furukawa,F. Hsu,S. Lin,S. Tsai,K. S. Abdel-Hafez,S. Wu

IEEE International Test Conference   916 - 925   2004.10

ロジックBIST技術の現状と課題 Invited Reviewed

温暁青，梶原誠司

日本信頼性学会誌 ( 未設定 )   26 ( 4 )   252 - 262   2004.06

Chapter 20 "Low-Power Testing for Low-Power LSI Circuits", Advanced Circuits for Emerging Technologies

X. Wen, Y. Zorian（Joint author）

John Wiley & Sons  2012.06  （ ISBN:978-0-470-90005-5 ）

Power-Aware Testing and Test Strategies for Low Power Devices

P. Girard, N. Nicolici, X. Wen（Joint editor）

Springer  2009.11  （ ISBN:9781441909275 ）

Chapter 3: "Low-Power Test Generation" in Power-Aware Testing and Test Strategies for Low Power Devices

X. Wen,S. Wang（Joint author）

Springer  2009.11  （ ISBN:978-1441909275 ）

Chapter 7: "Test Synthesis" in Electronic Design Automation: Synthesis, Verification, and Test

L.-T. Wang,X. Wen, S. Wu（Joint author）

Morgan Kaufmann Publishers  2009.03  （ ISBN:978-0123743640 ）

Chapter 7: "Low-Power Testing" in Advanced SOC Test Architectures Towards Nanometer Designs

P. Girard,X. Wen, N. A. Touba（Joint author）

Morgan Kaufmann Publishers  2007.12  （ ISBN:978-0123739735 ）

半導体デバイスの評価・テスト・解析技術

温暁青,筒井信明,益子洋治,木村祐造,小坂彰（Joint author）

九州地域産業活性化センター  2006.10 

Chapter 2: "Design for Testability" in VLSI Test Principles and Architectures: Design for Testability

L.-T. Wang, X. Wen, K. S. Abdel-Hafez（Joint author）

Morgan Kaufmann Publishers  2006.07  （ ISBN:978-0123705976 ）

VLSI Test Principles and Architectures: Design for Testability

L.-T. Wang, C.-W.Wu, X. Wen（Joint editor）

Morgan Kaufmann Publishers  2006.07  （ ISBN:978-0123705976 ）

半導体テスト技術者育成実証講座　ベーシックコース

益子洋治,上村正幸,小野陽二,温暁青,筒井信明（Joint author）

大分県産業創造機構  2006.01 

半導体テスト技術者育成実証講座　ベーシックコース

益子洋治,上村正幸,小野陽二,温暁青,筒井信明（Joint author）

大分県産業創造機構  2006.01 

3値テストパターンに対する遅延テスト品質評価とX割当について

情報創成工学専攻, 奥慎治

電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング 

部分X分解によるX故障モデルを用いた故障診断手法の高速化

情報創成工学専攻, 宮瀬紘平

電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング 

フィールドテストにおける巡回テストとテスト集合印加順序について

情報創成工学専攻, 広実一輝

第62回 FTC 研究会資料集 

劣化検知テストにおけるパス選択について

情報創成工学専攻, 野田光政

電子情報通信学会技術研究報告, VLD2009-65 

信号値遷移削減のためのドントケア判定率の最適化に関する研究

情報創成工学専攻, 別府厳

電子情報通信学会技術研究報告 VLD2009-55 

実速度スキャンテストにおけるクリティカルエリア特化型IR-Drop削減手法

情報創成工学専攻, 榎元和成

平成21年度 電気関係学会九州支部連合大会予稿集 

ブロードキャストスキャン圧縮環境下における実速度テストに対するIR-Drop削減Post-ATPG手法

情報創成工学専攻, 宮瀬紘平

第61回 FTC 研究会資料集 

先端LSI回路向け低消費電力テスト技術の研究開発

本人

福岡・長野クラスターマッチングフォーラム 2009 

論理回路における劣化故障の発生しやすい箇所の推定について

情報創成工学専攻, 野田光政

第60回 FTC 研究会資料集 

実速度スキャンテストにおけるキャプチャセーフテスト生成手法について

情報創成工学専攻, 高嶋敦之

電子情報通信学会技術研究報告 

3値論理シミュレーションにおける遅延計算について

情報創成工学専攻, 福澤友晶

第59回 FTC 研究会資料集 

実速度スキャンテストにおけるキャプチャ時消費電力削減手法

情報創成工学専攻, 福澤友晶

第58回 FTC 研究会資料集 

実速度スキャンテストにおけるキャプチャ時の低消費電力テスト生成手法について

情報創成工学専攻, 福澤友晶

デザインガイア2007 ディペンダブルコンピューティング研究会, 信学技法, IEICE Technical Report 

Per-Test X故障診断手法の 診断分解能向上に関する研究

情報創成工学専攻, 大谷雅志

LSIテスティイングシンポジウム2007会議録 

実速度スキャンテストにおけるキャプチャ時の低消費電力テスト生成手法について

信学技法, IEICE Technical Report 

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

The 7th International Workshop on Microelectronics Assembling and Packaging & Reverse Trade Show 

LSI回路のX故障によるPer-Test故障診断手法の拡張について

信学技法, IEICE Technical Report 

順序回路用故障シミュレーションにおけるコンパイル方式の適用と効果について

情報処理学会DAシンポジウム2007論文集 

遷移遅延故障に対する高品質テスト生成手法について

IEICE technical report, Dependable Computing 

低消費電力テストのための制約付テスト生成手法について

電子情報通信学会技術研究報告  

遅延テスト品質の正確な評価法とテスト生成への応用

第56回 FTC 研究会資料集 

ブロードサイドテストにおけるN回検出用テストパターンに対するX判定

電子情報通信学会技術研究報告 

A New Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits

LSIテスティイングシンポジウム 

縮退故障用テストパターンのブリッジ故障検出率向上手法について

情報処理学会DAシンポジウム 

コンパイル方式とイベント駆動方式を用いた故障シミュレーションの高速化について

第55回 FTC 研究会 

ブロードサイド方式におけるパス長を考慮した遷移故障用テストパターン生成について

電子情報通信学会技術研究報告 

Low-Capture-Power Test Generation for Scan Testing

COE workshop for SoC Design Technology and Automation 

縮退故障用テストパターンのブリッジ故障検出率向上手法について

情報処理学会DAシンポジウム 

SoCにおけるブロードキャストスキャンテスト効率化手法について

第53回 FTC 研究会 

超微細ＬＳＩのパス遅延故障に対するテスト圧縮法について

電子情報通信学会技術研究報告DC2004-107 

スキャンテストにおけるキャプチャ時の消費電力削減を考慮したテスト生成

第52回 FTC 研究会 

故障診断のための観測性の定量化について

電子情報通信学会技術研究報告ICD2004-212 

圧縮化スキャンパタン生成技術

SEMI Technology Synposium 

スキャン極性調節とピンポイントテスト変換によるテスト圧縮

電子情報通信学会技術研究報告  

入力ベクトルからの信号値を正当化する最小キューブ抽出

電子情報通信学会技術研究報告  

X故障モデルを用いたPer-Test故障診断手法に関する研究

LSIテスティイングシンポジウム 

X故障モデルを用いたPer-Test故障診断手法について

情報処理学会DAシンポジウム 

トランジスタ動作を考慮したデジタル回路のテストと解析

第51回 FTC 研究会 

GENERATING DEVICE, GENERATING METHOD, AND PROGRAM

K. Miyase, X. Wen, S. Kajihara, Y. Yamato

Test Device, Test Method, Program and Medium

X. Wen, K. Miyase, K. Enokimoto

Method and Apparatus for Unifying Self-Test with Scan-Test During Prototype Debug and Production Test

L.-T. Wang, X. Wen

DON'T-CARE-BIT IDENTIFICATION METHOD AND DON'T-CARE-BIT IDENTIFICATION PROGRAM

K. Miyase, X. Wen, S. Kajihara, Y. Yamato

LOGIC VALUE DETERMINATION METHOD AND LOGIC VALUE DETERMINATION PROGRAM

K. Miyase, X. Wen, S. Kajihara, Y. Yamato

TEST PATTERN GENERATION METHOD FOR AVOIDING FALSE TESTING IN TWO-PATTERN TESTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT

X. Wen, K. Miyase, S. Kajihara

DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM

X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

Generation Device, Generation Method, Program and Medium

M. Wu, J.-L. Huang, X. Wen, K. Miyase

Generation Device, Generation Method, Program and Medium

M. Miyase, X. Wen, S. Kajihara

METHOD AND APPARATUS FOR BROADCASTING SCAN PATTERNS IN A SCAN-BASED INTEGRATED CIRCUIT

L.-T. Wang, H.-P. Wang, X. Wen, M.-C. Lin, S.-H. Lin, T.-C. Yeh, S.-W. Tsai, K.-S. Abdel-Hafez

Logic Value Determination Method and Logic Value Determination Program

M. Miyase, X. Wen, S. Kajihara

Don't Care Extraction Method and Don't Care Extraction Program

M. Miyase, X. Wen, S. Kajihara

Multiple-Capture DFT system for scan-based integrated circuits

L.-T. Wang, M.-C. Lin, X. Wen, H.-P. Wang, C.-C. Hsu, S.-C. Kao, F.-S. Hsu

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

L.-T. Wang, X. Wen, K.-S. Abdel-Hafez, S.-H. Lin, H.-P. Wang, M.-T. Chang, P.-C. Hsu, S.-C. Kao, M.-C. Lin

GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM

X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

L.-T. Wang, P.-C. Hsu, S.-C. Kao, M.-C. Lin, H.-P. Wang, H.-J. Chao, X. Wen

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

L.-T. Wang, X. Wen, S.-H. Lin, K.-S. Abdel-Hafez

CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM

X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

Test Generation Method for Avoiding False Testing in 2-Pattern Test for LSI Circuits

X. Wen, K. Miyase, S. Kajijhara

Computer-aided design system to automate scan synthesis at register-transfer level

L.-T. Wang, X. Wen

GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM

X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

Test Method and Test Program of Semiconductor Logic Circuit Device

X. Wen, S. Kajihara

Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

L.-T. Wang, P.-C. Hsu, X. Wen

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

L.-T. Wang, M.-T. Chang, H.-J. Chao, X. Wen, P.-C. Hsu

Diagnosis Device, Diagnosis Method, Program and Medium

X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

Generation Device, Generation Method, Program and Medium

X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

Test vector generating method and test vector generating program of semiconductor logic circuit device

X. Wen, S. Kajihara

Generation Device, Generation Method, Program and Medium

X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

Conversion Device, Conversion Method, Program and Medium

X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

Multiple-capture DFT system for scan-based integrated circuits

L.-T. Wang, M.-C. Lin, X. Wen, H.-P. Wang, C.-C. Hsu, S.-C. Kao, F.-S. Hsu

Computer-aided design system to automate scan synthesis at register-transfer level

L.-T. Wang, X. Wen, S.-H. Lin

Fault Diagnosis Method, Device, Diagnosis Method, Medium of Program for Semiconductor Logic Circuits

X. Wen, S. Kajijhara

Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

L.-T. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu, F.-S. Hsu, A. Kifli, S.-H. Lin, S. Wu, S.-M. Wang

Mask network design for scan-based integrated circuits

L.-T. Wang, S.-M. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu

Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits

L.-T. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu, S.-M. Wang

Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

K.-S. Abdel-Hafez, X. Wen, L.-T. Wang, P.-C. Hsu, S.-C. Kao, H.-J. Chao, H.-P. Wang