Updated on 2024/05/14

 
WEN Xiaoqing
 
Scopus Paper Info  
Total Paper Count: 0  Total Citation Count: 0  h-index: 23

Citation count denotes the number of citations in papers published for a particular year.

Affiliation
Faculty of Computer Science and Systems Engineering Department of Computer Science and Networks
Job
Professor
External link

Research Interests

  • Design for Testability

  • Fault Diagnosis

  • High-Reliability Design

  • LSI Test

Research Areas

  • Informatics / Computer system  / 半導体集積回路のテストとテスト容易化設計

Undergraduate Education

  • 1986.07   Tsinghua University   Computer Science and Technology   Graduated   China

Post Graduate Education

  • 1993.03   Osaka University   Graduate School, Division of Engineering   Applied Physics   Doctoral Program   Completed   Japan

  • 1990.03   Hiroshima University   Graduate School, Division of Engineering   Information Engineering   Master's Course   Completed   Japan

Degree

  • Osaka University  -  Doctor of Engineering   1993.03

  • Hiroshima University  -  Master of Engineering   1990.03

  • Tsinghua University  -  Bachelor of Engineering   1986.07

Biography in Kyutech

  • 2019.04
     

    Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Computer Science and Networks   Professor  

  • 2017.04
    -
    2019.03
     

    Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering  

  • 2017.04
    -
    2019.03
     

    Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering  

  • 2013.04
    -
    2017.03
     

    Kyushu Institute of Technology   Research Center for Dependable Integrated Systems   Director  

  • 2012.04
    -
    2013.03
     

    Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering   Department of Creative Informatics   Department Chair  

  • 2008.04
    -
    2019.03
     

    Kyushu Institute of Technology   Faculty of Computer Science and Systems Engineering   Department of Creative Informatics   Professor  

  • 2008.04
    -
    2010.03
     

    Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering   Department of Creative Informatics   Department Chair  

  • 2007.04
    -
    2008.03
     

    Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering   Professor  

  • 2004.01
    -
    2007.03
     

    Kyushu Institute of Technology   Graduate School of Computer Science and Systems Engineering   Associate Professor (as old post name)  

▼display all

Biography before Kyutech

  • 2016.01   Universiti Teknologi Malaysia (UTM)   Embedded System Research Laboratory   Asscociate Member   United States

  • 1998.01 - 2003.12   SynTest Techniologies, Inc.   Vice President (VP) and Chief Technoilogy Officer (CTO)   United States

  • 1995.10 - 1996.03   Department of Eletrical and Computer Engineering University of Wisconsin - Madison   Visiting Researcher   United States

  • 1993.09 - 1997.12   Department of Information Engineering Akita University   Lecturer   Japan

  • 1993.04 - 1993.08   アイシー測器株式会社   研究開発技術者   Japan

Academic Society Memberships

  • 1989.01   Institute of Electrical and Electronics Engineers (IEEE)   United States

  • 2011.01   Technical Activity Committee on Power-Aware Testing, TTTC, IEEE Computer Society   United States

  • 2007.01   Asian Subcommittee, IEEE International Test Conference   United States

  • 2005.01   Institute of Electronic, Information and Communication Engineers (IEICE)   Japan

  • 2010.02   Information Processing Society of Japan (IPSJ)   Japan

  • 2005.04   Reliability Engineering Association of Japan   Japan

  • 2015.10   Japan Micro-Nano Bubble Society Corporation   Japan

  • 2017.12   日本学術振興会科学研究費委員会   Japan

  • 2017.01   中国自然科学基金委員会   China

  • 2014.04   国立研究開発法人科学技術振興機構「研究成果最適展開支援プログラム」   Japan

  • 2015.04 - 2017.03   国立研究開発法人科学技術振興機構「マッチングプランナープログラム」   Japan

  • 2017.04   国立研究開発法人科学技術振興機構「地域産学バリュープログラム」   Japan

  • 2014.04   国立研究開発法人科学技術振興機構「研究成果最適展開支援プログラム」   Japan

  • 2010.04   国立研究開発法人科学技術振興機構「A-STEP探索タイプ」   Japan

  • 2004.01   IEEE Transactions on Computer-Aided Design   United States

  • 2004.01   IEEE Transactions on VLSI Systems   United States

  • 2004.01   Journal of Electronic Testing: Theory and Applications   United States

  • 2009.01   Journal of Computer Science and Technology   China

  • 2009.01   Indian Journal of VLSI and Electronic System Design   India

  • 2017.01   International Conference on Intelligent Green Building and Smart Grid   Others

  • 2017.01   IEEE International Test Conference in Asia (ITC-Asia)   Others

  • 2016.01   International Doctoral Symposium on Applied Computation and Security Systems (ACSS)   Others

  • 2015.01   IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)   Others

  • 2015.01   IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)   Others

  • 2015.01   International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Others

  • 2014.01   IEEE Asia Pacific Conference on Circuits and Systms (APCCAS)   Others

  • 2014.01   International Conference on VLSI Design (VLSID)   Others

  • 2013.01   International Conference on Advanced Technologies for Communications (ATC)   Others

  • 2013.01   IEEE International Reliability Innovations Conference (IRIC)   Others

  • 2013.01   IEEE Latin-American Test Symposium (LATS)   Others

  • 2012.01   IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Others

  • 2010.06 - 2012.05   Association of Computing Machinery (ACM)   United States

  • 2010.01   IEEE International Conference of Networking, Sensing and Control (ICNSC)   Others

  • 2009.04   Design, Automation and Test in Europe Conference and Exhibition (DATE)   Others

  • 2009.01   IEEE/VSI VLSI Design And Test Symposium (VDAT)   Others

  • 2009.01   IEEE International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR)   Others

  • 2009.01   IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)   Others

  • 2009.01   IEEE International Conference on ASIC (ASICON)   Others

  • 2008.04 - 2010.03   JST シーズ発掘試験査読評価委員会   Japan

  • 2008.01   IEEE International Symposium on Electronic Design, Test and Applications (DFT)   Others

  • 2008.01   IEEE European Test Symposium (ETS)   Others

  • 2008.01   IEEE International Conference on Computer Design (ICCD)   Others

  • 2007.04 - 2011.03   大分県 LSIクラスター形成推進会議   Japan

  • 2007.01   IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Others

  • 2006.04 - 2009.03   福岡県 FIBA (Fukuoa International Business Association)   Japan

  • 2006.04 - 2007.03   大分県産業創造機構 H18年度ジョブカフェモデル事業検討会議   Japan

  • 2006.04 - 2007.03   経済産業省 産学連携製造中核人材育成事業   Japan

  • 2006.01   IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   United States

  • 2005.04 - 2006.03   経済産業省 平成17年度「半導体電子部品・装置・部材・解析等の製造現場のプロフェッショナル育成事業」   Japan

  • 2005.04 - 2006.03   東アジア経済交流推進機構 ウェハテストビジネス可能性検討委員会   Japan

  • 2005.04 - 2006.03   大分県半導体クラスター 未来を担う若い人材の養成(ジョブカフェ)協議会   Japan

  • 2004.04 - 2005.03   経済産業省 平成16年度製造現場の中核人材育成FS調査事業(半導体製造におけるテスト解析テクノロジストの育成)」の評価委員会   Japan

  • 2004.01   Asian and South Pacific Design Automation Conference (ASP-DAC)   United States

  • 2004.01   Design Automation Conference (DAC)   Others

  • 2004.01   IEEE International Symposium on Electronic Design, Test and Applications (DELTA)   Others

  • 2000.01   IEEE Workshop on RTL and High Level Testing (WRTLT)   Others

  • 1997.01 - 1997.12   International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability   Others

  • 1993.01   IEEE International Test Conference (ITC)   United States

  • 1993.01   IEEE Great Lake Symposium on VLSI   Others

  • 1993.01   IEEE Asian Test Symposium (ATS)   Others (Asian region)

▼display all

Research Career

  • Low-Power LSI Test

    研究期間: 2004.01  - 

  • LSI High Reliability Design

    研究期間: 2014.04  - 

  • LSI Test Generation

    研究期間: 1993.04  - 

  • LSI Design for Testability

    研究期間: 1993.04  - 

  • LSI Fault Diagnosis

    研究期間: 1993.04  - 

Papers

  • A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications Reviewed International journal

    Yan A., He Y., Niu X., Cui J., Ni T., Huang Z., Girard P., Wen X.

    IEEE Design and Test   40 ( 4 )   34 - 41   2023.08

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/MDAT.2023.3267747

    Scopus

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  • Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata Reviewed International journal

    Yan A., Liu R., Cui J., Ni T., Girard P., Wen X., Zhang J.

    IEEE Transactions on Circuits and Systems II: Express Briefs   70 ( 6 )   2256 - 2260   2023.06

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCSII.2023.3237695

    Scopus

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  • LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments Reviewed International journal

    Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   42 ( 6 )   2069 - 2073   2023.06

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2022.3213212

    Scopus

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  • Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments Reviewed International journal

    Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

    IEEE Transactions on Aerospace and Electronic Systems   59 ( 3 )   2885 - 2897   2023.06

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TAES.2022.3219372

    Scopus

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  • Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion Reviewed International journal

    Zhou W., Ouyang Y., Xu D., Huang Z., Liang H., Wen X.

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems   31 ( 4 )   442 - 455   2023.04

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TVLSI.2023.3244859

    Scopus

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  • High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology Reviewed International journal

    Yan A., Zhou Z., Ding L., Cui J., Huang Z., Wen X., Girard P.

    Proceedings -Design, Automation and Test in Europe, DATE   2023-April   2023.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.23919/DATE56975.2023.10136927

    Scopus

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  • Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates Reviewed International journal

    Yan A., Liu R., Huang Z., Girard P., Wen X.

    Electronics (Switzerland)   11 ( 10 )   2022.05

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.3390/ELECTRONICS11101658

    Scopus

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  • Evaluation and Test of Production Defects in Hardened Latches Reviewed International journal

    MA Ruijun, HOLST Stefan, WEN Xiaoqing, YAN Aibin, XU Hui

    IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers )   E105D ( 5 )   996 - 1009   2022.01

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    Language:English   Publishing type:Research paper (scientific journal)

    <p>As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (<i>PTVF</i>), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed <i>PTVF</i> metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.</p>

    DOI: 10.1587/transinf.2021EDP7216

    Scopus

    CiNii Research

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  • MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator Reviewed International journal

    Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wen X.

    Proceedings of the 2022 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2022   2022.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/AsianHOST56390.2022.10022291

    Scopus

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  • A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage Reviewed

    Yan A., Dingl L., Zhou Z., Huang Z., Cui J., Girard P., Wen X.

    Proceedings of the Asian Test Symposium   2022-November   1 - 6   2022.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS56056.2022.00013

    Scopus

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  • GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators Reviewed International journal

    Holst S., Bumun L., Wen X.

    Proceedings of the Asian Test Symposium   2021-November   127 - 132   2021.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS52891.2021.00034

    Scopus

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  • A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications Reviewed International journal

    Yan A., Wei S., Zhang J., Cui J., Song J., Ni T., Girard P., Wen X.

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   167 - 171   2023.06

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1145/3583781.3590281

    Scopus

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  • Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications Reviewed International journal

    Yan A., Chang Y., Xiang J., Luo H., Cui J., Huang Z., Ni T., Wen X.

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   293 - 298   2023.06

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1145/3583781.3590261

    Scopus

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  • Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array Reviewed International journal

    Chen N., Cheng F., Han C., Jiang J., Wen X.

    Tsinghua Science and Technology   28 ( 2 )   330 - 343   2023.04

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.26599/TST.2022.9010001

    Scopus

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  • A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design Reviewed International journal

    Yan A., Wei S., Chen Y., Fan Z., Huang Z., Cui J., Girard P., Wen X.

    Micromachines   13 ( 11 )   2022.11

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.3390/mi13111802

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  • A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications Reviewed International journal

    Yan A., Qian K., Song T., Huang Z., Ni T., Chen Y., Wen X.

    Integration   86   22 - 29   2022.09

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1016/j.vlsi.2022.04.008

    Scopus

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  • A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology Reviewed International journal

    Yan A., Zhou Z., Wei S., Cui J., Zhou Y., Ni T., Girard P., Wen X.

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   255 - 260   2022.06

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1145/3526241.3530321

    Scopus

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  • Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications Reviewed International journal

    Yan A., He Z., Xiang J., Cui J., Zhou Y., Huang Z., Girard P., Wen X.

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   261 - 266   2022.06

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1145/3526241.3530312

    Scopus

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  • Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications Reviewed International journal

    Yan A., Chen Y., Song S., Zhai Z., Cui J., Huang Z., Girard P., Wen X.

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   333 - 338   2022.06

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1145/3526241.3530355

    Scopus

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  • A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center Reviewed International journal

    Saxena D., Gupta I., Kumar J., Singh A.K., Wen X.

    IEEE Systems Journal   16 ( 2 )   3163 - 3174   2022.06

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/JSYST.2021.3092521

    Scopus

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  • Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications Reviewed International journal

    Yan A., Xiang J., Cao A., He Z., Cui J., Ni T., Huang Z., Wen X., Girard P.

    IEEE Transactions on Device and Materials Reliability   22 ( 2 )   282 - 295   2022.06

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TDMR.2022.3175324

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  • Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications Reviewed International journal

    Yan A., Fan Z., Ding L., Cui J., Huang Z., Wang Q., Zheng H., Girard P., Wen X.

    IEEE Transactions on Aerospace and Electronic Systems   58 ( 1 )   517 - 529   2022.02

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TAES.2021.3103586

    Scopus

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  • SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments Reviewed International journal

    Yan A., Li Z., Huang S., Zhai Z., Cheng X., Cui J., Ni T., Wen X., Girard P.

    Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022   1257 - 1262   2022.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.23919/DATE54114.2022.9774665

    Scopus

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  • Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments Reviewed International journal

    Yan A., Xu Z., Feng X., Cui J., Chen Z., Ni T., Huang Z., Girard P., Wen X.

    IEEE Transactions on Emerging Topics in Computing   10 ( 1 )   404 - 413   2022.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TETC.2020.3025584

    Scopus

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  • Broadcast-TDMA: A Cost-Effective Fault Tolerance Method for TSV Lifetime Reliability Enhancement Reviewed International journal

    Ni T., Bian J., Yang Z., Nie M., Yao L., Huang Z., Yan A., Wen X.

    IEEE Design and Test   2022.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/MDAT.2022.3189827

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  • A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications Reviewed International journal

    Yan A., Qian K., Cui J., Cui N., Huang Z., Wen X., Girard P.

    Proceedings of the IEEE VLSI Test Symposium   2022-April   2022.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/VTS52500.2021.9794197

    Scopus

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  • Power-Aware Testing in the Era of IoT Reviewed International journal

    Wen X.

    Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022   2022.01

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    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ICSICT55466.2022.9963241

    Scopus

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  • Power and Energy Safe Real-Time Multi-Core Task Scheduling Reviewed International journal

    Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

    Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022   16 - 21   2022.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/VLSID2022.2022.00016

    Scopus

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  • Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits Reviewed International journal

    Utsunomiya T., Hoshino R., Miyase K., Lu S.K., Wen X., Kajihara S.

    Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022   43 - 48   2022.01

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    DOI: 10.1109/ITCAsia55616.2022.00018

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  • Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS Reviewed International journal

    Yan A., Song S., Zhang J., Cui J., Huang Z., Ni T., Wen X., Girard P.

    Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022   73 - 78   2022.01

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    DOI: 10.1109/ITCAsia55616.2022.00023

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  • A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters Reviewed International journal

    Yan A., Song S., Chen Y., Cui J., Huang Z., Wen X.

    Proceedings of the IEEE Conference on Nanotechnology   2022-July   215 - 218   2022.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/NANO54668.2022.9928674

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  • A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC Reviewed International journal

    Ni T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   40 ( 9 )   1952 - 1956   2021.09

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2020.3025169

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  • Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications Reviewed International journal

    Yan A., Cao A., Xu Z., Cui J., Ni T., Girard P., Wen X.

    Journal of Electronic Testing: Theory and Applications (JETTA)   37 ( 4 )   489 - 502   2021.08

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1007/s10836-021-05962-0

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  • A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments Reviewed

    Yan A., Cao A., Fan Z., Xu Z., Ni T., Girard P., Wen X.

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI   301 - 306   2021.06

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1145/3453688.3461493

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  • Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications Reviewed

    Yan A., He Z., Zhou J., Cui J., Ni T., Huang Z., Wen X., Girard P.

    Microelectronics Journal   111   2021.05

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1016/j.mejo.2021.105034

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  • A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology Reviewed

    Ni T., Yang Z., Chang H., Zhang X., Lu L., Yan A., Huang Z., Wen X.

    IEEE Transactions on Emerging Topics in Computing   9 ( 2 )   724 - 734   2021.04

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TETC.2020.2969237

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  • Reliability-Driven Neuromorphic Computing Systems Design Reviewed

    Xu Q., Wang J., Geng H., Chen S., Wen X.

    Proceedings -Design, Automation and Test in Europe, DATE   2021-February   1586 - 1591   2021.02

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.23919/DATE51398.2021.9473929

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  • TPDICE and SIM based 4-node-upset completely hardened latch design for highly robust computing in harsh radiation Reviewed

    Yan A., Ding L., Shan C., Cai H., Chen X., Wei Z., Huang Z., Wen X.

    Proceedings - IEEE International Symposium on Circuits and Systems   2021-May   2021.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ISCAS51556.2021.9401453

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  • On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption Reviewed

    Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

    IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers )   E104D ( 6 )   816 - 827   2021.01

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    <p>Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.</p>

    DOI: 10.1587/transinf.2020EDP7042

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    CiNii Article

    CiNii Research

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  • Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS Reviewed

    Yan A., Lai C., Zhang Y., Cui J., Huang Z., Song J., Guo J., Wen X.

    IEEE Transactions on Emerging Topics in Computing   9 ( 1 )   520 - 533   2021.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TETC.2018.2871861

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  • Cellular Structure Based Fault-Tolerance TSV Configuration in 3D-IC Reviewed

    Xu Q., Sun W., Chen S., Kang Y., Wen X.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   41 ( 5 )   1196 - 1208   2021.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2021.3084920

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  • Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing Reviewed International journal

    Yan A., Zhai Z., Wang L., Zhang J., Cui N., Ni T., Wen X.

    Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021   2021.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC-Asia53059.2021.9808602

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  • LSI Testing: A Core Technology to a Successful LSI Industry Invited Reviewed International journal

    Wen X.

    Proceedings of International Conference on ASIC   2021.01

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    DOI: 10.1109/ASICON52560.2021.9620418

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  • GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning Reviewed International journal

    Xu Q., Geng H., Chen S., Yuan B., Zhuo C., Kang Y., Wen X.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   41 ( 10 )   3492 - 3502   2021.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2021.3131550

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  • Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure Reviewed International journal

    Xu Q., Ni T., Geng H., Chen S., Yu B., Kang Y., Wen X.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   41 ( 10 )   3182 - 3187   2021.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2021.3133484

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  • A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch Reviewed International journal

    Yan A., Qian K., Cui J., Cui N., Ni T., Huang Z., Wen X.

    2021 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021   2021.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/NANOARCH53687.2021.9642250

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  • A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets Reviewed International journal

    Yan A., Cao A., Qian K., Ding L., He Z., Fan Z., Wen X.

    Proceedings - 2021 8th International Conference on Dependable Systems and Their Applications, DSA 2021   734 - 736   2021.01

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    DOI: 10.1109/DSA52907.2021.00108

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  • Novel Speed-and-Power-Optimized SRAM Cell Designs with Enhanced Self-Recoverability from Single- And Double-Node Upsets Reviewed

    Yan A., Chen Y., Hu Y., Zhou J., Ni T., Cui J., Girard P., Wen X.

    IEEE Transactions on Circuits and Systems I: Regular Papers   67 ( 12 )   4684 - 4695   2020.12

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCSI.2020.3018328

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  • A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets Reviewed

    Yan A., Chen Y., Zhou J., Cui J., Ni T., Wen X., Girard P.

    Proceedings of the Asian Test Symposium   2020-November   2020.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS49688.2020.9301569

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  • Logic Fault Diagnosis of Hidden Delay Defects Reviewed

    Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

    Proceedings - International Test Conference   2020-November   2020.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC44778.2020.9325234

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  • Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC Reviewed

    Ni T., Chang H., Song T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

    IEEE Transactions on Circuits and Systems II: Express Briefs   67 ( 11 )   2657 - 2661   2020.11

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    DOI: 10.1109/TCSII.2019.2962824

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  • Design of double-upset recoverable and transient-pulse filterable latches for low-power and low-orbit aerospace applications Reviewed

    Yan A., Chen Y., Xu Z., Chen Z., Cui J., Huang Z., Girard P., Wen X.

    IEEE Transactions on Aerospace and Electronic Systems   56 ( 5 )   3931 - 3940   2020.10

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TAES.2020.2982341

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  • Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors Reviewed

    Dou Z., Yan A., Zhou J., Hu Y., Chen Y., Ni T., Cui J., Girard P., Wen X.

    Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020   35 - 40   2020.09

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC-Asia51099.2020.00018

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  • A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications Reviewed

    Yan A., Xu Z., Yang K., Cui J., Huang Z., Girard P., Wen X.

    IEEE Transactions on Aerospace and Electronic Systems   56 ( 4 )   2666 - 2676   2020.08

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TAES.2019.2951186

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  • HITTSFL: Design of a cost-effective HIS-Insensitive TNU-Tolerant and SET-Filterable latch for safety-critical applications Reviewed

    Yan A., Feng X., Zhao X., Zhou H., Cui J., Ying Z., Girard P., Wen X.

    Proceedings - Design Automation Conference   2020-July   2020.07

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/DAC18072.2020.9218704

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  • Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment Reviewed

    Yan A., Hu Y., Cui J., Chen Z., Huang Z., Ni T., Girard P., Wen X.

    IEEE Transactions on Computers   69 ( 6 )   789 - 799   2020.06

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TC.2020.2966200

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  • Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments Reviewed

    Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

    IEEE Transactions on Aerospace and Electronic Systems   56 ( 2 )   1163 - 1171   2020.04

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TAES.2019.2925448

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  • Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs Reviewed

    Yan A., Ling Y., Cui J., Chen Z., Huang Z., Song J., Girard P., Wen X.

    IEEE Transactions on Circuits and Systems I: Regular Papers   67 ( 3 )   879 - 890   2020.03

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCSI.2019.2959007

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  • Dual-interlocked-storage-cell-based double-node-upset self-recoverable flip-flop design for safety-critical applications Reviewed

    Yan A., Xu Z., Cui J., Ying Z., Huang Z., Liang H., Girard P., Wen X.

    Proceedings - IEEE International Symposium on Circuits and Systems   2020-October   2020.01

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  • Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications Reviewed

    Yan A., Wu Z., Zhou J., Hu Y., Chen Y., Ying Z., Wen X., Girard P.

    Proceedings of the Asian Test Symposium   2019-December   55 - 60   2019.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS47505.2019.00006

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  • Targeted partial-shift for mitigating shift switching activity hot-spots during scan test Reviewed

    Holst S., Shi S., Wen X.

    Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC   2019-December   124 - 129   2019.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/PRDC47002.2019.00042

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  • Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications Reviewed

    Yan A., Wu Z., Lu L., Chen Z., Song J., Ying Z., Girard P., Wen X.

    Proceedings of the Asian Test Symposium   2019-December   43 - 48   2019.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS47505.2019.000-2

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  • Variation-aware small delay fault diagnosis on compressed test responses Reviewed

    Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

    Proceedings - International Test Conference   2019-November   2019.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC44170.2019.9000143

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  • A fault-tolerant MPSoC for CubeSats Reviewed International journal

    Fuchs C., Chou P., Wen X., Murillo N., Furano G., Holst S., Tavoularis A., Lu S., Plaat A., Marinis K.

    2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019   2019.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/DFT.2019.8875417

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  • A static method for analyzing hotspot distribution on the LSI Reviewed

    Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

    Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   73 - 78   2019.09

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC-Asia.2019.00026

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  • A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells Reviewed International journal

    Song Z., Yan A., Cui J., Chen Z., Li X., Wen X., Lai C., Huang Z., Liang H.

    Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019   139 - 144   2019.09

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ITC-Asia.2019.00037

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  • Power-Aware Testing for Low-Power VLSI Circuits Invited Reviewed International journal

    X. Wen

    15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits   Paper S12-1   2019.06

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    China   Xi'an   2019.06.12  -  2019.06.14

  • Small Delay Fault Diagnosis with Compacted Responses Reviewed International journal

    S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich

    Poster at ACM Design Automation Conf.   2019.06

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  • Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications Reviewed International journal

    Yan A., Hu Y., Song J., Wen X.

    Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019   1679 - 1684   2019.05

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.23919/DATE.2019.8714841

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  • STAHL: A novel scan-test-aware hardened latch design Reviewed International journal

    Ma R., Holst S., Wen X., Yan A., Xu H.

    Proceedings of the European Test Workshop   2019-May   2019.05

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ETS.2019.8791544

    Kyutacar

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  • Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout Reviewed International journal

    Yan A., Wu Z., Guo J., Song J., Wen X.

    IEEE Transactions on Reliability   68 ( 1 )   354 - 363   2019.03

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TR.2018.2876243

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  • LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults Reviewed International journal

    Ni T., Yao Y., Chang H., Lu L., Liang H., Yan A., Huang Z., Wen X.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   39 ( 10 )   2938 - 2951   2019.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2019.2946243

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  • Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets Reviewed

    Yan A., Zhou J., Hu Y., Cui J., Huang Z., Girard P., Wen X.

    IEEE Access   7   176188 - 176196   2019.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/ACCESS.2019.2958109

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  • Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed International journal

    Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

    Proceedings of the Asian Test Symposium   2018-October   149 - 154   2018.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    DOI: 10.1109/ATS.2018.00037

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  • The impact of production defects on the soft-error tolerance of hardened latches Reviewed International journal

    Holst S., Ma R., Wen X.

    Proceedings of the European Test Workshop   2018-May   1 - 6   2018.06

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    DOI: 10.1109/ETS.2018.8400694

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  • Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM Reviewed International journal

    I. Syafalni, T. Sasao, X. Wen

    Proceedings of the 27th International Workshop on Logic and Synthesis   124 - 131   2018.06

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    USA   San Francisco   2018.06.23  -  2018.06.24

  • A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application Reviewed International journal

    A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

    IEEE Transactions on Circuits and Systems II: Express Briefs   66 ( 2 )   287 - 291   Early Access   2018.06

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    DOI: 10.1109/TCSII.2018.2849028

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  • A Method to Detect Bit Flips in a Soft-Error Resilient TCAM Reviewed International journal

    I. Syafalni, T. Sasao, X. Wen

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   37 ( 6 )   1185 - 1196   2018.06

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2017.2748019

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  • The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches Reviewed International journal

    S. Holst, R. Ma, X. Wen

    Proceedings of IEEE European Test Symposium   Paper 7A-1   2018.05

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    Germany   Bremen   2018.05.28  -  2018.06.01

  • Design Automation for Legacy Circuits Reviewed International journal

    I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

    Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies   174 - 179   2018.03

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    Japan   Matsue   2018.03.26  -  2018.03.27

  • Locating Hot Spot with Justification Techniques in a Layout Design Reviewed International journal

    K. Miyase, Y. Kawano, X. Wen, S. Kajihara

    Proceedings of IEEE Workshop on RTL and High Level Testing   Paper S1.2   2017.11

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    Taiwan   Taipei   2017.11.30  -  2017.12.01

  • Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption Reviewed International journal

    Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian

    Proceedings of the Asian Test Symposium   140 - 145   2017.11

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    Taiwan   Taipei   2017.11.27  -  2017.11.30

    DOI: 10.1109/ATS.2017.37

    Kyutacar

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  • Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors Reviewed International journal

    S. Holst, E. Schneider, H. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen

    Proceedings - International Test Conference   2017-December   1 - 8   Paper 3.4   2017.10

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    USA   Fort Warth   2017.10.29  -  2017.11.03

    DOI: 10.1109/TEST.2017.8242055

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  • A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips Reviewed International journal

    T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

    IEEE Transactions on Emerging Topics in Computing   8 ( 3 )   591 - 601   Early Access   2017.10

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TETC.2017.2767070

    Kyutacar

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  • Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs Reviewed International journal

    T. Ni, M. Nie, H. Liang, J. Bian, X. Xu, X. Fang, Z. Huang, X. Wen

    IEICE Electronics Express   18 ( 14 )   Letter 20170590   2017.10

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    Kyutacar

  • GPU-Accelerated Simulation of Small Delay Faults Reviewed International journal

    E. Schneider, M. Kochte, S. Holst, X. Wen, H. Wunderlich

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   36 ( 5 )   829 - 841   2017.05

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2016.2598560

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  • On Optimal Power-Aware Path Sensitization Reviewed International journal

    Workshop of Test and Reliability for Circuits and Systems   2017.03

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    Germany   2017.03.05  -  2017.03.07

  • Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding Reviewed International journal

    Xiang D., Wen X., Wang L.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   25 ( 3 )   942 - 953   2017.03

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TVLSI.2016.2606248

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  • Vernier ring based pre-bond through silicon vias test in 3D ICs Reviewed International journal

    Ni Tianming, Nie Mu, Liang Huaguo, Bian Jingchang, Xu Xiumin, Fang Xiangsheng, Huang Zhengfeng, Wen Xiaoqing

    IEICE Electronics Express ( The Institute of Electronics, Information and Communication Engineers )   14 ( 18 )   20170590 - 20170590   2017.01

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    <p>Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.</p>

    DOI: 10.1587/elex.14.20170590

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  • Logic-Path-and-Clock-Path-Aware at-Speed Scan Test Generation Reviewed International journal

    F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara

    2016.12

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    Japan   Kita-Kyushu   2016.12.18  -  2016.12.18

  • Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Reviewed International journal

    LI Fuqiang, WEN Xiaoqing, MIYASE Kohei, HOLST Stefan, KAJIHARA Seiji

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( The Institute of Electronics, Information and Communication Engineers )   E99A ( 12 )   2310 - 2319   2016.12

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    <p>Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called <i>LP-CP-aware ATPG</i>, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) <i>LP-CP-aware path classification</i> for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) <i>LP-CP-aware X-restoration</i> for obtaining more effective <i>X</i>-bits by backtracing from both logic and clock paths; (3) <i>LP-CP-aware X-filling</i> for using different strategies according to the positions of <i>X</i>-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power-safety without significant test vector count inflation and test quality loss.</p>

    DOI: 10.1587/transfun.E99.A.2310

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  • A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST Reviewed International journal

    T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

    IEEE Asian Test Symposium   203 - 208   2016.11

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    Japan   Hiroshima   2016.11.21  -  2016.11.24

    DOI: 10.1109/ATS.2016.59

    Kyutacar

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  • Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed International journal

    Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.

    IEEE Asian Test Symposium   19 - 24   2016.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Hiroshima   2016.11.21  -  2016.11.24

    DOI: 10.1109/ATS.2016.49

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  • On Optimal Power-Aware Path Sensitization Reviewed International journal

    Sauer M., Jiang J., Reimer S., Miyase K., Wen X., Becker B., Polian I.

    IEEE Asian Test Symposium   179 - 184   2016.11

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    Japan   Hiroshima   2016.11.21  -  2016.11.24

    DOI: 10.1109/ATS.2016.63

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  • Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test Reviewed International journal

    Eggersglub S., Holst S., Tille D., Miyase K., Wen X.

    Proceedings of the Asian Test Symposium   173 - 178   2016.11

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    Japan   Hiroshima   2016.11.21  -  2016.11.24

    DOI: 10.1109/ATS.2016.41

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  • Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures Reviewed International journal

    CHEN Tian, SHEN Dandan, YI Xin, LIANG Huaguo, WEN Xiaoqing, WANG Wei

    IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers )   E99D ( 11 )   2672 - 2681   2016.11

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    <p>Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, X-filling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.</p>

    DOI: 10.1587/transinf.2015EDP7289

    Kyutacar

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  • Power-Aware Testing For Low-Power VLSI Circuits Invited Reviewed International journal

    X. Wen

    2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings   585 - 588   Paper S37-1   2016.10

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    China   Hangzhou   2016.10.25  -  2016.10.28

    DOI: 10.1109/ICSICT.2016.7998986

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  • Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM Reviewed International journal

    Syafalni I., Sasao T., Wen X.

    Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI   2016-September   679 - 684   2016.07

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    USA   Pittsburgh   2016.07.11  -  2016.07.13

    DOI: 10.1109/ISVLSI.2016.77

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  • SAT-Based Post-Processing for Regional Capture Power Reduction in at-speed scan test generation Reviewed International journal

    Eggersgluss S., Miyase K., Wen X.

    IEEE European Test Symposium   2016-July   2016.05

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Netherlands   Amsterdam   2016.05.23  -  2016.05.27

    DOI: 10.1109/ETS.2016.7519327

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  • Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill Reviewed International journal

    D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   35 ( 3 )   499 - 512   2016.03

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2015.2474365

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  • Test Pattern Modification for Average IR-Drop Reduction Reviewed International journal

    W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen

    IEEE Transactions on VLSI Systems   24 ( 1 )   38 - 49   2016.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TVLSI.2015.2391291

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  • Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch Reviewed International journal

    IEEE Asian Test Symposium   103 - 108   2015.11

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    India   Bombay   2015.11.22  -  2015.11.25

    DOI: 10.1109/ATS.2015.25

    Kyutacar

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  • Power Supply Noise and Its Reduction in At-Speed Scan Testing Invited Reviewed International journal

    X. Wen

    IEEE International Conference on ASIC   Paper B5-3   2015.11

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    China   Chengdu   2015.11.03  -  2015.11.06

    DOI: 10.1109/ASICON.2015.7516980

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  • A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys Reviewed International journal

    I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

    24th International Workshop on Logic and Synthesis   2015.06

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    USA   Mountain View   2015.06.12  -  2015.06.13

  • Identification of High Power Consuming Areas with Gate Type and Logic Level Information Reviewed International journal

    K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

    IEEE European Test Symposium   Paper 9.1   2015.05

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    Romania   Cluj-Napoca   2015.05.25  -  2015.05.29

    DOI: 10.1109/ETS.2015.7138773

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  • A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys Reviewed International journal

    IEEE European Test Symposium   Poster 2.4   2015.05

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    Romania   Cluj-Napoca   2015.05.25  -  2015.05.29

    DOI: 10.1109/ETS.2015.7138743

    Scopus

  • GPU-Accelerated Small Delay Fault Simulation Reviewed International journal

    E. Schneider, S. Holst, M.-A. Kochte, X. Wen, H.-J. Wunderlich

    Design and Test in Europe   1174 - 1179   2015.03

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    France   Grenoble   2015.03.09  -  2015.03.13

  • Towards Memory-Aware VLSI Simulation Algorithms for Heterogeneous Architectures Reviewed International journal

    S. Holst, J. Miyazaki, X. Wen

    International Symposium on Applied Engineering and Sciences   2014.12

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    Japan   Kita-Kyushu   2014.12.20  -  2014.12.21

  • Soft-Error Tolerant TCAMs for High-Reliability Packet Classification Reviewed International journal

    IEEE Asia Pacific Conference on Circuits and Systems   471 - 474   2014.11

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    Japan   Ishigaki   2014.11.17  -  2014.11.20

    DOI: 10.1109/APCCAS.2014.7032821

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  • Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal

    E. Schneider, S. Holst, X. Wen, H. Wunderlich

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD   17 - 23   2014.11

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    USA   San Jose   2014.11.02  -  2014.11.06

    DOI: 10.1109/ICCAD.2014.7001324

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  • On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed International journal

    A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

    IEICE Transactions on Information and Systems   E97 ( 10 )   2706 - 2718   2014.10

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    DOI: 10.1587/transinf.2014EDP7039

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  • An X-Filling Method for Low-Capture-Power Scan Test Generation

    Li Fuqiang, Wen Xiaoqing, Miyase Kohei, Holst Stefan, Kajihara Seiji

    IEICE technical report. Dependable computing ( The Institute of Electronics, Information and Communication Engineers )   114 ( 99 )   15 - 20   2014.06

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    In order to generate a low capture power test pattern, we propose an X-filling method to suppress local switching activity (LSA), which is a local signal value transition metric that has a strong correlation with IR-Drop. In this method, after having divided the layout of a circuit into unit areas and then determined the priorities of X bits in a test cube based on the LSA of each unit area, we assign to X bits appropriate logic values which are easy to propagate. Experimental results show that the proposed method can effectively reduce the LSA in unit areas.

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  • Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal

    E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

    ACM Design Automation Conference   Poster   2014.06

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    USA   San Francisco   2014.06.01  -  2014.06.05

  • Low-power testing for 2D/3D devices and systems Reviewed International journal

    235 - 277   2014.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1201/9781315215709

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  • ATPG Enhancement Technology Reviewed International journal

    IEEE Workshop on RTL and High Level Testing   Paper IV.5.S   2013.11

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    Taiwan   Yilan   2013.11.21  -  2013.11.22

  • On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed International journal

    A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

    IEEE Asian Test Symposium   19 - 24   2013.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Jiaosi   2013.11.18  -  2013.11.21

    DOI: 10.1109/ATS.2013.14

    Kyutacar

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  • Search Space Reduction for Low-Power Test Generation Reviewed International journal

    IEEE Asian Test Symposium   171 - 176   2013.11

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    Taiwan   Jiaosi   2013.11.18  -  2013.11.21

    DOI: 10.1109/ATS.2013.40

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  • Test Pattern Modification for Average IR-drop Reduction Reviewed International journal

    J. Li, W-S. Ding, H-Y. Hsieh, X. Wen

    IEEE International Test Conference   Poster   2013.09

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    USA   Anaheim, CA   2013.09.06  -  2013.09.13

  • A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Reviewed International journal

    K. Miyase, R. Sakai, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

    IEICE Transaction on Information and Systems   E96-D ( 9 )   2003 - 2011   2013.09

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    DOI: 10.1587/transinf.E96.D.2003

    Kyutacar

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  • SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction Reviewed International journal

    Y.-T. Lin, J.-L. Huang, X. Wen

    VLSI Test Technology Workshop   Paper 4.4   2013.07

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    Taiwan   New Taipei City   2013.07.15  -  2013.07.17

  • Controllability Analysis of Local Switching Activity for Layout Design Reviewed International journal

    K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

    Workshop on Design and Test Methodologies for Emerging Technologies   Paper 2   2013.05

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    France   Avignon   2013.05.30  -  2013.05.31

  • LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing Reviewed International journal

    Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

    IEEE Design & Test of Computers   30 ( 4 )   60 - 70   2013.04

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    DOI: 10.1109/MDT.2012.2221152

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  • On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression Reviewed International journal

    26th International Conference on VLSI Design   279 - 284   2013.01

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    India   Pune   2013.01.05  -  2013.01.10

    DOI: 10.1109/VLSID.2013.201

    Kyutacar

    Scopus

  • Fault Detection with Optimum March Test Algorithm Reviewed International journal

    N. Zakaria, W. Hassan, I. Halin, R. Sidek, X. Wen

    Journal of Theoretical and Applied Information Technology   47 ( 1 )   18 - 27   2013.01

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    Kyutacar

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  • Estimation of the Amount of Don't-Care Bits in Test Vectors Reviewed International journal

    K. Miyase, S. Kajihara, X. Wen

    IEEE Workshop on RTL and High Level Testing   2012.11

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    Japan   Niigata   2012.11.22  -  2012.11.23

  • A Transition Isolation Scan Cell Design for Low Shift and Capture Power Reviewed International journal

    Y.-T. Lin, J.-L Huang, X. Wen

    IEEE Asian Test Symposium   107 - 112   2012.11

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    Japan   Niigata   2012.11.19  -  2012.11.22

    DOI: 10.1109/ATS.2012.29

    Scopus

  • On Pinpoint Capture Power Management in At-Speed Scan Test Generation Reviewed International journal

    X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

    IEEE International Test Conference   Paper 6.1   2012.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Anaheim   2012.11.05  -  2012.11.08

    DOI: 10.1109/TEST.2012.6401548

    Kyutacar

    Scopus

  • Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal

    S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang

    ACM Transactions on Design Automation of Electronic Systems   17 ( 4 )   Article No. 48   2012.10

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    DOI: 10.1145/2348839.2348852

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  • A Transition Isolation Scan Cell Design for Low Shift and Capture Power Reviewed International journal

    Y.-T. Lin, J.-L. Huang, X. Wen

    VLSI Test Technology Workshop   2012.07

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    Taiwan   Yilan   2012.07.10  -  2012.07.13

  • Power-Aware Testing: The Next Stage Invited Reviewed International journal

    X. Wen

    IEEE European Test Symposium   Invited Talk   2012.05

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    France   Annecy   2012.05.28  -  2012.06.01

    DOI: 10.1109/ETS.2012.6233000

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  • A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits Reviewed International journal

    K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara

    IEEE VLSI Test Symposium   197 - 202   2012.04

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    USA   Hawaii   2012.04.23  -  2012.04.26

    DOI: 10.1109/VTS.2012.6231102

    Scopus

  • Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns Reviewed International journal

    H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

    ASP Journal of Lower Power Electronics   8 ( 2 )   248 - 258   2012.04

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1166/jolpe.2012.1188

    Scopus

  • Fault Detection with Optimum March Test Algorithm Reviewed International journal

    N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

    IEEE International Conference on Intelligent Systems, Modeling and Simulation   Paper S8   2012.02

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    Malaysia   Sabah   2012.02.08  -  2012.02.10

    DOI: 10.1109/ISMS.2012.88

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  • Testing static single cell faults using static and dynamic data background Reviewed International journal

    N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

    IEEE Student Conference on Research and Development   1 - 6   2011.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Malaysia   Cyberjaya   2011.12.19  -  2011.12.20

    DOI: 10.1109/SCOReD.2011.6148694

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  • Additional Path Delay Fault Detection with Adaptive Test Data Reviewed International journal

    K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, S. Kajihara

    IEEE Workshop on RTL and High Level Testing   31 - 34   2011.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    India   Jaipur   2011.11.24  -  2011.11.26

  • Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling Reviewed International journal

    K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard

    IEEE Asian Test Symposium   90 - 95   2011.11

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    India   New Delhi   2011.11.20  -  2011.11.23

    DOI: 10.1109/ATS.2011.35

    Kyutacar

  • Efficient BDD-based Fault Simulation in Presence of Unknown Values Reviewed International journal

    M. A. Kochte, S. Kundu, K. Miyase, X. Wen, H.-J. Wunderlich

    IEEE Asian Test Symposium   383 - 388   2011.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    India   New Delhi   2011.11.20  -  2011.11.23

    DOI: 10.1109/ATS.2011.52

    Scopus

  • Power-Aware Test Pattern Generation for At-Speed LOS Testing Reviewed International journal

    A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase, X. Wen

    IEEE Asian Test Symposium   506 - 510   2011.11

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    India   New Delhi   2011.11.20  -  2011.11.23

    DOI: 10.1109/ATS.2011.50

    Scopus

  • Towards the Next Generation of Low-Power Test Technologies Reviewed International journal

    X. Wen

    IEEE International Conference on ASIC   Paper 1E-1   2011.10

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    China   Amoi   2011.10.25  -  2011.10.28

    DOI: 10.1109/ASICON.2011.6157164

    Scopus

  • Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing Reviewed International journal

    L.-T. Wang, N. A. Touba, M. S. Hsiao, J.-L. Huang, C.-M. Li, S. Wu, X. Wen, M. Bhattarai, F. Li, Z. Jiang

    IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits   Paper 5.4   2011.09

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    USA   Anaheim   2011.09.22  -  2011.09.23

  • A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing Reviewed International journal

    IEEE International Test Conference   Paper 12.1   2011.09

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    USA   Anaheim   2011.09.20  -  2011.09.22

    DOI: 10.1109/TEST.2011.6139162

    Kyutacar

    Scopus

  • Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing Reviewed International journal

    Y.-T. Lin, J.-L. Huang, X. Wen

    IEEE International Test Conference   Paper 2.3   2011.09

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    USA   Anaheim   2011.09.20  -  2011.09.22

    DOI: 10.1109/TEST.2011.6139132

    Kyutacar

    Scopus

  • SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures Reviewed International journal

    M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enokimoto, H.-J. Wunderlich

    IEEE International Symposium on Low Power Electronics and Design   33 - 38   2011.08

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    Japan   Fukuoka   2011.08.01  -  2011.08.03

    DOI: 10.1109/ISLPED.2011.5993600

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  • 低消費電力LSIのための低消費電力テスト技術 Invited Reviewed

    温暁青

    情報・システムソサイエティ誌 ( 電子情報通信学会 情報・システムソサイエティ )   16 ( 2 )   10 - 11   2011.08

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  • VLSI Testing and Test Power Reviewed International journal

    X. Wen

    Workshop on Low Power System on Chip   Paper 4.1   2011.07

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    USA   Orlando   2011.07.28  -  2011.07.28

    DOI: 10.1109/IGCC.2011.6008607

    Kyutacar

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  • Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing Reviewed International journal

    K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara

    IEICE Transactions on Information and Systems   E94-D ( 6 )   1216 - 1226   2011.06

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    DOI: 10.1587/transinf.E94.D.1216

    Kyutacar

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    CiNii Article

  • Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns Reviewed International journal

    H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

    IEEE International Workshop on Impact of Low-Power design on Test and Reliability   4 Pages   2011.05

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    Norway   Trodheim   2011.05.26  -  2011.05.27

  • Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme Reviewed International journal

    F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

    IEEE International Workshop on Impact of Low-Power design on Test and Reliability   4 Pages   2011.05

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    Norway   Trodheim   2011.05.26  -  2011.05.27

  • Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing Reviewed International journal

    X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, M. Tehranipoor

    IEEE VLSI Test Symposium   166 - 171   2011.05

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    USA   Dana Point   2011.05.01  -  2011.05.05

    DOI: 10.1109/VTS.2011.5783778

    Scopus

  • Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing Reviewed International journal

    F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

    6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era   1 - 6   2011.04

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    Greece   Athens   2011.04.06  -  2011.04.08

    DOI: 10.1109/DTIS.2011.5941434

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  • A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing Reviewed International journal

    IEICE Transactions on Information and Systems   E94-D ( 4 )   833 - 840   2011.04

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    DOI: 10.1587/transinf.E94.D.833

    Kyutacar

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    CiNii Article

  • Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation Reviewed International journal

    K. Miyase, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

    Design, Automation and Test in Europe   895 - 898   2011.03

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    France   Grenoble   2011.03.14  -  2011.03.18

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  • Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal

    S. Wu,L.-T. Wang,X. Wen,Z. Jiang,M. Hsiao,W.-B. Jone,L. Tan,Y. Zhang,Y. Hu,C.-M. Li,Member,J.-L. Huang,L. Yu

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   30 ( 3 )   455 - 463   2011.03

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2010.2092510

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  • X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme Reviewed International journal

    K. Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara

    IEEE Workshop on RTL and High Level Testing   125 - 129   2010.12

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    China   Shanghai   2010.12.05  -  2010.12.06

  • Hybrid Memory Built-In Self-Test Architecture for Multi-port Static RAMs Reviewed International journal

    L. Yu, J. Hung, B. Sheu, B. Huynh, L. Nguyen, S. Wu, L.-T. Wang, X. Wen

    IEEE Int Symposium on Defect and Fault Tolerance in VLSI Systems   331 - 339   2010.11

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    Japan   Kyoto   2010.11.06  -  2010.11.08

    DOI: 10.1109/DFT.2010.47

  • Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver Reviewed International journal

    K. Miyase,M. A. Kochte,X. Wen,S. Kajihara,H.-J. Wunderlich

    IEEE Workshop on Defect and Date Driven Testing   4 Pages   2010.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Austin   2010.11.04  -  2010.11.05

  • Is Test Power Reduction Through X-Filling Good Enough? Reviewed International journal

    F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

    IEEE International Test Conference   805 - 805   Poster   2010.11

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    USA   Austin   2010.11.02  -  2010.11.04

    DOI: 10.1109/TEST.2010.5699297

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  • On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test Reviewed International journal

    S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, X. Wen

    10th International Symposium on Communications and Information Technologies   723 - 726   2010.10

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    Japan   Tokyo   2010.10.26  -  2010.10.29

    DOI: 10.1109/ISCIT.2010.5665084

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  • Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains Reviewed International journal

    S. Wu,L.-T. Wang,L. Yu,H. Furukawa,X. Wen,W.-B. Jone,N. A. Touba,F. Zhao,J. Liu,H.-J. Chao,F. Li,Z. Jiang

    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems   358 - 366   2010.10

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    Japan   Kyoto   2010.10.06  -  2010.10.08

    DOI: 10.1109/DFT.2010.50

    Scopus

  • Case Studies on Transition Fault Test Generation for At-Speed Scan Testing Reviewed International journal

    N. A. Zakariz, E. V. Bautista, S. M. Jusoh, W. F. Lee, X. Wen

    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems   180 - 188   2010.10

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    Japan   Kyoto   2010.10.06  -  2010.10.08

    DOI: 10.1109/DFT.2010.29

    Scopus

  • A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes Reviewed International journal

    F. Wu,L. Dilillo,A. Bosio,P. Girard,S. Pravossoudovitch,A. Virazel,M. Tehranipoor,X. Wen,N. Ahmed

    ASP Journal of Lower Power Electronics   6 ( 2 )   359 - 374   2010.08

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1166/jolpe.2010.1086

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  • On Delay Test Quality for Test Cubes Reviewed International journal

    S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen

    IPSJ Transactions on System LSI Design Methodology   3   283 - 291   2010.08

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    DOI: 10.2197/ipsjtsldm.3.283

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    CiNii Article

  • A Study of Capture-Safe Test Generation Flow for At-Speed Testing Reviewed International journal

    K. Miyase, X. Wen, S. Kajihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja

    IEICE Transactions on Information and Systems   E93-A ( 7 )   1309 - 1318   2010.07

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1587/transfun.E93.A.1309

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  • On Estimation of NBTI-Induced Delay Degradation Reviewed International journal

    M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura

    IEEE European Test Symposium   107 - 111   2010.05

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    Czech   Prague   2010.05.24  -  2010.05.28

    DOI: 10.1109/ETSYM.2010.5512772

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  • Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes Reviewed International journal

    F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, X. Wen

    IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems   376 - 381   2010.04

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    Austria   Vienna   2010.04.14  -  2010.04.16

    DOI: 10.1109/DDECS.2010.5491748

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  • High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Reviewed International journal

    K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L. Wang, M. Tehranipoor

    IEICE Transactions on Information and Systems   E93-D ( 1 )   2 - 9   2010.04

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    Kyutacar

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  • CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing Invited Reviewed International journal

    X. Wen, K. Enokimoto, K. Miyase, S. Kajihara, M. Aso, H. Furukawa

    Symposium II (International Semiconductor Technology Conference & China Semiconductor Technology International Conference)   197 - 202   2010.03

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    China   Shanghai   2010.03.18  -  2010.03.19

    DOI: 10.1149/1.3360619

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  • Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal

    L.-T. Wang,X. Wen,S. Wu,H. Furukawa,H.-J. Chao,B. Sheu,J. Guo,and W.-B. Jone

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   29 ( 2 )   299 - 312   2010.02

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    DOI: 10.1109/TCAD.2009.2035483

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  • A Path Selection Method for Delay Test Targeting Transistor Aging Reviewed International journal

    M. Noda,S. Kajihara,Y. Sato,K. Miyase,X. Wen,and Y. Miura

    IEEE International Workshop on Reliability Aware System Design and Test   57 - 61   2010.01

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    India   Bangalore   2010.01.07  -  2010.01.08

  • X-Identification According to Required Distribution for Industrial Circuits Reviewed International journal

    I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

    IEEE Workshop on RTL and High Level Testing   76 - 81   2009.11

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    Hong Kong   Hong Kong   2009.11.27  -  2009.11.28

  • CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing Reviewed International journal

    K. Enokimoto,X. Wen,Y. Yamato,K. Miyase,H. Sone,S. Kajihara,M. Aso,and H. Furukawa

    IEEE Asian Test Symposium   99 - 104   2009.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Taichung   2009.11.23  -  2009.11.26

    DOI: 10.1109/ATS.2009.22

    Kyutacar

  • A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing Reviewed International journal

    Y. Yamato,X. Wen,K. Miyase,H. Furukawa,and S. Kajihara

    IEEE 15th Pacific Rim International Symposium on Dependable Computing   81 - 86   2009.11

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    China   Shanghai   2009.11.16  -  2009.11.18

    DOI: 10.1109/PRDC.2009.21

    Kyutacar

  • Optimizing the Percentage of X-Bits to Reduce Switching Activity Reviewed International journal

    I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

    IEEE Workshop on Defect and Date Driven Testing   4 Pages   2009.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Austin   2009.11.05  -  2009.11.06

  • A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment Reviewed International journal

    K. Miyase,K. Noda,H. Ito,K. Hatayama,T. Aikyo,Y. Yamato,X. Wen,and S. Kajihara

    IEEE/ACM International Conference on Computer Aided Design   97 - 104   2009.11

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    USA   San Jose   2009.11.02  -  2009.11.05

    DOI: 10.1145/1687399.1687420

  • Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment Reviewed International journal

    M.-F. Wu,J.-L. Huang,X. Wen,K. Miyase

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems   28 ( 11 )   1767 - 1776   2009.11

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/TCAD.2009.2030440

  • シグナルインテグリティ考慮型LSIテストを目指して Invited Reviewed

    温 暁青

    信頼性学会誌   31 ( 7 )   498 - 505   2009.10

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Research paper (scientific journal)

    主要雑誌

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  • LSI回路の低キャプチャ電力テスト生成技術 Invited Reviewed

    温暁青

    情報・システムソサイエティ誌 ( 電子情報通信学会 情報・システムソサイエティ )   14 ( 2 )   16 - 16   2009.08

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (other)

  • On Calculation of Delay Range in Fault Simulation for Test Cubes Reviewed International journal

    S. Oku,S. Kajihara,K. Miyase,X. Wen,Y. Sato

    International Symposium on VLSI Design, Automation, and Test   64 - 67   2009.04

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Taiwan   Hsinchu   2009.04.28  -  2009.04.30

    DOI: 10.1109/VDAT.2009.5158096

  • Power-Aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing Invited Reviewed International journal

    Y. Yamato,X. Wen,K. Miyase,H. Furukawa,S. Kajihara

    Metrology, Reliability and Testing (International Semiconductor Technology Conference & China Semiconductor Technology International Conference)   231 - 236   2009.03

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    China   上海   2009.03.19  -  2009.03.20

  • Turbo1500: Core-Based Design for Test and Diagnosis Using IEEE Std. 1500 Reviewed International journal

    L..-T. Wang,R. Apte,S. Wu,B. Sheu,K.-J. Lee,X. Wen,W.-B. Jone,C.-H. Yeh,J. Guo,J. Liu,Y.-C. Sung

    IEEE Design & Test of Computers   26 ( 1 )   26 - 35   2009.01

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/MDT.2009.21

  • On Delay Calculation in 3-valued Fault Simulation Reviewed International journal

    S. Oku,S. Kajihara,K. Miyase,X. Wen,Y. Sato

    IEEE Workshop on RTL and High Level Testing   123 - 128   2008.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    日本   札幌   2008.11.27  -  2008.11.28

  • Practical Challenges in Logic BIST Implementation  Case Studies Reviewed International journal

    S. Wu,H. Furukawa,B. Sheu,L.-T. Wang,H.-J. Chao,L. Yu,X. Wen,M. Murakami

    IEEE Asian Test Symposium   265 - 265   2008.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Sapporo   2008.11.24  -  2008.11.27

    DOI: 10.1109/ATS.2008.59

  • CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing Reviewed International journal

    H. Furukawa,X. Wen,K. Miyase,Yuta Yamato,S. Kajihara,Patrick Girard,L.-T. Wang,M. Teharanipoor

    IEEE Asian Test Symposium   397 - 402   2008.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Sapporo   2008.11.24  -  2008.11.27

    DOI: 10.1109/ATS.2008.27

    Kyutacar

  • Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification Reviewed International journal

    K. Miyase,K. Noda,H. Ito,K. Hatayama,T. Aikyo,Y. Yamato,H. Furukawa,X. Wen,S. Kajihara

    IEEE/ACM International Conference on Computer Aided Design   52 - 58   2008.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   San Jose   2008.11.10  -  2008.11.13

    DOI: 10.1109/ICCAD.2008.4681551

  • GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing Reviewed International journal

    Y. Yamato,X. Wen,K. Miyase,H. Furukawa,S. Kajihara

    IEEE Workshop on Defect and Date Driven Testing   4 Pages   2008.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara   2008.10.30  -  2008.10.31

  • Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG Reviewed International journal

    J. Ma,J. Lee,M. Tehranipoor,X. Wen,A. Crouch

    IEEE Workshop on Defect and Date Driven Testing   7 Pages   2008.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara   2008.10.30  -  2008.10.31

  • Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing Reviewed International journal

    M.-F. Wu,J.-L. Huang,X. Wen,K. Miyase

    IEEE International Test Conference   Paper 13.1   2008.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara   2008.10.28  -  2008.10.30

    DOI: 10.1109/TEST.2008.4700584

  • Turbo1500: Toward Core-Based Design for Test and Diagnosis Using IEEE Std. 1500 Reviewed International journal

    L.-T. Wang,R. Apte,S. Wu,B. Sheu,K.-J. Lee,X. Wen,W.-B. Jone,C.-H. Yeh,J. Guo,J. Liu,Y.-C. Sung

    IEEE International Test Conference   Paper 29.3   2008.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara   2008.10.28  -  2008.10.30

    DOI: 10.1109/TEST.2008.4700630

  • On Optimizing Pattern Count and ATPG Time Using A Hybrid Single-Capture Scheme for Testing Scan Designs Reviewed International journal

    B. Sheu,L.-T. Wang,Z. Jiang,J. Soong,S. Wu,R. Apte,X. Wen,C.-M. Li

    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems   143 - 151   2008.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Cambridge   2008.10.01  -  2008.10.03

    DOI: 10.1109/DFT.2008.29

    Scopus

  • Test Strategies for Low-Power Devices Invited Reviewed International journal

    C. P. Ravikumar,M. Hirech,X. Wen

    Journal of Low Power Electronics   4 ( 2 )   127 - 138   2008.08

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1166/jolpe.2008.174

  • Estimation of Delay Test Quality and Its Application to Test Generation Reviewed International journal

    S. Kajihara,S. Morishima,M. Yamamoto,X. Wen,M. Fukunaga,K. Hatayama,T. Aikyo

    IPSJ Transaction of System LSI Design Methodology   1   104 - 115   2008.08

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.2197/ipsjtsldm.1.104

  • A Capture-Safe Test Generation Scheme for At-Speed Scan Testing Reviewed International journal

    X. Wen,K. Miyase,S. Kajihara,H. Furukawa,Y. Yamato,A. Takashima,K. Noda,H. Ito,K. Hatayama,T. Aikyo,K. K. Saluja

    IEEE European Test Symposium   55 - 60   2008.05

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Italy   Verbania   2008.05.25  -  2008.05.29

    DOI: 10.1109/ETS.2008.13

    Kyutacar

  • Diagnosis of Realistic Defects Based on X-Fault Model Reviewed International journal

    I. Polian,Y. Nakamura,P. Engelke,S. Spinner,K. Miyase,S. Kajihara,B. Becker,X. Wen

    IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems   263 - 266   2008.04

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Slovakia   Bratislava   2008.04.16  -  2008.04.18

    DOI: 10.1109/DDECS.2008.4538798

  • Test Strategies for Low-Power Devices Invited Reviewed International journal

    C. P. Ravikumar,M. Hirech,X. Wen

    Design Automation, and Test in Europe   728 - 733   2008.03

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Germany   Munich   2008.03.10  -  2008.03.14

    DOI: 10.1145/1403375.1403552

    Kyutacar

  • VirtualScan: A Test Compression Technology Using Combinational Logic and One-Pass ATPG Reviewed International journal

    L.-T. Wang,X. Wen,S. Wu,Z. Wang,Z. Jiang,B. Sheu,X. Gu

    IEEE Design & Test of Computers   25 ( 2 )   122 - 130   2008.03

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1109/MDT.2008.56

  • On Detection of Bridge Defects with Stuck-at Tests Reviewed International journal

    K. Miyase,K. Terashima,X. Wen,S. Kajiihara,and S. M Reddy

    IEICE Transactions on Information and Systems   E91-D ( 3 )   683 - 689   2008.03

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    Language:English   Publishing type:Research paper (scientific journal)

    Kyutacar

  • A Novel Per-Test Fault Diagnosis Method Based On the Extended X-Fault Model for Deep-Submicron LSI Circuits Reviewed International journal

    Y. Yamato,Y. Nakamura,K. Miyase,X. Wen,and S. Kajihara

    IEICE Transactions on Information and Systems   E91-D ( 3 )   667 - 674   2008.03

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    Language:English   Publishing type:Research paper (scientific journal)

    Kyutacar

  • Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing Reviewed International journal

    X. Wen,K. Miyase,T. Suzuki,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

    Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing   24 ( 4 )   379 - 391   2008.01

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1007/s10836-007-5033-3

  • Estimation of Delay Test Quality and Its Application to Test Generation Reviewed International journal

    S. Kajihara,S. Morishima,M. Yamamoto,X. Wen,M. Fukunaga,K. Hatayama,and T. Aikyo

    IEEE/ACM International Conference on Computer Aided Design   413 - 417   2007.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   San Jose, CA   2007.11.05  -  2007.11.08

  • A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set Reviewed International journal

    K. Miyase,X. Wen,S. Kajihara,M. Haraguchi,H. Furukawa

    IEEE International Workshop on Defect Based Testing   51 - 56   2007.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara, CA   2007.10.25  -  2007.10.26

  • A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing Reviewed International journal

    X. Wen,K. Miyase,S. Kajihara,T. Suzuki,Y. Yamato,P. Girard,Y. Ohsumi,and L.-T. Wang

    IEEE International Test Conference   25.1   2007.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara   2007.10.21  -  2007.10.26

    DOI: 10.1109/TEST.2007.4437632

    Kyutacar

  • A Novel ATPG Method for Capture Power Reduction During Scan Testing Reviewed International journal

    X. Wen,S. Kajiihara,K. Miyase,T. Suzuki,K. K. Saluja,L.-T. Wang,K. Kinoshita

    IEICE Transactions on Information and Systems   E90-D ( 9 )   1398 - 1405   2007.09

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    Kyutacar

  • Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing Reviewed International journal

    X. Wen,K. Miyase,T. Suzuki,S. Kajihara,Y. Ohsumi,K. K. Saluja

    IEEE/ACM Design Automation Conference   527 - 532   2007.06

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   San Diego   2007.06.04  -  2007.06.08

  • An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits Reviewed International journal

    X. Wen,Y. Yamato,K. Miyase,S. Kajihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

    IEEE Workshop on RTL and High Level Testing   55 - 60   2006.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    日本   福岡   2006.11.23  -  2006.11.24

    Kyutacar

  • Test Data Compression Based on Clustered Random Access Scan Reviewed International journal

    Y. Hu,C. Li,J. Li,Y. Han,X. Li,W. Wang,H. Li,L.-T. Wang,X. Wen

    IEEE Asian Test Symposium   231 - 236   2006.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Fukuoka   2006.11.20  -  2006.11.23

    DOI: 10.1109/ATS.2006.261025

  • A Per-Test Fault Diagnosis Method Based on the X-Fault Model Reviewed International journal

    X. Wen,S. Kajiihara,K. Miyase,Y. Yamato,L.-T. Wang,K. K. Saluja,K. Kinoshita

    IEICE Transactions on Information and System   E89-D ( 11 )   2756 - 2765   2006.11

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  • A Framework of High-quality Transition Fault ATPG for Scan Circuits Reviewed International journal

    S. Kajihara,S. Morishima,A. Takuma,X. Wen,T. Maeda,S. Hamada,Y. Sato

    IEEE International Test Conference   Paper 2.1   2006.10

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara   2006.10.24  -  2006.10.26

    DOI: 10.1109/TEST.2006.297683

  • A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing Reviewed International journal

    H. Furukawa,X. Wen,L.-T. Wang,B. Sheu,Z. Jiang,S. Wu

    IEEE International Test Conference   Paper 17.2   2006.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Santa Clara   2006.10.24  -  2006.10.26

    DOI: 10.1109/TEST.2006.297641

    Kyutacar

  • Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time Reviewed International journal

    Y. Hu,Y. Han,X. Li,H. Li,X. Wen

    IEICE Transactions on Information and Systems   E89-D ( 10 )   2616 - 2625   2006.10

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    Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1093/ietisy/e89-d.10.2616

    Kyutacar

  • A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation Reviewed International journal

    X. Wen,K. Miyase,T. Suzuki,Y. Yamato,S. Kajihara,L.-T. Wang,K. K. Saluja

    IEEE International Conference on Computer Design   251 - 258   2006.10

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    USA   San Jose   2006.10.01  -  2006.10.04

    DOI: 10.1109/ICCD.2006.4380825

    Kyutacar

  • Hybrid Fault Simulation with Compiled and Event-Driven Methods Reviewed International journal

    K. Taniguchi,H. Fujii,S. Kajihara,X. Wen

    IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology   240 - 243   2006.09

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    Tunisia   Tunis   2006.09.05  -  2006.09.07

    DOI: 10.1109/DTIS.2006.1708670

  • A New Method for Low-Capture-Power Test Generation for Scan Testing Reviewed International journal

    X. Wen,Y. Yamashita,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

    IEICE Transactions on Information and Systems   E89-D ( 5 )   1679 - 1686   2006.05

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    Kyutacar

  • A New ATPG Method for Efficient Capture Power Reduction During Scan Testing Reviewed International journal

    X. Wen,S. Kajihara,K. Miyase,T. Suzuki,K. K. Saluja,L.-T. Wang,K. S. Abdel-Hafez,K. Kinoshita

    IEEE VLSI Test Symposium   58 - 63   2006.04

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Berkeley   2006.04.30  -  2006.05.04

    DOI: 10.1109/VTS.2006.8

    Kyutacar

  • A Dynamic Test Compaction Procedure for High-quality Path Delay Testing Reviewed International journal

    M. Fukunaga,S. Kajihara,X. Wen,T. Maeda,S. Hamada,Y. Sato

    IEEE/ACM Asian and South Pacific Design Automation Conference   348 - 353   2006.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Yokohama   2006.01.23  -  2006.01.26

    DOI: 10.1145/1118299.1118388

  • On Improving Defect Coverage of Stuck-at Fault Tests Reviewed International journal

    K. Miyase, K. Terashima, S. Kajihara, X. Wen, S. M. Reddy

    IEEE Asian Test Symposium   216 - 223   2005.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    India   Calcutta   2005.12.18  -  2005.12.21

    DOI: 10.1109/ATS.2005.84

  • Compression/Scan Co-Design for Reducing Test Data Volume, Scan-In Power Dissipation and Test Application Time Reviewed International journal

    Y. Hu, Y. Han, X. Li, H. Li, X. Wen

    IEEE Pacific Rim International Symposium on Dependable Computing   8 - 8   2005.12

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    Language:English   Publishing type:Research paper (international conference proceedings)

    China   Changsha   2005.12.12  -  2005.12.14

    DOI: 10.1109/PRDC.2005.26

  • Efficient Test Set Modification for Capture Power Reduction Reviewed International journal

    X. Wen,T. Suzuki,S. Kajihara,K. Miyase,Y. Minamoto,L.-T. Wang,K. K. Saluja

    Jounal of Low Power Electrnics   1 ( 3 )   319 - 330   2005.12

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1166/jolpe.2005.042

    Kyutacar

  • Low-Capture-Power Test Generation for Scan-Based At-Speed Testing Reviewed International journal

    X. Wen,Y. Yamashita,S. Morishima,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

    IEEE International Test Conference   Paper 39.2   2005.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Austin   2005.11.06  -  2005.11.11

    DOI: 10.1109/TEST.2005.1584068

    Kyutacar

  • UltraScan: Using Time-Division Demultiplexing/Multiplexing (TDDM/TDM) with VirtualScan for Test Cost Reduction Reviewed International journal

    S. Wu,L.-T. Wang,K. S. Abdel-Hafez,B. Sheu,F. Hsu,S. Lin,M. Chang,X. Wen

    IEEE International Test Conference   Paper 36.4   2005.11

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    USA   Austin   2005.11.06  -  2005.11.11

    DOI: 10.1109/TEST.2005.1584060

  • At-Speed Logic BIST Archtecture for Multiple-Clock Circuits Reviewed International journal

    IEEE International Conference on Computer Design   475 - 478   2005.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   San Jose   2005.10.02  -  2005.10.05

    DOI: 10.1109/ICCD.2005.119

  • Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores Reviewed International journal

    Y. Han, Y. Hu, X. Li, H. Li, A. Chandra, X. Wen

    IEICE Transactions on Information and Syste   E88-D ( 9 )   2126 - 2134   2005.09

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    Language:English   Publishing type:Research paper (scientific journal)

    Kyutacar

  • A Method for Low-Capture-Power At-Speed Test Generation Reviewed International journal

    X. Wen,Y. Yamashita,S. Morishima,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

    IEEE Workshop on RTL and High Level Testing   40 - 49   2005.07

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    China   Harbin   2005.07.20  -  2005.07.21

  • On Quantifying Observability for Fault Diagnosis of VLSI Circuits Reviewed International journal

    N. Toyota,X. Wen,S. Kajihara,M. Sanada

    IEEE Workshop on RTL and High Level Testing   192 - 197   2005.07

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    Language:English   Publishing type:Research paper (international conference proceedings)

    China   Harbin   2005.07.20  -  2005.07.21

  • Path Delay Test Compaction with Process Variation Tolerance Reviewed International journal

    S. Kajihara,M. Fukunaga,X. Wen,T. Maeda,S. Hamada,Y. Sato

    IEEE/ACM Design Automation Conference   845 - 850   2005.06

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    Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Anaheim, CA   2005.06.13  -  2005.06.17

    DOI: 10.1109/DAC.2005.193933

  • On the Extraction of a Minimum Cube to Justify Signal Line Values Reviewed International journal

    K. Miyase,S. Nagayama,S. Kajihara,X. Wen,S. M. Reddy

    IEEE European Test Symposium   79 - 84   2005.05

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Estonia   Tallinn   2005.05.22  -  2005.05.25

  • On Low-Capture-Power Test Generation for Scan Testing Reviewed International journal

    X. Wen,Y. Yamashita,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

    IEEE VLSI Test Symposium   265 - 270   2005.05

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Palm Springs   2005.05.01  -  2005.05.05

    DOI: 10.1109/VTS.2005.60

    Kyutacar

  • On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Reviewed International journal

    X. Wen,S. Kajihara,H. Tamamoto,K. K. Saluja,K. Kinoshita

    IEICE Transactions on Information and Systems   E88-D ( 4 )   703 - 710   2005.04

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1093/ietisy/e88-d.4.703

  • On Speed-Up of Fault Simulation for Handling Intermediate Faulty Voltages Reviewed

    X. Wen, S. kajihara, H. Tamamoto, K.K. Saluja, K. Kinoshita

    J88-D-I ( 4 )   906 - 907   2005.04

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Research paper (scientific journal)

  • At-Speed Logic BIST for IP Cores Reviewed International journal

    B. Cheon,E. Lee,L.-T. Wang,X. Wen,P. Hsu,J. Cho,J. Park,H. Chao,S. Wu

    Design Automation, and Test in Europe   860 - 861   2005.03

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Germany   Munich   2005.03.07  -  2005.03.11

    DOI: 10.1109/DATE.2005.70

    Kyutacar

  • Fault Diagnosis for Physical Defects using Unknown Behavior Model Reviewed International journal

    X. Wen,H. Tamamoto,K. K. Saluja,K. Kinoshita

    Journal of Computer Science and Technology   20 ( 2 )   187 - 194   2005.03

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)

    DOI: 10.1007/s11390-005-0187-x

  • Test Compression for Scan Circuits Using Scan Polarity Adjustment and Pinpoint Test Relaxation Reviewed International journal

    Y. Doi,S. Kajihara,X. Wen,L. Li,and K. Chakrabarty

    ACM Asian and South Pacific Design Automation Conference   59 - 64   2005.01

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    Language:English   Publishing type:Research paper (international conference proceedings)

    China   Shanghai   2005.01.18  -  2005.01.21

    DOI: 10.1109/ASPDAC.2005.1466130

  • On Extraction of a Cube with the Minimum Number of Literals from a Given Input Vector Reviewed International journal

    K. Miyase,S. Nagayama,S. Kajihara,X. Wen,and S. M. Reddy

    IEEE Workshop on RTL and High Level Testing   71 - 76   2004.11

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    Language:English   Publishing type:Research paper (international conference proceedings)

    Japan   Osaka   2004.11.11  -  2004.11.12

  • On Per-Test Fault Diagnosis Using the X-Fault Model Reviewed International journal

    X. Wen,T. Miyoshi,S. Kajiihara,L. Wang,K. K. Saluja,and K. Kinoshita

    IEEE/ACM International Conference on Computer Aided Design   633 - 640   2004.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   San Jose   2004.11.07  -  2004.11.11

    DOI: 10.1109/ICCAD.2004.1382653

  • VirtualScan: A New Compressed Scan Technology for Test Cost Reduction Reviewed International journal

    L.-T. Wang,X. Wen,H. Furukawa,F. Hsu,S. Lin,S. Tsai,K. S. Abdel-Hafez,S. Wu

    IEEE International Test Conference   916 - 925   2004.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)

    USA   Charlotte   2004.10.26  -  2004.10.28

    DOI: 10.1109/TEST.2004.1387356

    Kyutacar

  • ロジックBIST技術の現状と課題 Invited Reviewed

    温暁青,梶原誠司

    日本信頼性学会誌 ( 未設定 )   26 ( 4 )   252 - 262   2004.06

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    Kyutacar

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Publications (Books)

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 入門編(改訂版)

    温暁青、畠山一実(Joint author)

    日経BPコンサルティング  2020.12  ( ISBN:978-4864431361

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    Language:Japanese

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 応用編

    温暁青、畠山一実(Joint author)

    日経BPコンサルティング  2019.04  ( ISBN:978-4864431309

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    Language:Japanese

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 半導体テスト技術者検定3級 問題集

    温暁青、畠山一実(Joint author)

    日経BPコンサルティング  2014.12  ( ISBN:978-4-8644-3071-5

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    Language:Japanese

  • Chapter 9 "Low-Power Testing for 2D/3D Devices and Systems" in Design of 3D Integrated Circuits and Systems

    Rohit Sharma, et al.(Joint author)

    CRC Press  2014.11  ( ISBN:9781466589407

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    Language:English

  • 第3章 "半導体製品の分類"、はかる×わかる半導体 入門編

    温暁青、畠山一実(Joint author)

    日経BPコンサルティング  2013.05  ( ISBN:978-4-8644-3039-5

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    Language:Japanese

  • Chapter 20 "Low-Power Testing for Low-Power LSI Circuits", Advanced Circuits for Emerging Technologies

    X. Wen, Y. Zorian(Joint author)

    John Wiley & Sons  2012.06  ( ISBN:978-0-470-90005-5

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    Language:English

  • Power-Aware Testing and Test Strategies for Low Power Devices

    P. Girard, N. Nicolici, X. Wen(Joint editor)

    Springer  2009.11  ( ISBN:9781441909275

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    Language:English

    Scopus

  • Chapter 3: "Low-Power Test Generation" in Power-Aware Testing and Test Strategies for Low Power Devices

    X. Wen,S. Wang(Joint author)

    Springer  2009.11  ( ISBN:978-1441909275

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    Language:English

  • Chapter 7: "Test Synthesis" in Electronic Design Automation: Synthesis, Verification, and Test

    L.-T. Wang,X. Wen, S. Wu(Joint author)

    Morgan Kaufmann Publishers  2009.03  ( ISBN:978-0123743640

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    Language:English

  • Chapter 7: "Low-Power Testing" in Advanced SOC Test Architectures Towards Nanometer Designs

    P. Girard,X. Wen, N. A. Touba(Joint author)

    Morgan Kaufmann Publishers  2007.12  ( ISBN:978-0123739735

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  • 半導体デバイスの評価・テスト・解析技術

    温暁青,筒井信明,益子洋治,木村祐造,小坂彰(Joint author)

    九州地域産業活性化センター  2006.10 

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    Language:Japanese

  • Chapter 2: "Design for Testability" in VLSI Test Principles and Architectures: Design for Testability

    L.-T. Wang, X. Wen, K. S. Abdel-Hafez(Joint author)

    Morgan Kaufmann Publishers  2006.07  ( ISBN:978-0123705976

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    Language:English

  • VLSI Test Principles and Architectures: Design for Testability

    L.-T. Wang, C.-W.Wu, X. Wen(Joint editor)

    Morgan Kaufmann Publishers  2006.07  ( ISBN:978-0123705976

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  • 半導体テスト技術者育成実証講座 ベーシックコース

    益子洋治,上村正幸,小野陽二,温暁青,筒井信明(Joint author)

    大分県産業創造機構  2006.01 

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  • 半導体テスト技術者育成実証講座 ベーシックコース

    益子洋治,上村正幸,小野陽二,温暁青,筒井信明(Joint author)

    大分県産業創造機構  2006.01 

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    Language:Japanese

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Conference Prsentations (Oral, Poster)

  • New Test Partition Approach for Rotating Test with Lower Rate

    S. Wang

    第66回 FTC 研究会 

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    Event date: 2012.01.19 - 2012.01.21   Language:Japanese  

  • 実速度スキャンテストにおける高品質なキャプチャ安全性保障型テスト生成について

    西田優一郎

    第66回 FTC 研究会 

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    Event date: 2012.01.19 - 2012.01.21   Language:Japanese  

  • テストベクトル変換手法を用いた低消費電力LOS実速度テスト

    宮瀬紘平

    電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング 

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    Event date: 2011.06.17   Language:Japanese  

  • 実速度スキャンテストベクトルに対する遷移タイミング考慮キャプチャ安全性判定

    情報創成工学専攻, 武田敏秀

    電子情報通信学会技術研究報告 

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    Event date: 2011.02.14   Language:Japanese  

  • 知識ベースシステムに基づいたLSIテスト不良原因解析について

    情報創成工学専攻, 武田敏秀

    電子情報通信学会技術研究報告 

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    Event date: 2010.11.29   Language:Japanese  

  • 3値テストパターンに対する遅延テスト品質評価とX割当について

    情報創成工学専攻, 奥慎治

    電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング 

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    Event date: 2010.02.15   Language:Japanese  

  • 部分X分解によるX故障モデルを用いた故障診断手法の高速化

    情報創成工学専攻, 宮瀬紘平

    電子情報通信学会技術研究報告. DC, ディペンダブルコンピューティング 

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    Event date: 2010.02.15   Language:Japanese  

  • フィールドテストにおける巡回テストとテスト集合印加順序について

    情報創成工学専攻, 広実一輝

    第62回 FTC 研究会資料集 

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    Event date: 2010.01.21   Language:Japanese  

  • 劣化検知テストにおけるパス選択について

    情報創成工学専攻, 野田光政

    電子情報通信学会技術研究報告, VLD2009-65 

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    Event date: 2009.12.04   Language:Japanese  

  • 信号値遷移削減のためのドントケア判定率の最適化に関する研究

    情報創成工学専攻, 別府厳

    電子情報通信学会技術研究報告 VLD2009-55 

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    Event date: 2009.12.03   Language:Japanese  

  • 実速度スキャンテストにおけるクリティカルエリア特化型IR-Drop削減手法

    情報創成工学専攻, 榎元和成

    平成21年度 電気関係学会九州支部連合大会予稿集 

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    Event date: 2009.09.22   Language:Japanese  

  • ブロードキャストスキャン圧縮環境下における実速度テストに対するIR-Drop削減Post-ATPG手法

    情報創成工学専攻, 宮瀬紘平

    第61回 FTC 研究会資料集 

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    Event date: 2009.07.16 - 2009.07.18   Language:Japanese  

  • 先端LSI回路向け低消費電力テスト技術の研究開発

    本人

    福岡・長野クラスターマッチングフォーラム 2009 

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    Event date: 2009.06.18   Language:Japanese  

  • 論理回路における劣化故障の発生しやすい箇所の推定について

    情報創成工学専攻, 野田光政

    第60回 FTC 研究会資料集 

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    Event date: 2009.01   Language:Japanese  

  • 実速度スキャンテストにおけるキャプチャセーフテスト生成手法について

    情報創成工学専攻, 高嶋敦之

    電子情報通信学会技術研究報告 

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    Event date: 2008.11   Language:Japanese  

  • 3値論理シミュレーションにおける遅延計算について

    情報創成工学専攻, 福澤友晶

    第59回 FTC 研究会資料集 

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    Event date: 2008.01   Language:Japanese  

  • 実速度スキャンテストにおけるキャプチャ時消費電力削減手法

    情報創成工学専攻, 福澤友晶

    第58回 FTC 研究会資料集 

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    Event date: 2008.01   Language:Japanese  

  • 実速度スキャンテストにおけるキャプチャ時の低消費電力テスト生成手法について

    情報創成工学専攻, 福澤友晶

    デザインガイア2007 ディペンダブルコンピューティング研究会, 信学技法, IEICE Technical Report 

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    Event date: 2007.11.20   Language:Japanese  

  • Per-Test X故障診断手法の 診断分解能向上に関する研究

    情報創成工学専攻, 大谷雅志

    LSIテスティイングシンポジウム2007会議録 

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    Event date: 2007.11.08   Language:Japanese  

  • 実速度スキャンテストにおけるキャプチャ時の低消費電力テスト生成手法について

    信学技法, IEICE Technical Report 

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    Event date: 2007.11   Language:Japanese  

  • A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

    The 7th International Workshop on Microelectronics Assembling and Packaging & Reverse Trade Show 

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    Event date: 2007.10   Language:Japanese  

  • LSI回路のX故障によるPer-Test故障診断手法の拡張について

    信学技法, IEICE Technical Report 

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    Event date: 2007.09   Language:Japanese  

  • 順序回路用故障シミュレーションにおけるコンパイル方式の適用と効果について

    情報処理学会DAシンポジウム2007論文集 

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    Event date: 2007.04   Language:Japanese  

  • 遷移遅延故障に対する高品質テスト生成手法について

    IEICE technical report, Dependable Computing 

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    Event date: 2007.02   Language:Japanese  

  • 低消費電力テストのための制約付テスト生成手法について

    電子情報通信学会技術研究報告  

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    Event date: 2007.01   Language:Japanese  

  • 遅延テスト品質の正確な評価法とテスト生成への応用

    第56回 FTC 研究会資料集 

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    Event date: 2007.01   Language:Japanese  

  • ブロードサイドテストにおけるN回検出用テストパターンに対するX判定

    電子情報通信学会技術研究報告 

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    Event date: 2006.12   Language:Japanese  

  • A New Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits

    LSIテスティイングシンポジウム 

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    Event date: 2006.11   Language:Japanese  

  • 縮退故障用テストパターンのブリッジ故障検出率向上手法について

    情報処理学会DAシンポジウム 

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    Event date: 2006.07   Language:Japanese  

  • コンパイル方式とイベント駆動方式を用いた故障シミュレーションの高速化について

    第55回 FTC 研究会 

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    Event date: 2006.07   Language:Japanese  

  • ブロードサイド方式におけるパス長を考慮した遷移故障用テストパターン生成について

    電子情報通信学会技術研究報告 

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    Event date: 2005.12   Language:Japanese  

  • Low-Capture-Power Test Generation for Scan Testing

    COE workshop for SoC Design Technology and Automation 

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    Event date: 2005.09.15   Language:English  

  • 縮退故障用テストパターンのブリッジ故障検出率向上手法について

    情報処理学会DAシンポジウム 

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    Event date: 2005.08.24 - 2005.08.26   Language:Japanese  

  • SoCにおけるブロードキャストスキャンテスト効率化手法について

    第53回 FTC 研究会 

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    Event date: 2005.07.14 - 2005.07.16   Language:Japanese  

  • 超微細LSIのパス遅延故障に対するテスト圧縮法について

    電子情報通信学会技術研究報告DC2004-107 

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    Event date: 2005.02   Language:Japanese  

  • スキャンテストにおけるキャプチャ時の消費電力削減を考慮したテスト生成

    第52回 FTC 研究会 

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    Event date: 2005.01.20 - 2005.01.22   Language:Japanese  

  • 故障診断のための観測性の定量化について

    電子情報通信学会技術研究報告ICD2004-212 

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    Event date: 2005.01   Language:Japanese  

  • 圧縮化スキャンパタン生成技術

    SEMI Technology Synposium 

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    Event date: 2004.12.01 - 2004.12.03   Language:Japanese  

  • スキャン極性調節とピンポイントテスト変換によるテスト圧縮

    電子情報通信学会技術研究報告  

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    Event date: 2004.12   Language:Japanese  

  • 入力ベクトルからの信号値を正当化する最小キューブ抽出

    電子情報通信学会技術研究報告  

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    Event date: 2004.12   Language:Japanese  

  • X故障モデルを用いたPer-Test故障診断手法に関する研究

    LSIテスティイングシンポジウム 

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    Event date: 2004.11.10 - 2004.11.12   Language:Japanese  

  • X故障モデルを用いたPer-Test故障診断手法について

    情報処理学会DAシンポジウム 

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    Event date: 2004.07.21 - 2004.07.23   Language:Japanese  

  • トランジスタ動作を考慮したデジタル回路のテストと解析

    第51回 FTC 研究会 

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    Event date: 2004.07.15 - 2004.07.16   Language:Japanese  

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Industrial Property

  • MULTIPLE-CAPTURE DFT METHOD FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SELF-TEST OR SCAN-TEST

    L.-T. Wang, P.-C. Hsu, X. Wen

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    Application no:20160512  Date applied:2016.05.12

    Announcement no:20160131707  Date announced:2016.05.12

  • COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL

    L.-T. WANG, .X. WEN

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    Application no:20130305200  Date applied:2013.11.14

  • COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL

    L.-T. WANG, A. Kifli; Augusli, F.-S. Hsu, S.-C. Kao, X. Wen, S.-H. Lin, H.-P. Wang

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    Application no:20120246604  Date applied:2012.09.27

  • GENERATION DEVICE, CLASSIFICATION METHOD, GENERATION METHOD, AND PROGRAM

    M.-F. Wu, J.-L. Huang, X. Wen, K. Miyase

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    Application no:20110209024  Date applied:2011.08.25

  • COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL

    L.-T. Wang, X. Wen

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    Application no:20110197171  Date applied:2011.08.11

  • GENERATING DEVICE, GENERATING METHOD, AND PROGRAM

    K. Miyase, X. Wen, S. Kajihara, Y. Yamato

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    Application no:20110140734  Date applied:2011.06.16

  • Test Device, Test Method, Program and Medium

    X. Wen, K. Miyase, K. Enokimoto

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    Application no:特願2011-099216  Date applied:2011.04.27

  • Method and Apparatus for Unifying Self-Test with Scan-Test During Prototype Debug and Production Test

    L.-T. Wang, X. Wen

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    Application no:20100218062  Date applied:2010.08.26

  • DON'T-CARE-BIT IDENTIFICATION METHOD AND DON'T-CARE-BIT IDENTIFICATION PROGRAM

    K. Miyase, X. Wen, S. Kajihara, Y. Yamato

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    Application no:20100218063  Date applied:2010.08.26

  • LOGIC VALUE DETERMINATION METHOD AND LOGIC VALUE DETERMINATION PROGRAM

    K. Miyase, X. Wen, S. Kajihara, Y. Yamato

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    Application no:20100205491  Date applied:2010.08.12

  • TEST PATTERN GENERATION METHOD FOR AVOIDING FALSE TESTING IN TWO-PATTERN TESTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT

    X. Wen, K. Miyase, S. Kajihara

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    Application no:20100095179  Date applied:2010.04.15

  • DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Application no:20100064191  Date applied:2010.03.11

  • Generation Device, Generation Method, Program and Medium

    M. Wu, J.-L. Huang, X. Wen, K. Miyase

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    Application no:特願2010-534766  Date applied:2009.10.05

    Announcement no:再公表10-047219  Date announced:2010.04.29

  • Generation Device, Generation Method, Program and Medium

    M. Miyase, X. Wen, S. Kajihara

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    Application no:特願2010-525650  Date applied:2009.07.30

    Announcement no:再公表10-021233  Date announced:2010.02.25

  • METHOD AND APPARATUS FOR BROADCASTING SCAN PATTERNS IN A SCAN-BASED INTEGRATED CIRCUIT

    L.-T. Wang, H.-P. Wang, X. Wen, M.-C. Lin, S.-H. Lin, T.-C. Yeh, S.-W. Tsai, K.-S. Abdel-Hafez

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    Application no:Serial No.: 468909 / Series Code: 12  Date applied:2009.05.20

    Announcement no:20090235132  Date announced:2009.09.17

  • Logic Value Determination Method and Logic Value Determination Program

    M. Miyase, X. Wen, S. Kajihara

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    Application no:特願2009-538144  Date applied:2008.10.16

    Announcement no:再公表09-051193  Date announced:2011.03.03

  • Don't Care Extraction Method and Don't Care Extraction Program

    M. Miyase, X. Wen, S. Kajihara

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    Application no:特願2009-538142  Date applied:2008.10.16

    Announcement no:再公表09-051191  Date announced:2011.03.03

  • Multiple-Capture DFT system for scan-based integrated circuits

    L.-T. Wang, M.-C. Lin, X. Wen, H.-P. Wang, C.-C. Hsu, S.-C. Kao, F.-S. Hsu

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    Application no:Serial No.: 285269 / Series Code: 12  Date applied:2008.10.01

    Announcement no:20090070646  Date announced:2009.03.12

  • Method and apparatus for unifying self-test with scan-test during prototype debug and production test

    L.-T. Wang, X. Wen, K.-S. Abdel-Hafez, S.-H. Lin, H.-P. Wang, M.-T. Chang, P.-C. Hsu, S.-C. Kao, M.-C. Lin

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    Application no:Serial No.: 285225 / Series Code: 12  Date applied:2008.09.30

    Announcement no:20090037786  Date announced:2009.02.05

  • GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Application no:Serial No.: 235628 / Series Code: 12  Date applied:2008.09.23

    Announcement no:20090019327  Date announced:2009.01.15

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

    L.-T. Wang, P.-C. Hsu, S.-C. Kao, M.-C. Lin, H.-P. Wang, H.-J. Chao, X. Wen

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    Application no:Serial No.: 222931 / Series Code: 12  Date applied:2008.08.20

    Announcement no:20090132880  Date announced:2009.05.21

  • Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

    L.-T. Wang, X. Wen, S.-H. Lin, K.-S. Abdel-Hafez

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    Application no:Serial No.: 216639 / Series Code: 12  Date applied:2008.07.09

    Announcement no:20080276141  Date announced:2008.11.06

  • CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Application no:Serial No.: 129746 / Series Code: 12  Date applied:2008.05.30

    Announcement no:20080235543  Date announced:2008.09.25

  • Test Generation Method for Avoiding False Testing in 2-Pattern Test for LSI Circuits

    X. Wen, K. Miyase, S. Kajijhara

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    Application no:特願2009-511784  Date applied:2008.04.11

    Announcement no:再公表08-133052  Date announced:2010.07.22

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, X. Wen

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    Application no:Serial No.: 984316 / Series Code: 11  Date applied:2007.11.15

    Announcement no:20080134107  Date announced:2008.06.05

  • GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Application no:PCT/JP2007/068505  Date applied:2007.09.25

    Announcement no:20090319842  Date announced:2009.12.24

  • Test Method and Test Program of Semiconductor Logic Circuit Device

    X. Wen, S. Kajihara

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    Application no:PCT/JP2006/306142  Date applied:2007.08.28

    Announcement no:20090083593  Date announced:2009.03.26

  • Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

    L.-T. Wang, P.-C. Hsu, X. Wen

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    Application no:Serial No.: 806098 / Series Code: 11  Date applied:2007.05.30

    Announcement no:20070255988  Date announced:2007.11.01

  • Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

    L.-T. Wang, M.-T. Chang, H.-J. Chao, X. Wen, P.-C. Hsu

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    Application no:Serial No.: 603085 / Series Code: 11  Date applied:2006.11.22

    Announcement no:20070168803  Date announced:2007.07.19

  • Diagnosis Device, Diagnosis Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Application no:特願2006-301012  Date applied:2006.11.06

    Announcement no:特開2008-116374  Date announced:2006.11.06

  • Generation Device, Generation Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Application no:特願2006-262764  Date applied:2006.09.27

    Announcement no:開2008-082867  Date announced:2008.04.10

  • Test vector generating method and test vector generating program of semiconductor logic circuit device

    X. Wen, S. Kajihara

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    Application no:PCT/JP2006/313848  Date applied:2006.07.12

    Announcement no:20090259898  Date announced:2009.10.15

  • Generation Device, Generation Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Application no:特願2006-088695  Date applied:2006.03.28

    Announcement no:特開2007-263724  Date announced:2007.10.11

  • Conversion Device, Conversion Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Application no:特願2005-346613  Date applied:2005.11.30

    Announcement no:特開2007-155339  Date announced:2007.06.21

  • Multiple-capture DFT system for scan-based integrated circuits

    L.-T. Wang, M.-C. Lin, X. Wen, H.-P. Wang, C.-C. Hsu, S.-C. Kao, F.-S. Hsu

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    Application no:Serial No.: 151258 / Series Code: 11  Date applied:2005.06.14

    Announcement no:20050235186  Date announced:2005.10.20

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, X. Wen, S.-H. Lin

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    Application no:Serial No.: 111908 / Series Code: 11  Date applied:2005.04.22

    Announcement no:20050229123  Date announced:2005.10.13

  • Fault Diagnosis Method, Device, Diagnosis Method, Medium of Program for Semiconductor Logic Circuits

    X. Wen, S. Kajijhara

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    Application no:特願2004-305064  Date applied:2004.10.20

    Announcement no:特開2006-118903  Date announced:2006.05.11

  • Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

    L.-T. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu, F.-S. Hsu, A. Kifli, S.-H. Lin, S. Wu, S.-M. Wang

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    Application no:Serial No.: 901298 / Series Code: 10  Date applied:2004.07.29

    Announcement no:20050055617  Date announced:2005.03.10

  • Mask network design for scan-based integrated circuits

    L.-T. Wang, S.-M. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu

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    Application no:Serial No.: 876784 / Series Code: 10  Date applied:2004.06.28

    Announcement no:20050060625  Date announced:2005.03.17

  • Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits

    L.-T. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu, S.-M. Wang

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    Application no:Serial No.: 850460 / Series Code: 10  Date applied:2004.05.21

    Announcement no:20050262409  Date announced:2005.11.24

  • Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

    K.-S. Abdel-Hafez, X. Wen, L.-T. Wang, P.-C. Hsu, S.-C. Kao, H.-J. Chao, H.-P. Wang

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    Application no:Serial No.: 762571 / Series Code: 10  Date applied:2004.01.23

    Announcement no:20040237015  Date announced:2004.11.25

  • Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit

    K.-S. Abdel-Hafez, L.-T. Wang, A. Kifli, F.-S. Hsu, X. Wen, M.-C. Lin, H.-P. Wang

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    Application no:Serial No.: 691966 / Series Code: 10  Date applied:2003.10.24

    Announcement no:20040153926  Date announced:2004.08.05

  • Method and apparatus for unifying self-test with scan-test during prototype debug and production test

    L.-T. Wang, X. Wen, K.-S. Abdel-Hafez

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    Application no:Serial No.: 406592 / Series Code: 10  Date applied:2003.04.04

    Announcement no:20040268181  Date announced:2004.12.30

  • Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

    L.-T. Wang, H.-P. Wang, X. Wen, M.-C. Lin, S.-H. Lin, T.-C. Yeh, S.-W. Tsai, K.-S. Abdel-Hafez

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    Application no:Serial No.: 39667 / Series Code: 10  Date applied:2003.01.10

    Announcement no:20030154433  Date announced:2003.08.14

  • Method and system to optimize test cost and disable defects for scan and BIST memories

    L.-T. Wang, S.-H. Lin, C.-C. Hsu, X. Wen, A. M. Vu, Y.-H. Park, H.-P. Wang

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    Application no:Serial No.: 16128 / Series Code: 10  Date applied:2002.04.05

    Announcement no:20020194558  Date announced:2002.12.19

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, A. Kifli, F.-S. Hsu, S.-C. Kao, X. Wen, S.-H. Lin, H.-P. Wang

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    Application no:Serial No.: 108238 / Series Code: 10  Date applied:2002.03.28

    Announcement no:20030023941  Date announced:2003.01.30

  • Multiple-capture DFT system for scan-based integrated circuits

    L.-T. Wang, M.-C. Lin, X. Wen, H.-P. Wang, C.-C. Hsu, S.-C. Kao, F.-S. Hsu

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    Application no:Serial No.: 101517 / Series Code: 10  Date applied:2002.03.20

    Announcement no:20020184560  Date announced:2002.12.05

  • Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

    L.-T. Wang, M.-T. Chang, S.-H. Lin, H.-J. Chao, J. Lee, H.-P. Wang, X. Wen, P.-C. Hsu, S.-C. Kao, M. Lin

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    Application no:Serial No.: 086214 / Series Code: 10  Date applied:2002.02.27

    Announcement no:20020138801  Date announced:2002.09.26

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

    L._T. Wang, P.-C. Hsu, S.-C. Kao, M.-C. Lin, H.-P. Wang, H.-J. Chao, .X. Wen

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    Application no:Serial No.: 067372 / Series Code: 10  Date applied:2002.02.07

    Announcement no:20020120896  Date announced:2002.08.29

  • Test method and test program of semiconductor logic circuit device

    X. Wen, S. Kajihara

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    Patent/Registration no:8,117,513  Date registered:2012.02.14 

  • Conversion device, conversion method, program, and recording medium

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Patent/Registration no:7,971,118  Date registered:2011.06.28 

  • Generating device, generating method, program and recording medium

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Patent/Registration no:7,962,822  Date registered:2011.06.14 

  • Method and apparatus for unifying self-test with scan-test during prototype debug and production test

    L.-T. Wang, X. Wen

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    Patent/Registration no:7,945,830  Date registered:2011.05.17 

  • Diagnostic device, diagnostic method, program, and recording medium

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Patent/Registration no:7,913,144  Date registered:2011.03.22 

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, X. Wen

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    Patent/Registration no:7,904,857  Date registered:2011.03.08 

  • Multiple-capture DFT system for scan-based integrated circuits

    L.-T. Wang, M.-C. Lin, X. Wen, H.-P. Wang, C.-C. Hsu, S.-C. Kao, F.-S. Hsu

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    Patent/Registration no:7,904,773  Date registered:2011.03.08 

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

    L.-T. Wang, P.-C. Hsu, S.-C. Kao, M.-C. Lin, H.-P. Wang, H.-J. Chao, X. Wen

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    Patent/Registration no:7,779,323  Date registered:2010.08.17 

  • Compacting test responses using X-driven compactor

    Z. Wang, L.-T. Wang, S. Wu, X. Wen, B. Sheu, Z. Jiang

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    Patent/Registration no:7,779,322  Date registered:2010.08.17 

  • Method and apparatus for unifying self-test with scan-test during prototype debug and production test

    L.-T. Wang, X. Wen

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    Patent/Registration no:7,747,920  Date registered:2010.06.29 

  • Generating device, generating method, program and recording medium

    X. Wen, S. Kajihara, K. Miyase, Y. Minamoto, H. Date

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    Patent/Registration no:7,979,765  Date registered:2011.07.12 

  • Test vector generating method and test vector generating program of semiconductor logic circuit device

    X. Wen, S. Kajihara

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    Patent/Registration no:7,743,306  Date registered:2010.06.22 

  • Mask network design for scan-based integrated circuits

    L.-T. Wang, X. Wen, B. Sheu

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    Patent/Registration no:7,735,049  Date registered:2010.06.08 

  • Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

    L.-T. Wang, H.-P. Wang, X. Wen, M.-C. Lin, S.-H. Lin, T.-C. Yeh, S.-W. Tsai, K.-S. Abdel-Hafez

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    Patent/Registration no:7,721,173  Date registered:2010.05.18 

  • Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

    L.-T. Wang, H.-P. Wang, X. Wen, M.-C. Lin, S.-H. Lin, T.-C. Yeh, S.-W. Tsai, K.-S. Abdel-Hafez

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    Patent/Registration no:7,552,373  Date registered:2009.06.23 

  • Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

    L.-T. Wang, .K.-S. Abdel-Hafez, X. Wen, B. Sheu, F.-S. Hsu, A. Kifli, S.-H. Lin, S. Wu, S.-M. Wang

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    Patent/Registration no:7,512,851  Date registered:2009.03.31 

  • Method and apparatus of fault diagnosis for integrated logic circuits

    X. Wen, S. Kajihara

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    Patent/Registration no:7,478,295  Date registered:2009.01.13 

  • Multiple-capture DFT system for scan-based integrated circuits

    L.-T. Wang, X. Wen

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    Patent/Registration no:7,451,371  Date registered:2008.11.11 

  • Method and apparatus for unifying self-test with scan-test during prototype debug and production test

    L.-T. Wang, X. Wen, K.-S. Abdel-Hafez, S.-H. Lin, H.-P. Wang, M.-T. Chang, P.-C. Hsu, S.-C. Kao, M.-C. Lin, C.-C. Hsu

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    Patent/Registration no:7,444,567  Date registered:2008.10.28 

  • Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

    L.-T. Wang, P.-C. Hsu, X. Wen

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    Patent/Registration no:7,434,126  Date registered:2008.10.07 

  • Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

    L.-T. Wang, X. Wen, S.-H. Lin, K.-S. Abdel-Hafez

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    Patent/Registration no:7,412,672  Date registered:2008.08.12 

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, A. Kifli, F.-S. Hsu, X. Wen, S.-C. Kao, S.-H. Lin, H.-P. Wang

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    Patent/Registration no:7,331,032  Date registered:2008.02.12 

  • Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

    L.-T. wang, M.-T. Chang, H.-J. Chao, X. Wen, P.-C. Hsu

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    Patent/Registration no:7,284,175  Date registered:2008.10.16 

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

    L.-T. Wang, P.-C. Hsu, X. Wen

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    Patent/Registration no:7,260,756  Date registered:2007.08.21 

  • Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

    L.-T. Wang, M.-T. Chang, S.-H. Lin, H.-J. Chao, J. Lee, H.-P. Wang, X. Wen, P.-C. Hsu, S.-C. Kao, M.-C. Lin, S.-W. Tsai, C.-C. Hsu

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    Patent/Registration no:7,191,373  Date registered:2007.03.13 

  • Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits

    L.-T. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu, S.-M. Wang

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    Patent/Registration no:7,124,342  Date registered:2006.10.17 

  • Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

    K.-S. Abdel-Hafez, X. Wen, L.-T. Wang, P.-C. Hsu, S.-C. Kao, H.-J. Chao, H.-P. Wang

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    Patent/Registration no:7,058,869  Date registered:2006.06.06 

  • Mask network design for scan-based integrated circuits

    L.-T. Wang, S.-M. Wang, K.-S. Abdel-Hafez, X. Wen, B. Sheu

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    Patent/Registration no:7,032,148  Date registered:2006.04.18 

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

    L.-T. Wang, P.-C. Hsu, S.-C. Kao, M.-C. Lin, H.-P. Wang, H.-J. Chao, X. Wen

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    Patent/Registration no:7,007,213  Date registered:2006.02.28 

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, A. Kifli, F.-S. Hsu, S.-C. Kao, X. Wen, S.-H. Lin, H.-P. Wang

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    Patent/Registration no:6,957,403  Date registered:2005.10.18 

  • Multiple-capture DFT system for scan-based integrated circuits

    L.-T. Wang, M.-C. Lin, X. Wen, H.-P. Wang, C.-C. Hsu, S.-C. Kao, F.-S. Hsu

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    Patent/Registration no:6,954,887  Date registered:2005.10.11 

  • Conversion Device, Conversion Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許5017603  Date registered:2012.06.22 

  • Test Vector Generation Method and Program for Semiconductor Logic Circuits

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許4752030  Date registered:2012.06.03 

  • Test Vector Generation Method and Program for Semiconductor Logic Circuits

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許4752029  Date registered:2012.06.03 

  • Conversion Device, Conversion Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許4482622  Date registered:2010.04.02 

  • Fault Diagnosis Method and Program for Semiconductor Logic Circuits

    X. Wen, S. Kajijhara

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    Announcement no:特開2010-217188  Date announced:2010.09.30

    Patent/Registration no:特許4919237  Date registered:2012.02.10 

  • Conversion Device, Conversion Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:I368042  Date registered:2013.07.11 

  • Generation Device, Generation Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許5017604  Date registered:2012.06.22 

  • Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit

    X. Wen, K. Miyase, S. Kajihara

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    Patent/Registration no:8,001,437  Date registered:2011.08.16 

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, X. Wen

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    Patent/Registration no:8,219,945  Date registered:2013.07.10 

  • Generation Device, Determination Method, Generation Method, and Program

    M. Wu, J.-L. Huang, K. MIyase, X. Wen

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    Patent/Registration no:特許5481754  Date registered:2014.02.26 

  • Diagnosis Device, Diagnosis Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許5333956  Date registered:2013.08.09 

  • Generation Device and Generation Method

    M. Miyase, X. Wen, S. Kajihara, Y. Yamato

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    Patent/Registration no:特許5311351  Date registered:2013.07.12 

  • Don't Care Extraction Method and Don't Care Extraction Program

    M. Miyase, X. Wen, S. Kajihara

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    Patent/Registration no:特許5221554  Date registered:2013.03.15 

  • Logic Value Determination Method and Logic Value Determination Program

    X. Wen, S. Kajijhara, K. Miyase

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    Patent/Registration no:特許5141989  Date registered:2012.11.30 

  • Test Generation Method for Avoding False Testing in 2-Pattern Test for LSI Circuits

    X. Wen, S. Kajijhara, K. Miyase

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    Patent/Registration no:特許5141988  Date registered:2012.11.30 

  • Generation Device, Generation Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許5066684  Date registered:2012.08.24 

  • Proram and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:特許5035663  Date registered:2012.07.13 

  • Generation Device, Generation Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:I368041  Date registered:2013.07.11 

  • Test Vector Generation Method and Program for Semiconductor Logic Circuits

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:I311650  Date registered:2009.07.01 

  • Generation Device and Generation Method

    M. Miyase, X. Wen, S. Kajihara, Y. Yamato

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    Patent/Registration no:ZL 2009 8 0134361.2  Date registered:2014.03.14 

  • Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

    L.-T. Wang, H.-P. Wang, X. Wen

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    Patent/Registration no:9,678,156  Date registered:2017.06.13 

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

    L.-T. Wang, H.-P. Wang, X. Wen

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    Patent/Registration no:9,316,688  Date registered:2016.04.19 

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

    L.-T. Wang, H.-P. Wang, X. Wen

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    Patent/Registration no:9,274,168  Date registered:2016.03.01 

  • Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

    L.-T. Wang, H.-P. Wang, X. Wen

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    Patent/Registration no:9,091,730  Date registered:2015.07.28 

  • Method and system to optimize test cost and disable defects for scan and BIST memories

    L.-T. Wang, S.-H. Lin, C.-C. Hsu, X. Wen, A. M. Vu, Y.-H. Park, H.-P. Wang

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    Announcement no:20020194558  Date announced:2002.12.19

  • Mask network design for scan-based integrated circuits

    L.-T. Wang, X. Wen, B, Sheu

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    Announcement no:20060156122  Date announced:2006.07.13

  • MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SCAN-TEST

    L.-T. Wang, P.-C. Hsu, X. Wen

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    Announcement no:20150316616  Date announced:2015.11.05

  • MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SCAN-TEST

    L.-T. Wang, P.-C. Hsu, X. Wen

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    Announcement no:20150338465  Date announced:2015.11.26

  • Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

    L.-T. Wang, H.-P. Wang, X. Wen, M.-C. Lin, S.-H. Lin, T.-C. Yeh, S.-W. Tsai, K. S. Abdel-Hafez

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    Patent/Registration no:9,696,377  Date registered:2017.07.04 

  • METHOD AND APPARATUS FOR DIAGNOSING FAILURES IN AN INTEGRATED CIRCUIT USING DESIGN-FOR-DEBUG (DFD) TECHNIQUES

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    Patent/Registration no:EP01364436B1  Date registered:2006.05.24 

  • MULTIPLE-CAPTURE DFT SYSTEM FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SELF-TEST OR SCAN TEST

    L.-T. WANG, P.-C. HSU, S.-C. KAO, M.-C. LIN, H.-P. WANG, X. WEN

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    Patent/Registration no:EP01360513B1  Date registered:2008.04.02 

  • METHOD AND SYSTEM TO OPTIMIZE TEST COST AND DISABLE DEFECTS FOR SCAN AND BIST MEMORIES

    P.-C. HSU, S.-C. KAO, M.-C. LIN, X. WEN, C.-C. HSU, Y.-H. PARK

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    Patent/Registration no:EP01377981B1  Date registered:2007.06.06 

  • A MULTIPLE-CAPTURE DFT SYSTEM FOR SCAN-BASED INTEGRATED CIRCUITS

    L.-T. WANG, S.-C. KAO, M.-C. LIN, H.-P. WANG, X. WEN, C.-C. HSU, F.-S. HSU

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    Patent/Registration no:EP01370880B1  Date registered:2008.08.27 

  • Test Vector Generation Method and Program for Semiconductor Logic Circuits

    X. Wen, S. Kajijhara

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    Patent/Registration no:発明第I311650 号  Date registered:2009.07.01 

  • Test Pattern Optimization Method

    M. Wu, J.-L. Huang, X. Wen, K. Miyase

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    Patent/Registration no:I403746  Date registered:2013.08.01 

  • Diagnosis Device, Diagnosis Method, Program and Medium

    X. Wen, S. Kajijhara, K. Miyase, Y. Minato, H. Date

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    Patent/Registration no:I369503  Date registered:2013.08.01 

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, X. Wen

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    Patent/Registration no:8,775,985  Date registered:2014.07.08 

  • Don't-care-bit identification method and don't-care-bit identification program

    K. Miyase, X. Wen, S, Kajihara

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    Patent/Registration no:8,589,751  Date registered:2013.11.19 

  • Computer-aided design system to automate scan synthesis at register-transfer level

    L.-T. Wang, A. Kifli, F-.S. Hsu, S.-C. Kao, X. Wen, S.-H. Lin, H.-P. Wang

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    Patent/Registration no:8,543,950  Date registered:2013.09.24 

  • Target logic value determination method for unspecified bit in test vector for combinational circuit and non-transitory computer-readable medium

    K. Miyase, X. Wen, S. Kajihara

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    Patent/Registration no:8,453,023  Date registered:2013.05.28 

  • Generating device, generating method, and progra

    K. Miyase, X. Wen, S. Kajihara, Y. Yamato

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    Patent/Registration no:8,429,472  Date registered:2013.04.23 

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Lectures

  • Power-Aware Testing for Low-Power VLSI Circuits

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  • Reliability: The Unchanging Value of the Ever-Changing Semiconductor World

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  • Power-Aware IC Testing: Present and Future

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  • LSI Testing: A Core Technology to A Successful LSI Industry

    The IEEE International Conference on ASIC  2021.10 

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    Language:Chinese   Presentation type:Invited lecture   Venue:Kumming, China  

  • Power-Aware Testing for Low-Power LSI Circuits

    The 9th IEEE International Symposium on Next-Generation Electronicserence  2021.07 

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    Language:English   Presentation type:Invited lecture  

  • LSI Test: from Research to Business

    The 18th China Fault Tolerant Computing Conference  2019.08 

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    Language:Chinese   Presentation type:Invited lecture  

  • Power-Aware Testing of Low-Power VLSI Circuits

    The 15th IEEE International Conference on Electron Devices and Solid-State Circuits  2019.06 

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    Presentation type:Invited lecture  

  • Power-Aware Testing for Low-Power LSI Circuits

    Special Seminar  2018.12  Beijing University of Technology

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    Presentation type:Invited lecture  

  • All about ICs: From Technology Trends to Career Choices

    Special Seminar  2018.12  School of Software, Tsinghua University

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    Presentation type:Invited lecture  

  • Power-Aware LSI Testing: Challenges and Strategies

    Special Seminar  2018.03  Beijing University of Aeronautics and Astronautics

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    Presentation type:Invited lecture  

  • Power-Aware Testing for Low-Power VLSI Circuits

    特別講演会  2017.12 

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    Presentation type:Invited lecture   Venue:Beijing, China  

  • IC: Technical Trends and Career Development

    Special Seminar  2017.03  School of Computer Science and Technology, Anhui University

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    Presentation type:Invited lecture  

  • IC: Technical Trends and Career Development

    特別講演会  2017.03 

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    Presentation type:Invited lecture   Venue:Xuancheng, China  

  • IC: Technical Trends and Career Development

    Special Seminar  2017.03  School of Electronic Science and Applied Physics, Hefei University of Technology

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    Presentation type:Invited lecture  

  • Power-Aware Testing For Low-Power VLSI Circuits

    The 13th IEEE International Conference on Solid-State and Integrated Circuit Technology  2016.10 

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    Presentation type:Invited lecture  

  • IC: Technical Trends and Career Development

    Special Seminar  2016.10  Nantong University

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    Presentation type:Invited lecture  

  • Power Supply Noise and Its Reduction in At-Speed Scan Testing

    The IEEE 11th International Conference on ASIC  2015.11 

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    Presentation type:Invited lecture  

  • Low-Power Test to Power-Safe Test

    2014.10  Duke University

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    Presentation type:Invited lecture  

  • From Low-Power Test to Power-Safe Test

    2014.10  Tsinghua University

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    Presentation type:Invited lecture  

  • From Low-Power Test to Power-Safe Test

    2014.09  Hefei University of Technology

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    Presentation type:Invited lecture  

  • Power-Aware Testing: The Next Stage

    2014.05  University of Stuttgart

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    Presentation type:Invited lecture  

  • Low-Power LSI Testing

    2013.11 

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    Presentation type:Invited lecture  

  • Power-Aware Testing: The Next Stage

    2013.09  National Sun Yat-Sen University

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    Presentation type:Invited lecture  

  • Power-Aware Testing: The Next Stage

    2013.09  National Chun Hsing University

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    Language:English   Presentation type:Special lecture  

  • Power-Aware Testing: The Next Stage

    2013.06  Hefei University of Technology

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    Presentation type:Invited lecture  

  • Towards the Next-Generation Power-Aware Testing Technologies

    CMOS Emerging Technologies Conference  2012.07 

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    Presentation type:Invited lecture   Venue:Vancouver, Canada  

  • Power-Aware Testing for Low-Power VLSI Circuits

    特別講演会  2012.03 

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    Presentation type:Special lecture   Venue:Beijing, China  

  • Power-Aware Testing for Low-Power VLSI Circuits

    特別講演会  2012.03 

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    Presentation type:Special lecture   Venue:Beijing, China  

  • Power-Aware Testing for Low-Power VLSI Circuits

    2011.12  ECE Seminar, University of Connecticut

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    Presentation type:Special lecture  

  • Low-Power Testing for Low-Power Devices

    2011.10  Hong Kong Chinese University

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    Presentation type:Special lecture  

  • Power-Aware Test for Low-Power Devices

    AMD Tech Forum: KGD Track  2011.01  AMD

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    Presentation type:Special lecture   Venue:Shanghai, China  

  • Low-Aware Test for Low-Power Devices

    MAP 2010  2010.11  MAP

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    Presentation type:Invited lecture   Venue:Fukuoka, Japan  

  • Low-Aware Test for Low-Power Devices

    DFT 2010  2010.10  DFT

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    Presentation type:Invited lecture   Venue:Kyoto, Japan  

  • Serhcing for High and Low for the Right Test

    LPonTR 2010  2010.05  LPonTR

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    Presentation type:Panel discussion   Venue:Czech, Prague  

  • Power-Aware Test for Low-Power LSI Circuits

    CMOS 2010  2010.05  CMOS

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    Presentation type:Invited lecture   Venue:Wislter, Canada  

  • Low-Power Test and Noise-Aware Test: Foes or Friends

    VTS 2010  2010.04  VTS

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    Presentation type:Panel discussion   Venue:Santa Cruz, USA  

  • Challenges and Chances in Deep-Submicron LSI Testing

    Academic Forum on Computer Science and Technology  2010.03  Shanghai University

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    Language:English   Presentation type:Invited lecture   Venue:Shanghai, China  

  • 省電力志向テスト技術(Power-Aware Testing) の現状と課題

    第4回 四国シリコンテスト技術研究会  2010.02  四国シリコンテスト技術研究会

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    Presentation type:Special lecture   Venue:日本、松山市  

  • Is Low Power Testing Necessary? What does the Test Industry Truly Need? --> Real Issues and Available Solutions

    ATS 2009  2009.11  ATS

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    Presentation type:Panel discussion   Venue:Taichung, Taiwan  

  • From Artillery Fire to Sniper Fire: A Paradigm Shift in Test Power Reduction

    ITC 2009  2009.11  ITC

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    Presentation type:Invited lecture   Venue:Austin, USA  

  • Low-Power Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing

    特別講演会  2009.10 

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    Presentation type:Special lecture   Venue:Madison, USA  

  • VLSIの低消費電力テスト技術

    半導体テスト技術交流会  2009.02  大分県LSIクラスター推進会議

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    Presentation type:Special lecture   Venue:日本、大分県  

  • 低消費電力テスト: 現状と展望

    アドバンテスト展2008 テクニカルセミナー  2008.06  ㈱アドバンテスト

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    Presentation type:Special lecture   Venue:日本、東京  

  • Test Power: A Devil or an Angel?

    China Test Conference 2008  2008.05  China Test Conference組織委員会

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    Presentation type:Panel discussion   Venue:Suzhou, China  

  • Challenges and Chances in Deep-Submicron LSI Testing

    特別講演会  2008.04 

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    Presentation type:Special lecture   Venue:Storr, USA  

  • Test Strategies for Low Power Devices

    DATE 2008  2008.03  DATE 2008 組織委員会

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    Presentation type:Panel discussion   Venue:Munich, Germany  

  • SIAT:Signal-Integrity-Aware Testing

    STS(SEMI テクノロジーシンポジウム)  2007.12  SEMICON JAPAN

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    Presentation type:Special lecture   Venue:日本、東京  

  • LSIテスト技術の開発動向について

    平成19年度知的財産セミナー  2007.11  株式会社ベンチャーラボ

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    Presentation type:Special lecture   Venue:日本、福岡市  

  • テスト技術の概論と最新動向

    平成19年度大分県LSIクラスター推進会議総会  2007.07  大分県LSIクラスター推進会議

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    Presentation type:Special lecture   Venue:日本、大分市  

  • SIAT:Signal-Integrity-Aware Testingを目指して

    JEITA: STRJ-WG2  2006.10  JEITA: STRJ-WG2

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    Presentation type:Special lecture   Venue:日本、横浜市  

  • 集積回路の高信頼化技術

    三木会  2006.05  本学地域共同研究センター

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    Presentation type:Special lecture   Venue:日本、北九州市  

  • 集積回路のテスト技術の研究開発

    第19回e-ZUKAトライバレー産学官交流研究会  2006.04  飯塚市

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    Presentation type:Special lecture   Venue:日本、飯塚市  

  • Low-Capture-Power Test Generation for Scan-Based At-Speed Testing

    特別講演会  2005.10 

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    Presentation type:Special lecture   Venue:Madison, USA  

  • ディジタルLSIのテスト技術の最新動向

    ウエハテストビジネス研究会  2005.06  ウエハテストビジネス研究会

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    Presentation type:Special lecture   Venue:日本、福岡市  

  • LSIテスト: 現状と動向

    VLSIテスト技術研究会  2005.03  福岡県産業・科学技術振興財団

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    Presentation type:Special lecture   Venue:日本、福岡市  

  • A Method for Low-Capture-Power At-Speed Test Generation

    特別講演会  2005.01 

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    Presentation type:Special lecture   Venue:Beijing, China  

  • LSIテストとテスト容易化設計 ~現状と動向~

    平成16年度第4回大分県半導体関連企業ビジネスチャンス研究会  2004.12  大分県商工労働部

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    Presentation type:Special lecture   Venue:日本、大分市  

  • On Low-Capture-Power Test Generation for Scan Testing

    特別講演会  2004.10 

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    Presentation type:Special lecture   Venue:Beijing, China  

  • On Low-Capture-Power Test Generation for Scan Testing

    特別セミナー  2004.10 

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    Presentation type:Special lecture   Venue:Beijing, China  

  • At-Speed Logic BIST for Multi-Clock Multi-frequency Designs

    特別講演会  2002.06 

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    Presentation type:Special lecture   Venue:Palo Alto, USA  

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Press

  • 高品質半導体を開発へ

    温暁青

    西日本新聞  2013.05.11

  • 九工大 半導体検査に新技術 廃棄率が大幅改善へ スマホ製造費削減 価格低下も

    温暁青

    西日本新聞   2012.01.08

  • 九州工業大 保有特許活用でSPC

    温暁青

    日経産業新聞  2011.12.16

  • テスト時のローパワー化に高い関心

    温暁青

    Tech-On  2008.03.17

Honors and Awards

  • Best Paper Award

    The 30th IEEE Asian Test Symposium   GPU-Accelerated Timing Simulation of Systolic Array Based AI Accelerators   2021.11.24

    S. Holst, B. Lim, X. Wen

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    Country:Japan

  • Best Paper Award

    The 25th IEEE Asian Test Symposium   Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch   2016.11.22

    K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian,

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    Country:Others

  • IEEE Fellow

    IEEE   2012.01.01

    Xiaoqing Wen

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    Country:United States

  • Best Paper Award, Institute of Electronics, Information and Communication Engineers (IEICE) / Information and Systems Society (ISS)

    2009.11.26

    X. Wen,Y. Yamashita,S. Kajihara,L.-T. Wang,K. K. Saluja,K. Kinoshita,K. Miyase,T. Suzuki

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    Country:Japan

  • Best Paper Award

    2018.08.15

    A. Yan, Y. Ling, J. Cui, Z. Chen, X. Wen

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    Country:China

  • Best Paper Award

    2007.10.12

    X. Wen, Y. Yamato, K. Miyase, S. Kajihara, H. Furukawa, L.-T. Wang, K. K. Saluja, K. Kinoshita

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    Country:Others

  • Research Achievement Award, Information Processing Society of Japan (IPSJ) / Northeastern Section

    1993.05.11

    Xiaoqing Wen

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    Country:Japan

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Grants-in-Aid for Scientific Research

  • High-Quality False-Test-Avoidance Test for Next-Generation Low-Power LSI Circuits

    Grant number:15K12003  2015.04 - 2018.03   Grant-in-Aid for challenging Exploratory Research

  • Ultra-Low-Power Built-In Self-Test for LSIs in Implantable Medical Devices

    Grant number:25280016  2013.04 - 2018.03   Grant-in-Aid for Scientific Research(B)

  • Research on Logic Switching Activity Balanced Test for High-Quality Low-Cost LSIs

    Grant number:24650022  2012.04 - 2015.03   Grant-in-Aid for challenging Exploratory Research

  • Power-Adjustment-Based Testing for Next-Generation Low-Power LSI Circuits

    Grant number:22300017  2010.04 - 2013.03   Grant-in-Aid for Scientific Research(B)

  • VLSIの高品質フィールドテストに関する研究

    Grant number:21300015  2009.04 - 2012.03   基盤研究(B)

  • Test Technology for Avoiding Signal Degradation in Next-Generation LSI Circuis

    Grant number:19500047  2007.04 - 2010.03   Grant-in-Aid for Scientific Research(C)

  • LSI歩留まり向上のための誤テスト回避型テスト方式に関する研究

    Grant number:17500039  2005.04 - 2007.03   基盤研究(C)

  • マルチフォールトモデルを対象としたLSIのテストに関する研究

    Grant number:16500036  2004.04 - 2007.03   基盤研究(C)

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Contracts

  • Advanced Test Technology Development for Realizing Nano-CMOS LSI Circuits

    2011.04 - 2015.03

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    Grant type:Consigned research

  • 最先端半導体(cell/B.E.)を活用した超高速演算処理に関する実証試験

    2009.09 - 2010.03

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    Grant type:Consigned research

  • 高精度電力・ノイズ考慮テスト生成技術の研究

    2008.04 - 2009.03

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    Grant type:Joint research

  • Yield Improvement Platform for LSI Circuits

    2007.06 - 2012.03

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    Grant type:Consigned research

  • テスト時電力・ノイズ考慮テストの研究

    2007.06 - 2008.03

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    Grant type:Joint research

Other External Funds

  • Research on High-Quality LSI Test Methodology based on Checking and Removal of Test Clock Risks

    2015.04 - 2017.03

  • フィールド高信頼化のための回路・システム機構

    2008.10 - 2014.03

    CREST  

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    委託研究

  • マルチフォールトモデルを対象としたLSIのテストに関する研究

    2007.10 - 2008.03

    特定課題調査  

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    委託研究

  • 半導体集積回路の高信頼化に貢献する先端テスト技術の研究開発

    2007.09 - 2008.03

    地域新生コンソーシアム研究開発事業  

  • 自己検査・自己診断によるLSI高信頼化方式に関する研究

    2006.04 - 2008.03

    二国間交流事業共同研究・セミナー  

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    アメリカ合衆国, オーストラリア及び欧州諸国との共同研究

  • 半導体集積回路の低消費電力テスト技術の研究開発

    2006.04 - 2007.03

    平成18年度産学連携戦略・次世代産業創出事業(研究開発委託事業)  

  • 次世代LSIテスト設計自動化システムの研究開発

    2005.04 - 2007.03

    プラザ育成研究  

  • システムオンチップに対するテスト・診断の効率化技法に関する研究

    2004.04 - 2006.03

    アメリカ合衆国, オーストラリア及び欧州諸国との共同研究  

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    委託研究

  • VLSI Automatic Fault Diagnosis System Research and Development

    2004.04 - 2005.03

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Other Research Activities

  • Power-Aware Testing in the Era of IoT

    2021.10

  • Power-Aware Testing in the Era of IoT

    2021.10

  • Power-Aware Testing in the Era of IoT

    2020.07

  • Power-Aware Testing in the Era of IoT

    2019.11

  • Power-Aware LSI Testing ~ Challenges and Strategies ~

    2019.06

  • Power-Aware Testing in the Era of IoT

    2018.05

  • Power-Aware Testing in the Era of IoT

    2018.03

  • Power-Aware Testing in the Era of IoT

    2017.11

  • Power-Aware Testing and Test Strategies for Low Power Devices

    2012.11

  • チュートリアル @ ITC 2012 (Anaheim, USA)

    2012.11

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    Tutorial "Power-Aware Testing and Test Strategies for Low Power Devices" by P. Girard, N. Nicolici, and X. Wen

  • チュートリアル @ ISQED 2012 (Santa Clara, USA)

    2012.03

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    Tutorial "Power-Aware Testing and Test Strategies for Low Power Devices" by P. Girard, N. Nicolici, and X. Wen

  • チュートリアル @ ITC 2011 (Anaheim, USA)

    2011.09

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    Tutorial "Power-Aware Testing and Test Strategies for Low Power Devices" by P. Girard, N. Nicolici, and X. Wen

  • チュートリアル @ DATE 2011 (Grenoble, France)

    2011.03

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    Tutorial "Power-Aware Testing and Test Strategies for Low Power Devices" by P. Girard, N. Nicolici, and X. Wen

  • チュートリアル @ MWSCAS 2010 (Seattle, USA)

    2010.08

     More details

    Tutorial "Power-Aware Testing and Test Strategies for Low Power Devices" by P. Girard, N. Nicolici, and X. Wen

  • チュートリアル @ NEWCAS 2010 (Montreal, Canada)

    2010.06

     More details

    Tutorial "Power-Aware Testing and Test Strategies for Low Power Devices" by P. Girard, N. Nicolici, and X. Wen

  • Power-Aware Testing and Test Strategies for Low Power Devices

    2009.11

  • チュートリアル @ DATE 2008 (Munich, Germany)

    2008.03

     More details

    Tutorial "Power-Aware Testing and Test Strategies for Low Power Devices" by P. Girard, N. Nicolici, and X. Wen

  • チュートリアル @ リアライズ理工センター (日本, 東京)

    2007.06

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    "歩留まり向上に貢献するためのテスト技術の最新動向"

  • チュートリアル @ ETS 2007 (Freiburg, Germany)

    2007.05

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    Tutorial "Power Issues in Test" by N. Nicolici and X.Wen

  • チュートリアル @ リアライズ理工センター (日本, 東京)

    2006.01

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    "歩留まり向上に貢献するためのテスト技術の最新動向"

  • チュートリアル @ リアライズ理工センター (日本, 東京)

    2005.06

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    "歩留まり向上に貢献するためのテスト技術の最新動向"

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Activities of Academic societies and Committees

  • International Conference on VLSI Design (VLSID)   Program Committee Member (2019)  

    2019.01 - 2019.12

  • International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Program Committee Member (2019)  

    2019.01 - 2019.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2019)  

    2019.01 - 2019.12

  • IEEE Latin-American Test Symposium (LATS)   Regional Publicity Co-Chair (2018)  

    2018.01 - 2018.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • International Conference on VLSI Design (VLSID)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • IEEE International Conference on Computer Design (ICCD)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Co-Chair (2018)  

    2018.01 - 2018.12

  • IEEE International Test Conference in Asia (ITC-Asia)   Program Committee Co-Chair (2018)  

    2018.01 - 2018.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Program Committee Member (2018)  

    2018.01 - 2018.12

  • 国立研究開発法人科学技術振興機構「地域産学バリュープログラム」   専門委員  

    2017.04

  • 中国自然科学基金委員会   審査員  

    2017.04

  • IEEE Asian Test Symposium (ATS)   Best Paper Selection Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • International Doctoral Symposium on Applied Computation and Security Systems (ACSS)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • International Conference on VLSI Design (VLSID)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE International Conference on Computer Design (ICCD)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE International Conference on ASIC (ASICON)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE Latin-American Test Symposium (LATS)   Publicity Co-Chair (2017)  

    2017.01 - 2017.12

  • International Conference on Intelligent Green Building and Smart Grid   International Advisory Board Member (2017)  

    2017.01 - 2017.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2017)  

    2017.01 - 2017.12

  • International Doctoral Symposium on Applied Computation and Security Systems (ACSS)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Co-Chair (2016)  

    2016.01 - 2016.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • International Conference on VLSI Design (VLSID)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE International Conference on Computer Design (ICCD)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE Great Lake Symposium on VLSI   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE European Test Symposium (ETS)   Topic Chair (2016)  

    2016.01 - 2016.12

  • IEEE Latin-American Test Symposium (LATS)   Publicity Co-Chair (2016)  

    2016.01 - 2016.12

  • IEEE Asian Test Symposium (ATS)   Special Award Selection Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE European Test Symposium (ETS)   Best Paper Selection Committee Member (2016)  

    2016.01 - 2016.12

  • International Conference on VLSI Design (VLSID)   Best Paper Selection Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Co-Chair (2016)  

    2016.01 - 2016.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2016)  

    2016.01 - 2016.12

  • 国立研究開発法人科学技術振興機構「マッチングプランナープログラム」   専門委員  

    2015.04 - 2017.03

  • IEEE Transactions on VLSI Systems  

    2015.01

  • Journal of Electronic Testing: Theory and Applications  

    2015.01

  • IEEE Transactions on Computer-Aided Design   Best Paper Award Selection Committee Member (2015-2017)  

    2015.01 - 2017.12

  • IEEE European Test Symposium (ETS)   Topic Chair (2015)  

    2015.01 - 2015.12

  • International Conference on VLSI Design (VLSID)   Topic Vice-Chair (2015)  

    2015.01 - 2015.12

  • IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE International Conference on ASIC (ASICON)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • International Conference on VLSI Design (VLSID)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE International Conference on Computer Design (ICCD)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE Asian Test Symposium (ATS)   Ph.D. Thesis Contest Academic Jusy Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE Great Lake Symposium on VLSI   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE Latin-American Test Symposium (LATS)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2015)  

    2015.01 - 2015.12

  • 国立研究開発法人科学技術振興機構「研究成果最適展開支援プログラム」   専門委員  

    2014.04

  • Journal of Electronic Testing: Theory and Applications   Best Paper Award Selection Committee Member (2014-Present)  

    2014.01

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • International Conference on VLSI Design (VLSID)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Track Chair (2014)  

    2014.01 - 2014.12

  • IEEE European Test Symposium (ETS)   Topic Chair (2014)  

    2014.01 - 2014.12

  • IEEE Asian Test Symposium (ATS)   Ph.D. Thesis Contest Academic Jusy Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE Transactions on Computer-Aided Design   Advisory Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE Asia Pacific Conference on Circuits and Systms (APCCAS)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE International Conference on Computer Design (ICCD)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE Great Lake Symposium on VLSI   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE Latin-American Test Symposium (LATS)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2014)  

    2014.01 - 2014.12

  • IEEE International Reliability Innovations Conference (IRIC)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE Latin-American Test Symposium (LATS)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • International Conference on Advanced Technologies for Communications (ATC)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE Great Lake Symposium on VLSI   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE International Conference on ASIC (ASICON)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2013)  

    2013.01 - 2013.12

  • IEEE Transactions on Computer-Aided Design  

    2012.01 - 2017.12

  • Institute of Electrical and Electronics Engineers (IEEE)   IEEE CS Fellows Evaluation Committee Member (2012-2013)  

    2012.01 - 2013.12

  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE International Conference of Networking, Sensing and Control (ICNSC)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Panel Chair (2012)  

    2012.01 - 2012.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2012)  

    2012.01 - 2012.12

  • 日本学術振興会科学研究費委員会   審査員  

    2011.04

  • Institute of Electrical and Electronics Engineers (IEEE)   Co-Chair (CS-TTTC Technical Activity Committee on Power-Aware Testing)  

    2011.01

  • IEEE International Conference on ASIC (ASICON)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • Design Automation Conference (DAC)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE International Symposium on Electronic Design, Test and Applications (DELTA)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE/VSI VLSI Design And Test Symposium (VDAT)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2011)  

    2011.01 - 2011.12

  • 国立研究開発法人科学技術振興機構「A-STEP探索タイプ」   専門委員  

    2010.04

  • IEEE International Conference of Networking, Sensing and Control (ICNSC)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE International Symposium on Electronic Design, Test and Applications (DELTA)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • Design Automation Conference (DAC)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE/VSI VLSI Design And Test Symposium (VDAT)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2010)  

    2010.01 - 2010.12

  • Journal of Computer Science and Technology   編集委員  

    2009.01

  • Indian Journal of VLSI and Electronic System Design   編集委員  

    2009.01

  • IEEE/VSI VLSI Design And Test Symposium (VDAT)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • Design, Automation and Test in Europe Conference and Exhibition (DATE)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE International Conference on ASIC (ASICON)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2009)  

    2009.01 - 2009.12

  • 大分県 LSIクラスター形成推進会議   審査会委員・技術参与  

    2008.04 - 2018.03

  • Information Processing Society of Japan (IPSJ)  

    2008.04 - 2010.03

  • JST シーズ発掘試験査読評価委員会   委員  

    2008.04 - 2010.03

  • IEEE International Symposium on Electronic Design, Test and Applications (DFT)   Program Committee Member (2008-2016)  

    2008.01 - 2016.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Publicity Chair (2008)  

    2008.01 - 2008.12

  • IEEE International Conference on Computer Design (ICCD)   Program Committee Member (2008)  

    2008.01 - 2008.12

  • IEEE European Test Symposium (ETS)   Program Committee Member (2008)  

    2008.01 - 2008.12

  • IEEE International Symposium on Electronic Design, Test and Applications (DELTA)   Program Committee Member (2008)  

    2008.01 - 2008.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2008)  

    2008.01 - 2008.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2008)  

    2008.01 - 2008.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2008)  

    2008.01 - 2008.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2008)  

    2008.01 - 2008.12

  • 大分県 LSIクラスター形成推進会議   幹事会幹事  

    2007.05 - 2009.03

  • Reliability Engineering Association of Japan  

    2007.04 - 2016.03

  • Information Processing Society of Japan (IPSJ)  

    2007.04 - 2011.03

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Co-Chair (2007)  

    2007.01 - 2007.12

  • IEEE International Test Conference (ITC)   Program Committee Member (2007)  

    2007.01 - 2007.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Co-Chair (2007)  

    2007.01 - 2007.12

  • IEEE International Workshop on Defect and Adaptove Test Analysis (DATA)   Program Committee Member (2007)  

    2007.01 - 2007.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Co-Chair (2007)  

    2007.01 - 2007.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2007)  

    2007.01 - 2007.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2007)  

    2007.01 - 2007.12

  • 大分県産業創造機構 H18年度ジョブカフェモデル事業検討会議   委員  

    2006.05 - 2007.03

  • 福岡県 FIBA (Fukuoa International Business Association)   理事  

    2006.04 - 2009.03

  • 経済産業省 産学連携製造中核人材育成事業   教育サブグループ委員  

    2006.04 - 2007.03

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Local Arrangement Chair (2006)  

    2006.01 - 2006.12

  • IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS)   Program Committee Member (2006)  

    2006.01 - 2006.12

  • IEEE International Symposium on Electronic Design, Test and Applications (DELTA)   Program Committee Member (2006)  

    2006.01 - 2006.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2006)  

    2006.01 - 2006.12

  • IEEE International Test Conference (ITC)  

    2005.04

  • 大分県半導体クラスター 未来を担う若い人材の養成(ジョブカフェ)協議会   委員  

    2005.04 - 2006.03

  • 経済産業省 平成17年度「半導体電子部品・装置・部材・解析等の製造現場のプロフェッショナル育成事業」   委員  

    2005.04 - 2006.03

  • 東アジア経済交流推進機構 ウェハテストビジネス可能性検討委員会   委員  

    2005.03 - 2006.03

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2005)  

    2005.01 - 2005.12

  • Asian and South Pacific Design Automation Conference (ASP-DAC)   Program Committee Member (2005)  

    2005.01 - 2005.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2005)  

    2005.01 - 2005.12

  • 経済産業省 平成16年度製造現場の中核人材育成FS調査事業(半導体製造におけるテスト解析テクノロジストの育成)」の評価委員会   委員  

    2004.12 - 2005.02

  • IEEE International Symposium on Electronic Design, Test and Applications (DELTA)   Program Committee Member (2004)  

    2004.01 - 2004.12

  • IEEE Asian Test Symposium (ATS)   North America Liaison (2004)  

    2004.01 - 2004.12

  • Asian and South Pacific Design Automation Conference (ASP-DAC)   Program Committee Member (2004)  

    2004.01 - 2004.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2004)  

    2004.01 - 2004.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2004)  

    2004.01 - 2004.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2003)  

    2003.01 - 2003.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2003)  

    2003.01 - 2003.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2002)  

    2002.01 - 2002.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2002)  

    2002.01 - 2002.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2001)  

    2001.01 - 2001.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2001)  

    2001.01 - 2001.12

  • IEEE Workshop on RTL and High Level Testing (WRTLT)   Program Committee Member (2000)  

    2000.01 - 2000.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (2000)  

    2000.01 - 2000.12

  • Asian and South Pacific Design Automation Conference (ASP-DAC)   Program Committee Member (2000)  

    2000.01 - 2000.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (1999)  

    1999.01 - 1999.12

  • Asian and South Pacific Design Automation Conference (ASP-DAC)   Program Committee Member (1999)  

    1999.01 - 1999.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (1998)  

    1998.01 - 2018.12

  • Asian and South Pacific Design Automation Conference (ASP-DAC)   Program Committee Member (1998)  

    1998.01 - 1998.12

  • Asian and South Pacific Design Automation Conference (ASP-DAC)   Program Committee Member (1997)  

    1997.01 - 1997.12

  • International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability   Program Committee Member (1997)  

    1997.01 - 1997.12

  • IEEE Asian Test Symposium (ATS)   Program Committee Member (1997)  

    1997.01 - 1997.12

  • IEEE Great Lake Symposium on VLSI   Publicity Chair (1997)  

    1997.01 - 1997.12

▼display all

Social activity outside the university

  • 情報工学部サイエンスカフェ

    2018.07.10

     More details

    Type:Science cafe

    「高信頼LSI技術で情報化社会を守る」

  • 半導体テスト技術者検定問題出題・点検

    2013.04.01

     More details

    Type:Other

  • 半導体テスト技術ロードマップ説明会

    2012.06.11

     More details

    Type:Seminar, workshop

    主催者:大分県LSIクラスター形成推進会議
    役割:講師
    会場:大分県、大分県産業科学技術センター

  • 半導体製造・技術・工程管理改善講座

    2010.06.10

     More details

    Type:Seminar, workshop

    主催者:大分県LSIクラスター形成推進会議
    役割:講師
    会場:大分県、大分県産業科学技術センター

  • 半導体製造・技術・工程管理改善講座

    2009.05.14

     More details

    Type:Seminar, workshop

    主催者:大分県LSIクラスター形成推進会議
    役割:講師
    会場:大分県、大分県産業科学技術センター

  • 「半導体テスト技術者育成」ベーシック講座

    2008.11.07

     More details

    Type:Seminar, workshop

    主催者:大分県LSIクラスター形成推進会議
    役割:講師
    会場:大分県、大分県産業科学技術センター

  • 「半導体テスト技術者育成」ベーシック講座

    2008.07.14

     More details

    Type:Seminar, workshop

    主催者:大分県LSIクラスター形成推進会議
    役割:講師
    会場:大分県、大分県産業科学技術センター

  • 「半導体テスト技術者育成」ベーシック講座

    2007.12.13

     More details

    Type:Seminar, workshop

    主催者:大分県LSIクラスター形成推進会議
    役割:講師
    会場:大分県、アイネス

  • 産学連携製造中核人材育成事業

    2007.12.01

     More details

    Type:Seminar, workshop

    主催者:経済産業省
    役割:講師
    会場:大分県産業科学技術センター

  • DFTセミナー

    2007.06.29

     More details

    Type:Seminar, workshop

    主催者:リアライズ理工センター
    役割:講師
    会場:東京都、化学会館

  • 「半導体テスト技術者育成」ベーシック講座

    2007.06.22

     More details

    Type:Seminar, workshop

    主催者:大分県LSIクラスター形成推進会議
    役割:講師
    会場:大分県、アイネス

  • 産学連携製造中核人材育成事業

    2006.11.18

     More details

    Type:Seminar, workshop

    主催者:経済産業省
    役割:講師
    会場:大分県産業科学技術センター

  • DFTセミナー

    2006.08.03

     More details

    Type:Seminar, workshop

    主催者:リアライズ理工センター
    役割:講師
    会場:東京都、化学会館

▼display all