Faculty Profiles - WEN Xiaoqing

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MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator Reviewed International journal

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wen X.

Proceedings of the 2022 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2022 2022.01

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage Reviewed

Yan A., Dingl L., Zhou Z., Huang Z., Cui J., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2022-November 1 - 6 2022.01

GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators Reviewed International journal

Holst S., Bumun L., Wen X.

Proceedings of the Asian Test Symposium 2021-November 127 - 132 2021.01

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method Reviewed International journal

Yan A., Li Z., Gao Z., Zhang J., Huang Z., Ni T., Cui J., Wang X., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43 ( 7 ) 2205 - 2214 2024.07

A new die-level flexible design-for-test architecture for 3D stacked ICs Reviewed International journal

Zhang Q., Zhan W., Wen X.

Integration 97 2024.07

Efficient design approaches to CMOS full adder circuits Reviewed International journal

Yan A., Bao H., Jiang W., Cui J., Huang Z., Wen X.

Microelectronics Journal 149 2024.07

IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications Reviewed International journal

Yan A., Dong C., Guo X., Song J., Cui J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 19 - 24 2024.06

A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors Reviewed International journal

Xu H., Li J., Ma R., Liang H., Liu C., Wang S., Wen X.

IEEE Transactions on Device and Materials Reliability 24 ( 2 ) 302 - 312 2024.06

FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell Reviewed International journal

Yan A., Chen Y., Gao Z., Ni T., Huang Z., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 71 ( 4 ) 2299 - 2303 2024.04

SwinT-ILT: Swin Transformer embedding end-To-end mask optimization model Reviewed International journal

Xu H., Qi P., Tang F., Ma R., Liang H., Huang Z., Wen X.

Journal of Micro/Nanopatterning, Materials and Metrology 23 ( 1 ) 2024.01

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS Reviewed International journal

Yan A., Wang L., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32 ( 1 ) 116 - 127 2024.01

NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization Reviewed International journal

Huang Z., Sun L., Wang X., Liang H., Lu Y., Yan A., Pan J., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 60 ( 4 ) 4590 - 4600 2024.01

Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices Reviewed International journal

Yan A., Lin Z., Liu G., Zhang Q., Huang Z., Cui J., Wen X., Girard P.

Proceedings - IEEE International Symposium on Circuits and Systems 2024.01

Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications Reviewed International journal

Yan A., He Y., Huang Z., Yan W., Cui J., Wang X., Ni T., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2024.01

Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware Reviewed International journal

Ni T., Wen X., Amrouch H., Zhuo C., Song P.

ACM Transactions on Design Automation of Electronic Systems 29 ( 1 ) 2023.12

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness Reviewed International journal

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wang S., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 70 ( 12 ) 5074 - 5085 2023.12

RMC-NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel Reviewed International journal

Xu D., Ouyang Y., Zhou W., Huang Z., Liang H., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 ( 12 ) 2061 - 2074 2023.12

An AI-Driven VM Threat Prediction Model for Multi-Risks Analysis-Based Cloud Cybersecurity Reviewed International journal

Saxena D., Gupta I., Gupta R., Singh A.K., Wen X.

IEEE Transactions on Systems, Man, and Cybernetics: Systems 53 ( 11 ) 6815 - 6827 2023.11

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications Reviewed International journal

Yan A., Cao A., Huang Z., Cui J., Ni T., Girard P., Wen X., Zhang J.

IEEE Transactions on Emerging Topics in Computing 11 ( 4 ) 1070 - 1081 2023.10

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting Reviewed International journal

SHI Shiling, HOLST Stefan, WEN Xiaoqing

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E106.D ( 10 ) 1694 - 1704 2023.10

Language：English Publishing type：Research paper (scientific journal)

High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

DOI： 10.1587/transinf.2023EDP7011

Kyutacar

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An equivalent processing method for integrated circuit electrical parameter data using BP neural networks Reviewed International journal

Zhan W., Zhang L., Feng X., Pan P., Cai X., Wen X.

Microelectronics Journal 139 2023.09

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications Reviewed International journal

Yan A., Xiang J., Chang Y., Huang Z., Cui J., Girard P., Wen X.

Microelectronics Journal 139 2023.09

Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata Reviewed International journal

Yan A., Li X., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland) 12 ( 14 ) 2023.07

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications Reviewed International journal

Yan A., Wei S., Zhang J., Cui J., Song J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 167 - 171 2023.06

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications Reviewed International journal

Yan A., Chang Y., Xiang J., Luo H., Cui J., Huang Z., Ni T., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 293 - 298 2023.06

Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array Reviewed International journal

Chen N., Cheng F., Han C., Jiang J., Wen X.

Tsinghua Science and Technology 28 ( 2 ) 330 - 343 2023.04

SASL-JTAG: A Light-Weight Dependable JTAG Reviewed International journal

Wang S., Wei S., Ma J., Kai H., Higami Y., Takahashi H., Shimizu A., Wen X., Ni T.

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023.01

Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling Reviewed International journal

Shi S., Holst S., Wen X.

Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 501 - 507 2023.01

Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning Reviewed International journal

Nie M., Jiang W., Yang W., Wang S., Wen X., Ni T.

Proceedings of the Asian Test Symposium 2023.01

Design of Low-Cost Approximate CMOS Full Adders Reviewed International journal

Yan A., Wei S., Li Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2023-May 2023.01

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness Reviewed International journal

Yan A., Zhou C., Wei S., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023.01

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications Reviewed International journal

Yan A., Xiang J., Huang Z., Ni T., Cui J., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023.01

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell Reviewed International journal

Holst S., Ma R., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2023-May 2023.01

Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications Reviewed International journal

Yan A., Li X., Gao Z., Huang Z., Ni T., Wen X.

Proceedings of the Asian Test Symposium 2023.01

A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery Reviewed International journal

Yan A., Li X., Ni T., Huang Z., Wen X.

Proceedings - 2023 10th International Conference on Dependable Systems and Their Applications, DSA 2023 474 - 476 2023.01

A Low Overhead and Double-Node-Upset Self-Recoverable Latch Reviewed International journal

Yan A., Xia F., Ni T., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023.01

A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges Reviewed International journal

Ni T., Li F., Peng Q., Wang S., Wen X.

Proceedings of the 2023 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2023 2023.01

A High-Performance and P-Type FeFET-Based Non-Volatile Latch Reviewed International journal

Yan A., Chen Y., Huang Z., Cui J., Wen X.

Proceedings of the Asian Test Symposium 2023.01

A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design Reviewed International journal

Yan A., Wei S., Chen Y., Fan Z., Huang Z., Cui J., Girard P., Wen X.

Micromachines 13 ( 11 ) 2022.11

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications Reviewed International journal

Yan A., Qian K., Song T., Huang Z., Ni T., Chen Y., Wen X.

Integration 86 22 - 29 2022.09

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology Reviewed International journal

Yan A., Zhou Z., Wei S., Cui J., Zhou Y., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 255 - 260 2022.06

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications Reviewed International journal

Yan A., He Z., Xiang J., Cui J., Zhou Y., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 261 - 266 2022.06

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications Reviewed International journal

Yan A., Chen Y., Song S., Zhai Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 333 - 338 2022.06

A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center Reviewed International journal

Saxena D., Gupta I., Kumar J., Singh A.K., Wen X.

IEEE Systems Journal 16 ( 2 ) 3163 - 3174 2022.06

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications Reviewed International journal

Yan A., Xiang J., Cao A., He Z., Cui J., Ni T., Huang Z., Wen X., Girard P.

IEEE Transactions on Device and Materials Reliability 22 ( 2 ) 282 - 295 2022.06

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications Reviewed International journal

Yan A., Fan Z., Ding L., Cui J., Huang Z., Wang Q., Zheng H., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 58 ( 1 ) 517 - 529 2022.02

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments Reviewed International journal

Yan A., Li Z., Huang S., Zhai Z., Cheng X., Cui J., Ni T., Wen X., Girard P.

Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 1257 - 1262 2022.01

Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments Reviewed International journal

Yan A., Xu Z., Feng X., Cui J., Chen Z., Ni T., Huang Z., Girard P., Wen X.

IEEE Transactions on Emerging Topics in Computing 10 ( 1 ) 404 - 413 2022.01

Broadcast-TDMA: A Cost-Effective Fault Tolerance Method for TSV Lifetime Reliability Enhancement Reviewed International journal

Ni T., Bian J., Yang Z., Nie M., Yao L., Huang Z., Yan A., Wen X.

IEEE Design and Test 39 ( 5 ) 34 - 42 2022.01

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications Reviewed International journal

Yan A., Qian K., Cui J., Cui N., Huang Z., Wen X., Girard P.

Proceedings of the IEEE VLSI Test Symposium 2022-April 2022.01

Power-Aware Testing in the Era of IoT Reviewed International journal

Wen X.

Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022 2022.01

Power and Energy Safe Real-Time Multi-Core Task Scheduling Reviewed International journal

Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 16 - 21 2022.01

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits Reviewed International journal

Utsunomiya T., Hoshino R., Miyase K., Lu S.K., Wen X., Kajihara S.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 43 - 48 2022.01

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS Reviewed International journal

Yan A., Song S., Zhang J., Cui J., Huang Z., Ni T., Wen X., Girard P.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 73 - 78 2022.01

A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters Reviewed International journal

Yan A., Song S., Chen Y., Cui J., Huang Z., Wen X.

Proceedings of the IEEE Conference on Nanotechnology 2022-July 215 - 218 2022.01

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC Reviewed International journal

Ni T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40 ( 9 ) 1952 - 1956 2021.09

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications Reviewed International journal

Yan A., Cao A., Xu Z., Cui J., Ni T., Girard P., Wen X.

Journal of Electronic Testing: Theory and Applications (JETTA) 37 ( 4 ) 489 - 502 2021.08

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments Reviewed

Yan A., Cao A., Fan Z., Xu Z., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 301 - 306 2021.06

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications Reviewed

Yan A., He Z., Zhou J., Cui J., Ni T., Huang Z., Wen X., Girard P.

Microelectronics Journal 111 2021.05

A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology Reviewed

Ni T., Yang Z., Chang H., Zhang X., Lu L., Yan A., Huang Z., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 2 ) 724 - 734 2021.04

Reliability-Driven Neuromorphic Computing Systems Design Reviewed

Xu Q., Wang J., Geng H., Chen S., Wen X.

Proceedings -Design, Automation and Test in Europe, DATE 2021-February 1586 - 1591 2021.02

TPDICE and SIM based 4-node-upset completely hardened latch design for highly robust computing in harsh radiation Reviewed

Yan A., Ding L., Shan C., Cai H., Chen X., Wei Z., Huang Z., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2021-May 2021.01

On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption Reviewed

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E104D ( 6 ) 816 - 827 2021.01

Language：English Publishing type：Research paper (scientific journal)

Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

DOI： 10.1587/transinf.2020EDP7042

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Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS Reviewed

Yan A., Lai C., Zhang Y., Cui J., Huang Z., Song J., Guo J., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 1 ) 520 - 533 2021.01

Cellular Structure Based Fault-Tolerance TSV Configuration in 3D-IC Reviewed

Xu Q., Sun W., Chen S., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 5 ) 1196 - 1208 2021.01

Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing Reviewed International journal

Yan A., Zhai Z., Wang L., Zhang J., Cui N., Ni T., Wen X.

Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 2021.01

LSI Testing: A Core Technology to a Successful LSI Industry Invited Reviewed International journal

Wen X.

Proceedings of International Conference on ASIC 2021.01

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning Reviewed International journal

Xu Q., Geng H., Chen S., Yuan B., Zhuo C., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3492 - 3502 2021.01

Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure Reviewed International journal

Xu Q., Ni T., Geng H., Chen S., Yu B., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3182 - 3187 2021.01

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch Reviewed International journal

Yan A., Qian K., Cui J., Cui N., Ni T., Huang Z., Wen X.

2021 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021 2021.01

A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets Reviewed International journal

Yan A., Cao A., Qian K., Ding L., He Z., Fan Z., Wen X.

Proceedings - 2021 8th International Conference on Dependable Systems and Their Applications, DSA 2021 734 - 736 2021.01

Novel Speed-and-Power-Optimized SRAM Cell Designs with Enhanced Self-Recoverability from Single- And Double-Node Upsets Reviewed

Yan A., Chen Y., Hu Y., Zhou J., Ni T., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 12 ) 4684 - 4695 2020.12

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets Reviewed

Yan A., Chen Y., Zhou J., Cui J., Ni T., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2020-November 2020.11

Logic Fault Diagnosis of Hidden Delay Defects Reviewed

Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

Proceedings - International Test Conference 2020-November 2020.11

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC Reviewed

Ni T., Chang H., Song T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 67 ( 11 ) 2657 - 2661 2020.11

Design of double-upset recoverable and transient-pulse filterable latches for low-power and low-orbit aerospace applications Reviewed

Yan A., Chen Y., Xu Z., Chen Z., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 5 ) 3931 - 3940 2020.10

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors Reviewed

Dou Z., Yan A., Zhou J., Hu Y., Chen Y., Ni T., Cui J., Girard P., Wen X.

Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 35 - 40 2020.09

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications Reviewed

Yan A., Xu Z., Yang K., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 4 ) 2666 - 2676 2020.08

HITTSFL: Design of a cost-effective HIS-Insensitive TNU-Tolerant and SET-Filterable latch for safety-critical applications Reviewed

Yan A., Feng X., Zhao X., Zhou H., Cui J., Ying Z., Girard P., Wen X.

Proceedings - Design Automation Conference 2020-July 2020.07

Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment Reviewed

Yan A., Hu Y., Cui J., Chen Z., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computers 69 ( 6 ) 789 - 799 2020.06

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments Reviewed

Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 2 ) 1163 - 1171 2020.04

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs Reviewed

Yan A., Ling Y., Cui J., Chen Z., Huang Z., Song J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 3 ) 879 - 890 2020.03

Dual-interlocked-storage-cell-based double-node-upset self-recoverable flip-flop design for safety-critical applications Reviewed

Yan A., Xu Z., Cui J., Ying Z., Huang Z., Liang H., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2020-October 2020.01

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications Reviewed

Yan A., Wu Z., Zhou J., Hu Y., Chen Y., Ying Z., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2019-December 55 - 60 2019.12

Targeted partial-shift for mitigating shift switching activity hot-spots during scan test Reviewed

Holst S., Shi S., Wen X.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2019-December 124 - 129 2019.12

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications Reviewed

Yan A., Wu Z., Lu L., Chen Z., Song J., Ying Z., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2019-December 43 - 48 2019.12

Variation-aware small delay fault diagnosis on compressed test responses Reviewed

Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings - International Test Conference 2019-November 2019.11

A fault-tolerant MPSoC for CubeSats Reviewed International journal

Fuchs C., Chou P., Wen X., Murillo N., Furano G., Holst S., Tavoularis A., Lu S., Plaat A., Marinis K.

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 2019.10

A static method for analyzing hotspot distribution on the LSI Reviewed

Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 73 - 78 2019.09

A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells Reviewed International journal

Song Z., Yan A., Cui J., Chen Z., Li X., Wen X., Lai C., Huang Z., Liang H.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 139 - 144 2019.09

Power-Aware Testing for Low-Power VLSI Circuits Invited Reviewed International journal

X. Wen

15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits Paper S12-1 2019.06

Small Delay Fault Diagnosis with Compacted Responses Reviewed International journal

S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich

Poster at ACM Design Automation Conf. 2019.06

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications Reviewed International journal

Yan A., Hu Y., Song J., Wen X.

Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 1679 - 1684 2019.05

STAHL: A novel scan-test-aware hardened latch design Reviewed International journal

Ma R., Holst S., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2019-May 2019.05

Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout Reviewed International journal

Yan A., Wu Z., Guo J., Song J., Wen X.

IEEE Transactions on Reliability 68 ( 1 ) 354 - 363 2019.03

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults Reviewed International journal

Ni T., Yao Y., Chang H., Lu L., Liang H., Yan A., Huang Z., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 ( 10 ) 2938 - 2951 2019.01

Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets Reviewed

Yan A., Zhou J., Hu Y., Cui J., Huang Z., Girard P., Wen X.

IEEE Access 7 176188 - 176196 2019.01

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing Reviewed International journal

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018.12

Message from the Technical Program Co-Chairs Invited Reviewed International journal

Li H., Wen X., Huang Z.

Proceedings of the Asian Test Symposium 2018-October 2018.12

Foreword Reviewed International journal

Li X., Li H., Cheng K.T.T., Wen X.

Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018 2018.09

The impact of production defects on the soft-error tolerance of hardened latches Reviewed International journal

Holst S., Ma R., Wen X.

Proceedings of the European Test Workshop 2018-May 1 - 6 2018.06

Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM Reviewed International journal

I. Syafalni, T. Sasao, X. Wen

Proceedings of the 27th International Workshop on Logic and Synthesis 124 - 131 2018.06

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application Reviewed International journal

A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

IEEE Transactions on Circuits and Systems II: Express Briefs 66 ( 2 ) 287 - 291 Early Access 2018.06

A Method to Detect Bit Flips in a Soft-Error Resilient TCAM Reviewed International journal

I. Syafalni, T. Sasao, X. Wen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 ( 6 ) 1185 - 1196 2018.06

The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches Reviewed International journal

S. Holst, R. Ma, X. Wen

Proceedings of IEEE European Test Symposium Paper 7A-1 2018.05

Design Automation for Legacy Circuits Reviewed International journal

I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies 174 - 179 2018.03

Locating Hot Spot with Justification Techniques in a Layout Design Reviewed International journal

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

Proceedings of IEEE Workshop on RTL and High Level Testing Paper S1.2 2017.11

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption Reviewed International journal

Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian

Proceedings of the Asian Test Symposium 140 - 145 2017.11

Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors Reviewed International journal

S. Holst, E. Schneider, H. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen

Proceedings - International Test Conference 2017-December 1 - 8 Paper 3.4 2017.10

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips Reviewed International journal

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Transactions on Emerging Topics in Computing 8 ( 3 ) 591 - 601 Early Access 2017.10

Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs Reviewed International journal

T. Ni, M. Nie, H. Liang, J. Bian, X. Xu, X. Fang, Z. Huang, X. Wen

IEICE Electronics Express 18 ( 14 ) Letter 20170590 2017.10

GPU-Accelerated Simulation of Small Delay Faults Reviewed International journal

E. Schneider, M. Kochte, S. Holst, X. Wen, H. Wunderlich

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 ( 5 ) 829 - 841 2017.05

On Optimal Power-Aware Path Sensitization Reviewed International journal

Workshop of Test and Reliability for Circuits and Systems 2017.03

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding Reviewed International journal

Xiang D., Wen X., Wang L.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 ( 3 ) 942 - 953 2017.03

Vernier ring based pre-bond through silicon vias test in 3D ICs Reviewed International journal

Ni Tianming, Nie Mu, Liang Huaguo, Bian Jingchang, Xu Xiumin, Fang Xiangsheng, Huang Zhengfeng, Wen Xiaoqing

IEICE Electronics Express ( The Institute of Electronics, Information and Communication Engineers ) 14 ( 18 ) 20170590 - 20170590 2017.01

Language：English Publishing type：Research paper (scientific journal)

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.

DOI： 10.1587/elex.14.20170590

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85030178580&origin=inward

Logic-Path-and-Clock-Path-Aware at-Speed Scan Test Generation Reviewed International journal

F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara

2016.12

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Reviewed International journal

LI Fuqiang, WEN Xiaoqing, MIYASE Kohei, HOLST Stefan, KAJIHARA Seiji

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( The Institute of Electronics, Information and Communication Engineers ) E99A ( 12 ) 2310 - 2319 2016.12

Language：English Publishing type：Research paper (international conference proceedings)

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power-safety without significant test vector count inflation and test quality loss.

DOI： 10.1587/transfun.E99.A.2310

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84999232940&origin=inward

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST Reviewed International journal

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Asian Test Symposium 203 - 208 2016.11

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test Reviewed International journal

Holst S., Schneider E., Wen X., Kajihara S., Yamato Y., Wunderlich H., Kochte M.

IEEE Asian Test Symposium 19 - 24 2016.11

On Optimal Power-Aware Path Sensitization Reviewed International journal

Sauer M., Jiang J., Reimer S., Miyase K., Wen X., Becker B., Polian I.

IEEE Asian Test Symposium 179 - 184 2016.11

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test Reviewed International journal

Eggersglub S., Holst S., Tille D., Miyase K., Wen X.

Proceedings of the Asian Test Symposium 173 - 178 2016.11

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures Reviewed International journal

CHEN Tian, SHEN Dandan, YI Xin, LIANG Huaguo, WEN Xiaoqing, WANG Wei

IEICE Transactions on Information and Systems ( The Institute of Electronics, Information and Communication Engineers ) E99D ( 11 ) 2672 - 2681 2016.11

Language：English Publishing type：Research paper (scientific journal)

Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, X-filling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

DOI： 10.1587/transinf.2015EDP7289

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84994577136&origin=inward

Power-Aware Testing For Low-Power VLSI Circuits Invited Reviewed International journal

X. Wen

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings 585 - 588 Paper S37-1 2016.10

Authorship：Corresponding author Language：English Publishing type：Research paper (international conference proceedings)

China Hangzhou 2016.10.25 - 2016.10.28

DOI： 10.1109/ICSICT.2016.7998986

Kyutacar

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85028640934&origin=inward

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM Reviewed International journal

Syafalni I., Sasao T., Wen X.

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016-September 679 - 684 2016.07

SAT-Based Post-Processing for Regional Capture Power Reduction in at-speed scan test generation Reviewed International journal

Eggersgluss S., Miyase K., Wen X.

IEEE European Test Symposium 2016-July 2016.05

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill Reviewed International journal

D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35 ( 3 ) 499 - 512 2016.03

Test Pattern Modification for Average IR-Drop Reduction Reviewed International journal

W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen

IEEE Transactions on VLSI Systems 24 ( 1 ) 38 - 49 2016.01

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch Reviewed International journal

IEEE Asian Test Symposium 103 - 108 2015.11

Power Supply Noise and Its Reduction in At-Speed Scan Testing Invited Reviewed International journal

X. Wen

IEEE International Conference on ASIC Paper B5-3 2015.11

Authorship：Lead author,　Last author,　Corresponding author Language：English Publishing type：Research paper (international conference proceedings)

China Chengdu 2015.11.03 - 2015.11.06

DOI： 10.1109/ASICON.2015.7516980

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84982256034&origin=inward

A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys Reviewed International journal

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

24th International Workshop on Logic and Synthesis 2015.06

Identification of High Power Consuming Areas with Gate Type and Logic Level Information Reviewed International journal

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE European Test Symposium Paper 9.1 2015.05

A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys Reviewed International journal

IEEE European Test Symposium Poster 2.4 2015.05

GPU-Accelerated Small Delay Fault Simulation Reviewed International journal

E. Schneider, S. Holst, M.-A. Kochte, X. Wen, H.-J. Wunderlich

Design and Test in Europe 1174 - 1179 2015.03

Towards Memory-Aware VLSI Simulation Algorithms for Heterogeneous Architectures Reviewed International journal

S. Holst, J. Miyazaki, X. Wen

International Symposium on Applied Engineering and Sciences 2014.12

Soft-Error Tolerant TCAMs for High-Reliability Packet Classification Reviewed International journal

IEEE Asia Pacific Conference on Circuits and Systems 471 - 474 2014.11

Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal

E. Schneider, S. Holst, X. Wen, H. Wunderlich

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD 17 - 23 2014.11

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed International journal

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEICE Transactions on Information and Systems E97 ( 10 ) 2706 - 2718 2014.10

An X-Filling Method for Low-Capture-Power Scan Test Generation

Li Fuqiang, Wen Xiaoqing, Miyase Kohei, Holst Stefan, Kajihara Seiji

IEICE technical report. Dependable computing ( The Institute of Electronics, Information and Communication Engineers ) 114 ( 99 ) 15 - 20 2014.06

Language：English Publishing type：Research paper (conference, symposium, etc.)

In order to generate a low capture power test pattern, we propose an X-filling method to suppress local switching activity (LSA), which is a local signal value transition metric that has a strong correlation with IR-Drop. In this method, after having divided the layout of a circuit into unit areas and then determined the priorities of X bits in a test cube based on the LSA of each unit area, we assign to X bits appropriate logic values which are easy to propagate. Experimental results show that the proposed method can effectively reduce the LSA in unit areas.

Other Link： https://ci.nii.ac.jp/naid/110009925706

Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits Reviewed International journal

E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

ACM Design Automation Conference Poster 2014.06

Low-power testing for 2D/3D devices and systems Reviewed International journal

235 - 277 2014.01

ATPG Enhancement Technology Reviewed International journal

IEEE Workshop on RTL and High Level Testing Paper IV.5.S 2013.11

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Reviewed International journal

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE Asian Test Symposium 19 - 24 2013.11

Search Space Reduction for Low-Power Test Generation Reviewed International journal

IEEE Asian Test Symposium 171 - 176 2013.11

Test Pattern Modification for Average IR-drop Reduction Reviewed International journal

J. Li, W-S. Ding, H-Y. Hsieh, X. Wen

IEEE International Test Conference Poster 2013.09

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Reviewed International journal

K. Miyase, R. Sakai, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

IEICE Transaction on Information and Systems E96-D ( 9 ) 2003 - 2011 2013.09

SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction Reviewed International journal

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop Paper 4.4 2013.07

Controllability Analysis of Local Switching Activity for Layout Design Reviewed International journal

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

Workshop on Design and Test Methodologies for Emerging Technologies Paper 2 2013.05

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing Reviewed International journal

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE Design & Test of Computers 30 ( 4 ) 60 - 70 2013.04

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression Reviewed International journal

26th International Conference on VLSI Design 279 - 284 2013.01

Fault Detection with Optimum March Test Algorithm Reviewed International journal

N. Zakaria, W. Hassan, I. Halin, R. Sidek, X. Wen

Journal of Theoretical and Applied Information Technology 47 ( 1 ) 18 - 27 2013.01

Estimation of the Amount of Don't-Care Bits in Test Vectors Reviewed International journal

K. Miyase, S. Kajihara, X. Wen

IEEE Workshop on RTL and High Level Testing 2012.11

A Transition Isolation Scan Cell Design for Low Shift and Capture Power Reviewed International journal

Y.-T. Lin, J.-L Huang, X. Wen

IEEE Asian Test Symposium 107 - 112 2012.11

On Pinpoint Capture Power Management in At-Speed Scan Test Generation Reviewed International journal

X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE International Test Conference Paper 6.1 2012.11

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains Reviewed International journal

S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang

ACM Transactions on Design Automation of Electronic Systems 17 ( 4 ) Article No. 48 2012.10

A Transition Isolation Scan Cell Design for Low Shift and Capture Power Reviewed International journal

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop 2012.07

Power-Aware Testing: The Next Stage Invited Reviewed International journal

X. Wen

IEEE European Test Symposium Invited Talk 2012.05

Authorship：Corresponding author Language：English Publishing type：Research paper (international conference proceedings)

France Annecy 2012.05.28 - 2012.06.01

DOI： 10.1109/ETS.2012.6233000