研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示 >> ／全件表示339 件中 1 - 339 件目

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications 査読有り国際誌

Yan A., He Y., Niu X., Cui J., Ni T., Huang Z., Girard P., Wen X.

IEEE Design and Test 40 ( 4 ) 34 - 41 2023年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

This article proposes a robust and low power flip-flop cell with complete double-node-upset (DNU) tolerance for aerospace applications. The proposed cell is constructed from a master latch and a slave latch. The master latch comprises two C-elements as well as one clock-controlled C-element; the slave latch is similar to the master but has an extra keeper to avoid high-impedance state of the output-level C-element. The proposed cell can provide complete DNU-tolerance while reducing power dissipation by 65x0025; on average when compared with existing radiation-hardened flip-flop cells.

DOI： 10.1109/MDAT.2023.3267747

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Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata 査読有り国際誌

Yan A., Liu R., Cui J., Ni T., Girard P., Wen X., Zhang J.

IEEE Transactions on Circuits and Systems II: Express Briefs 70 ( 6 ) 2256 - 2260 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it a promising candidate to replace the complementary metal oxide semiconductor (CMOS) technology. Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this brief, we propose two types of excess-3 code (XS-3) based BCD adders (XS-3DAs). We use ripple-carry adders (RCA) and parallel binary adders (PBA) to construct XS-3DAs in QCA Designer tool, respectively. The PBA-based XS-3DA is constructed with a new correction logic. 4-bit, 8-bit, and 16-bit XS-3DAs are constructed based on the two proposed XS-3DAs, respectively. Comparisons show that, with the increase of design scaling, the delay and area-delay product (ADP) of the PBA-based XS-3DAs can be significantly reduced in comparison with that of the RCA-based XS-3DAs. Compared with the 16-digit RCA-based XS-3DA, the cell count, area, delay and ADP of the proposed 16-digit PBA-based XS-3DA are reduced by 37.88%, 25.99%, 37.68% and 53.88%, respectively.

DOI： 10.1109/TCSII.2023.3237695

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LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42 ( 6 ) 2069 - 2073 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

DOI： 10.1109/TCAD.2022.3213212

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Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 59 ( 3 ) 2885 - 2897 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low-cost version of the QRHIL), for highly robust computing in harsh radiation environments. First, the QRHIL that mainly consists of a 5 × 5 looped C-element matrix is proposed. Then, to reduce overhead, the QRHIL-LC that mainly uses 24 interlocking C-elements is proposed. Both latches can self-recover from any QNU, while the QRHIL-LC has a low cost compared to the QRHIL. Simulation waveforms show the QNU-recoverability of the proposed QRHIL and QRHIL-LC latches. Moreover, compared with the QRHIL latch, the QRHIL-LC can approximately save power dissipation by 16% and silicon area by 5%.

DOI： 10.1109/TAES.2022.3219372

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Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion 査読有り国際誌

Zhou W., Ouyang Y., Xu D., Huang Z., Liang H., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 ( 4 ) 442 - 455 2023年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

As technology feature sizes diminish to the nanometer regime, the leakage power crisis has become a major challenge in network-on-chip (NoC) design. Power gating (PG) is used to mitigate growing leakage power as an effective static power-saving technique. Applying PG in a multiple NoC (Multi-NoC) rather than a traditional NoC is a promising solution. However, limited by the channel width of the subnets, the increase in packet length will bring a severe serialization issue and performance loss. Previous Multi-NoC schemes have to wake up more subnets to minimize the performance loss, which also sacrifices their energy efficiency. In this article, we introduce an architecture, namely, BandExp, which allows subnets to expand their bandwidth by utilizing the idle physical links of other subnets. More bandwidth helps subnets mitigate the serialization issue and reduce the performance loss. Meanwhile, other subnets gain longer sleep cycles and thus save more energy. Evaluation results indicate that compared to the state-of-the-art Catnap, the proposed architecture reduces the average packet latency and execution time of different benchmarks by 19.3% and 3.2%, respectively. Also, the net static energy of the network is reduced by 23.2% on average, while the incurred area overhead is only 1.3%.

DOI： 10.1109/TVLSI.2023.3244859

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High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology 査読有り国際誌

Yan A., Zhou Z., Ding L., Cui J., Huang Z., Wen X., Girard P.

Proceedings -Design, Automation and Test in Europe, DATE 2023-April 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the advancement of CMOS technologies, circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). To effectively provide nonvolatility as well as tolerance against DNUs caused by radiation, this paper proposes a nonvolatile and DNU resilient latch that mainly comprises two magnetic tunnel junction (MTJ), two inverters and eight C-elements. Since two MTJs are used and all internal nodes are interlocked, the latch can provide nonvolatility and recovery from all possible DNUs. Simulation results demonstrate the nonvolatility, DNU recovery and high performance of the proposed latch.

DOI： 10.23919/DATE56975.2023.10136927

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Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates 査読有り国際誌

Yan A., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland) 11 ( 10 ) 2022年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata is a novel nanotechnology that has the advantages of low energy dissipation, easy integration, and high computing speed. It is regarded as one of the powerful alternative technologies for the next generation of integrated circuits because of its unique implementation concept. In this paper, two XOR/XNOR gates are proposed. Level-sensitive T flip-flops, negative edge-trigger T flip-flops, two-to-one multiplexers, reversible gates, and (8, 4) polar encoders are implemented based on these two proposed logic gates. Simulation results show that, compared with the existing level-sensitive T flip-flops, the second proposed level-sensitive T flip-flop has fewer cells and lower energy dissipation; compared with the best (8, 4) polar encoder, the cell count and area of the second proposed (8, 4) polar encoder are decreased by 13.67% and 12.05%, respectively. The two XOR/XNOR gates have a stable output and low energy dissipation, which can be flexibly designed into complex quantum-dot cellular automata circuits.

DOI： 10.3390/ELECTRONICS11101658

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Evaluation and Test of Production Defects in Hardened Latches 査読有り国際誌

Ma R., Holst S., Wen X., Yan A., Xu H.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E105D ( 5 ) 996 - 1009 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (PTVF), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed PTVF metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.

DOI： 10.1587/transinf.2021EDP7216

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A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage 査読有り

Yan A., Dingl L., Zhou Z., Huang Z., Cui J., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2022-November 1 - 6 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With technology scaling down, the vulnerability of circuits to radiation and the increase of static power have become severe concerns. Spintronic devices such as magnetic tunnel junction (MTJ) have been developed to cope with many concerns, among which reliability concerns [1]. Spintronic devices have attractive properties, such as non-volatility and compatibility with conventional CMOS fabrication process. Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magnetic latch, namely M-TPDICE, that can completely tolerate single-node upsets (SNUs) and double-node upsets (DNUs). Simulations of the proposed latch with the HSPICE tool with a 45 nm CMOS technology model have demonstrated the effectiveness of the proposed latch.

DOI： 10.1109/ATS56056.2022.00013

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MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator 査読有り国際誌

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wen X.

Proceedings of the 2022 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2022 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the potential at the input flips too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses propagating in the circuit. We study the effect of jitter on the output of the XOR gate when the XOR gate has high-speed changing inputs. Excessively small short pulses will be eliminated in the circuit and suppresses the accumulation of jitter in the oscillator. Our proposed TRNG cleverly avoids the concatenation of the short pulses with the inverter so that the short pulses are only input to the XOR gate, affecting the oscillation of the circuit by interfering with the change of the XOR gate output by another input change. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA, making it comparable to the state-of-the-art TRNG also implemented on FPGAs. The results show that this TRNG has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.

DOI： 10.1109/AsianHOST56390.2022.10022291

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GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators 査読有り国際誌

Holst S., Bumun L., Wen X.

Proceedings of the Asian Test Symposium 2021-November 127 - 132 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Systolic arrays are currently used in autonomous systems such as self-driving cars to accelerate the enormous amount of matrix operations necessary for DNN inference. The reliability of such accelerators are of utmost importance since any loss in DNN accuracy due to erroneous calculations can have dire consequences. We propose a novel method to measure accuracy losses caused by arbitrary timing faults in systolic arrays. Our GPU-based simulation system enables for the first time a complete and accurate timing simulation of all inference-related matrix operations on large systolic arrays. A single consumer-grade GPU can simulate a LeNet-5 at a throughput of about 13s per inference. Furthermore, our simulation approach readily scales to larger DNNs and multiple GPUs.

DOI： 10.1109/ATS52891.2021.00034

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QART: A low-power quadruple-node-upset hardened latch based on asymmetric ring topology 査読有り国際誌

Huang Z., Yang S., Wu J., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

Microelectronics Journal 176 2026年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

As CMOS technology continues to scale down, the charge sharing effect has made multiple-node upsets a critical challenge to the reliability of integrated circuits. Existing quadruple-node upset (QNU) hardened latches commonly suffer from large area, high power consumption, and excessive overall overhead. This paper proposes a highly robust, low-power quadruple-node upset self-recoverable latch named QART (Quadruple-upset Asymmetric Ring Topology). The latch adopts an asymmetric bipartite graph architecture, consisting of 11 four-input variant C-elements (CE-4) and 11 two-input inverter (PN) cells interleaved into a ring network. It utilizes node parity isolation and ring-offset mapping to sever cascaded fault paths within the same group. HSPICE simulation based on a 45 nm CMOS process shows that the QART latch achieves complete QNU self-recovery. Compared with conventional QNU self-recovery structures (QRHIL, MURLAV, RS-QTRL), the power consumption, area-power-delay product (APDP), and setup time are reduced by averages of 60.57%, 60.61%, and 18.51%, respectively, and the overall overhead is significantly superior to that of similar self-recovery structures. In addition, for latches composed of heterogeneous cells, this paper proposes a heterogeneous worst-case path tracing algorithm based on discrete state convergence, which improves the self-recovery rate verification efficiency by more than 99.9% compared to conventional SPICE fault injection simulation.

DOI： 10.1016/j.mejo.2026.107358

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LOSTA: A low-overhead high-defect-detectability test-aware hardened latch with layout-aware short-defect modeling 査読有り国際誌

Xu H., Zhao Z., Ma R., Holst S., Wang S., Liang H., Wen X.

Microelectronics Journal 175 2026年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

Many hardened latch designs employ cell-internal redundancy to mitigate soft errors. However, this redundancy tends to mask manufacturing defects, rendering them difficult to detect. Furthermore, such undetected defects can compromise the soft-error resilience of hardened latches. To enhance defect-detectability while preserving high soft-error tolerance, several scan-test-aware hardened latch designs integrate Design-For-Test (DFT) techniques, which inevitably incur substantial overhead. Moreover, existing short-defect models used to evaluate the defect detectability of test-aware hardened latches are derived from netlist node combinations, without accounting for actual physical wire placement. To address these challenges, this paper proposes a novel low-overhead, high-defect-detectability scan-test-aware hardened latch (LOSTA), and introduces a layout-aware short-defect-modeling method based on the open-source tool KLayout to evaluate test-aware hardened latch designs. In addition, within the proposed defect-modeling framework, tailored net-pair spacing guidelines are incorporated into the layout design of LOSTA to increase defect coverage (DC). Simulation results demonstrate that, compared to state-of-the-art test-aware hardened latches, the proposed LOSTA latch achieves the highest DC while realizing an average reduction of 40.90% in power consumption, 33.26% in delay, 52.96% in area overhead, and 85.83% in power-delay-area product (PDAP), respectively.

DOI： 10.1016/j.mejo.2026.107314

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A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values 査読有り国際誌

Ni T., Rui W., Zhuo C., Li Y., Wen X., Nie M.

ACM Transactions on Design Automation of Electronic Systems 31 ( 4 ) 2026年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

Wafer acceptance testing (WAT) is a process that is used to assess the quality and reliability of manufactured wafers. This technique for the early detection and screening of chips allows for improvements in their reliability and performance during the manufacture of semiconductor devices. The automatic test equipment (ATE) used for processing millions of wafers is susceptible to a number of issues, including the absence of data values, the presence of redundant parameters, and categorical imbalance. These issues increase the cost of data processing and impede an investigation into the relationship between WAT and feature diagnostics. In this study, we propose a method with a low test escape rate based on a multi-objective optimization algorithm to reduce the cost of testing and minimize the number of defective dice that go undetected. The proposed method retains outliers, dynamically selects the range of the neighborhood to reduce the cost of testing, and uses Shapley values to analyze a WAT dataset to determine the importance of features of the data. The multi-objective optimization algorithm ranks features by their importance and applies an adaptive method to eliminate features with a low overall correlation, thereby reducing the risk that defective dice are undetected.

DOI： 10.1145/3716826

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LTTL: A Low-Overhead and Triple-Node-Upset-Tolerant Latch Design for Aerospace Applications 査読有り国際誌

Ma Z., Gao Z., Guo X., Liu Q., Man Y., Liang H., Wen X.

Glsvlsi 2026 Proceedings of the Great Lakes Symposium on VLSI 2026 187 - 193 2026年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the feature size of the CMOS technology keeps scaling down, the charge sharing caused by radiation is becoming more and more prominent, and the occurrence possibility of the triple-node upset (TNU) increases significantly. In this paper, we propose a low-overhead and TNU-tolerant latch (LTTL) that leverages three parallel storage cells and an output-level error interceptive module to achieve complete TNU tolerance while minimizing design overhead. The optimized structure eliminates redundant devices and employs a high-speed D-to-Q path, significantly reducing delay-area-power product (DAPP). Even any three nodes of the latch are flipped at the same time, the output of the latch can retain the original value. Simulation results not only confirm the TNU tolerance of the proposed latch but also demonstrate that the latch can provide a 57% reduction in delay, 20% reduction in area, and 62% reduction in DAPP on average compared to state-of-the-art TNU-tolerant latches.

DOI： 10.1145/3787109.3815297

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High-Accuracy, Low-Utilization Multichannel 2-ps Bin Size FPGA Digital-to-Time Converter Based on Compact Multidimensional Delay Array 査読有り国際誌

Chen P., Wijaya J.A., Chen C., Wen X., Holst S.

IEEE Transactions on Very Large Scale Integration VLSI Systems 34 ( 6 ) 1930 - 1939 2026年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Digital-to-time converter (DTC) or digital delay/timing generator has been developed for quite many years and plays a crucial role in automatic test equipment (ATE) and built-in self-test (BIST) industries. This study proposes a compact multidimensional delay array DTC based on phase shift in a phase-locked loop (PLL) to further extend field-programmable gate array (FPGA) applications into the analog domain. All internal delay cells are precisely controlled by PLL from the beginning to make the output phases distributed within the reference clock period as uniformly as possible. For further resolution enhancement, a hybrid structure based on PLL and a multidimensional delay array is presented to ensure high enough accuracy and substantially reduce logic utilization through phase sorting and selection. For concept proving, the proposed four-channel DTC is implemented on an Altera Stratix IV FPGA board to achieve 20 internal control bits, 2-ps resolution with very low integral nonlinearity (INL) and differential nonlinearity (DNL) of -2.06 to 2.01 and -2.50 to 2.31 LSB, respectively. In addition, the circuit has been successfully implemented on a much cheaper Cyclone IV platform also for cost reduction to achieve the same resolution with the best fine stage INL and DNL of -3.81 to 3.56 and -3.93 to 4.41 LSB, respectively. The DTC performance has demonstrated improvements to that of prior arts by one order finer resolution and higher accuracy compared to non-Vernier prior works, while eliminating the serious dead time issues inherent in Vernier DTCs.

DOI： 10.1109/TVLSI.2026.3676373

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Design of Quintuple-Node-Upset Hardened Latches Based on C-Element Voting and an Analog Voter 査読有り国際誌

Huang Z., Yang S., Wu J., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

IEEE Transactions on Device and Materials Reliability 26 ( 2 ) 604 - 615 2026年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

As nanometer-scale CMOS technology continues to advance, the susceptibility of memory cells to soft errors has significantly increased. Single-event multiple-node upsets (MNUs) have become a critical factor affecting integrated circuit reliability. This paper first proposes a self-recoverable double-node-upset (DNU) hardened latch (DSAR) based on the Soft-Error Aware Read-Decoupled (SAR) latch. Building upon this, a Quad-SAR latch capable of tolerating Quintuple-node upset (QtNU) is designed through dual DSAR redundancy and a two-stage C-element (CE) voting mechanism, achieving an optimized balance in area, power consumption, and delay. Furthermore, to address the high-impedance-state (HIS) sensitivity issue of C-elements, a Quint-SAR latch is achieved in this paper through the implementation of Quintuple-modular redundancy (QMR) combined with an Analog Voter (AV). This structure not only effectively tolerates QtNUs, but its incorporated Analog Voter features HIS insensitivity and offers significant low-overhead advantages compared to traditional voters. Extensive fault injection, PVT fluctuation, and negative bias temperature instability (NBTI) aging effect simulations verify the reliability of the proposed designs. HSPICE simulation results show that both the Quad-SAR and Quint-SAR latches possess QtNU tolerance capability and achieve a good balance in hardware overhead. Quad-SAR is suitable for low-power and low-delay requirements in non-HIS-sensitive scenarios, while Quint-SAR, with its HIS immunity, becomes the preferred solution for high-robustness scenarios. Compared to QNU-hardened and QtNU-hardened latches, their area-power-delay product (APDP) exhibits a decrease of 49.41% and 17.16%, respectively, and their setup time exhibits a decrease of 35.10% and 49.71%, respectively.

DOI： 10.1109/TDMR.2026.3680306

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Hi-ILT: A hybrid End-to-End framework of lightweight hierarchical VAE and physics-Guided ILT for inverse lithography technology 査読有り国際誌

Xu H., Wang T., Zhao Z., Ma R., Wen X., Liang H.

Optics and Lasers in Engineering 200 2026年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

Optical Proximity Correction (OPC) is a core technology for compensating lithographic diffraction effects in advanced manufacturing processes. Although Inverse Lithography Technology (ILT) enables high-precision mask optimization, it faces challenges in balancing mask printability and optimization efficiency due to three key problems: (1) low-quality initial solutions, (2) high computational overhead, and (3) the inability of pure data-driven methods to accurately model Sub-Resolution Assist Features (SRAF). To address these problems, this paper proposes Hi-ILT, an end-to-end OPC framework that integrates lightweight deep learning and physical ILT correction. A lightweight Convolutional Neural Network (CNN) first generates a high-precision initial mask at low resolution, with a Binary-Straight-Through Estimator (BSTE) resolving binarization gradient vanishing to stabilize training and achieve fast convergence. Subsequently, a gradient descent based ILT correction layer performs fine-grained optimization of mask details (especially SRAF) at high resolution and models process variations. Experiments on 32 nm node M1 layouts (ICCAD 2013 benchmark) and 10 large-scale datasets demonstrate that Hi-ILT outperforms state-of-the-art methods. Compared to deep learning-based ILT methods, it reduces L<inf>2</inf> error by up to 30.1%, Process Variation Band (PVB) by up to 19.8%, and Edge Placement Error (EPE) violations by up to 73.4%; compared to gradient descent-based ILT methods, it shortens end-to-end Turn Around Time (TAT) by up to 69.4% while maintaining higher precision. Hi-ILT effectively achieves a balance between high printability and efficient optimization, making it suitable for advanced lithography requirements.

DOI： 10.1016/j.optlaseng.2026.109621

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Functional Fault Impact Probability Prediction using Spatio-Temporal Graph Convolutional Network 査読有り国際誌

Wei S., Wang S., Kai H., Higami Y., Ma R., Ni T., Wen X., Takahashi H.

ACM Transactions on Design Automation of Electronic Systems 31 ( 5 ) 2026年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

Logic-level defects that escape manufacturing tests pose reliability risks in modern systems and require functional testing to identify their activation and propagation behaviors. However, effective functional testing is limited by the high cost of long-cycle fault simulations. To address this challenge, we propose a Spatio-Temporal Graph Convolutional Network framework to efficiently and accurately predict the Fault Impact Probability on the circuit's function cross-over multiple function cycles, enabling rapid quantitative assessment of functionally possible faults. Our method represents gate-level netlists as spatio-temporal graphs, capturing both structural connectivity and short-range signal-propagation dynamics. With dedicated spatial and temporal encoders, the proposed ST-GCN enables accurate prediction of multi-cycle circuit-level FIP. Experiments on ISCAS’89 benchmarks show that the approach reduces fault-simulation cost by over an order of magnitude while maintaining high accuracy (mean absolute error as low as 0.024 for 5-cycle predictions). The framework supports both testability-metric-based and simulation-based feature construction, enabling a tunable balance between efficiency and accuracy. A case study on test point selection further demonstrates that using predicted FIPs to guide observation-point placement improves the detectability of multi-cycle, hard-to-detect circuit-level faults. Overall, this work provides a scalable solution for circuit-level multi-cycle fault-impact assessment and can be readily integrated into functional test generation and other Electronic Design Automation workflows.

DOI： 10.1145/3798106

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105042557905&origin=inward

Nonvolatile Flip-Flop Designs with Soft Error Recovery Based on Magnetic Tunnel Junction and CMOS for Aerospace Applications 査読有り国際誌

Gao Z., Liu H., Song J., Pei Z., Jiang W., Wang Q., Wen X.

Journal of Electronic Testing Theory and Applications JETTA 42 ( 2 ) 249 - 257 2026年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the semiconductor technology advances, soft errors caused by radiative particles are becoming a major concern for power-sensitive digital circuits in aerospace applications. Radiation hardening by design (RHBD) and magnetic tunnel junction (MTJ) are employed to cope with these issues. In this paper, two novel non-volatile flip-flops (FFs) are proposed, both of which can fully recover from all single- and double-node upsets (DNUs). The embedded MTJs are non-volatile and compatible with the conventional CMOS process. Comprehensive simulations show that the proposed flip-flops have excellent DNU-recovery and non-volatility at the cost of a low increase in area overhead. The proposed flip-flops reduce the delay by 21.99% and the power by 46.18%, on average, compared to state-of-the-art non-volatile flip-flops.

DOI： 10.1007/s10836-026-06226-5

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Incremental learning strategies for improved detection of unknown defects in wafer maps with limited samples 査読有り国際誌

Ni T., Jiang W., Liang H., Wen X., Nie M.

Computers in Industry 175 2026年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

Accurate detection of a wide range of defect patterns on wafers is crucial for enhancing chip yield and ensuring the reliability of semiconductor manufacturing systems. As this process becomes increasingly complex, new types of defects — referred to as unknown defects — emerge on wafers. Traditional pattern recognition methods struggle in this setting because limited samples are insufficient to effectively train deep learning models. Moreover, these models are prone to catastrophic forgetting when incrementally trained on new defect classes. To address these challenges, this paper proposes a method termed Few-Shot Class Contrastive Incremental Learning (FCCIL) for unknown wafer map defect detection. FCCIL integrates a contrastive learning network for distinguishing novel defect types and an incremental learning model for dynamic knowledge updating—both designed to mitigate catastrophic forgetting, thereby enabling the detection of unknown defects in wafer maps with limited data. Experimental results demonstrate a 4% improvement in forgetting resistance over state-of-the-art approaches, confirming the effectiveness of FCCIL in real-world semiconductor manufacturing scenarios.

DOI： 10.1016/j.compind.2025.104432

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105026613282&origin=inward

Design and verification of a robust near-memory computing architecture for image fusion tasks 査読有り国際誌

Yan A. (Heifei University of Technology), Bao H. (Heifei University of Technology), Cui J. (Heifei University of Technology), Waris H., Li J. (Heifei University of Technology), Wen X.

Microelectronics Journal 168 2026年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the development of data-intensive applications, traditional von-Neumann architectures face the “storage wall” bottleneck, limiting the performance and energy efficiency of computing systems. Near-memory computing (NMC) mitigates this problem by integrating compute units near memory, enabling data to be processed in-situ. In this study, a novel near-memory computing architecture is designed and applied to the image fusion tasks with an approximate full adder. By integrating basic compute units near the storage module, local data-weighted processing reduces the performance-aware overhead of data migration. Experimental results show that, the designed approximate full adder reduces power consumption, delay and power-area-delay product (PADP) by an average of 4.3 %, 95.29 % and 94.49 %, respectively. Compared with the traditional von-Neumann architecture, the performance of the designed near-memory computing architecture is improved by 40 %. This solution realizes the energy efficiency optimization while maintaining the integrity of image fusion functionality, validating the feasibility of near-memory computing in lightweight image processing tasks.

DOI： 10.1016/j.mejo.2025.107006

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A Highly Robust and Low-Cost Multiple Node Upset Resilient Fast Latch for Radiation Applications 査読有り国際誌

Bai N., Wang F., Xu Y., Wang S., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 62 4411 - 4421 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the size of semiconductor processes continues to shrink and deep space exploration continues to advance, the design of multiple-node-upset (MNU)-resilient latches has become indispensable for radiation hardening by design (RHBD). The C-element (CE) and the clock-gated C-element (CG-CE) are the basic elements for most conventional MNU-resilient latches. However, most MNU-resilient latches improve the antiradiation ability with the redundant nodes or redundant CE and CG-CE, causing a large area overhead. Some other MNU-resilient latches have less area overhead but have less antiradiation ability. To overcome this problem, this article proposes a corresponding MNU resilient latch design named HLDRF. The proposed design consists of a generation module and a feedback module. The generation module transfers the generation nodes’ voltage to the feedback module, whereas the feedback module feeds the feedback nodes’ voltage back to the generation nodes through the pull-up/pull-down paths of the CE. This bidirectional interaction forms a closed-loop feedback circuit, ensuring a strong antiradiation ability. The proposed latch can fix errors quickly through feedback loops and without causing the propagation of faulty logic. The proposed latch achieves an optimal balance between area overhead and radiation hardness, offering superior comprehensive performance for deep space exploration. Furthermore, the proposed latch exhibits a lower sensitivity to process, supply voltage, and temperature variations compared to similar latches.

DOI： 10.1109/TAES.2026.3651658

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ACDRL: Aging-Mitigated C-Elements Based Double-Node-Upset-Recoverable Latch for Long-Term Reliability Enhancement 査読有り国際誌

Dong C. (Heifei University of Technology), Yan A. (Heifei University of Technology), Guo X. (Heifei University of Technology), Pei Z. (Heifei University of Technology), Wang Q. (Heifei University of Technology), Huang Z. (Heifei University of Technology), Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 62 6645 - 6652 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Soft errors and aging are two major factors impacting the long-term reliability of integrated circuits, especially for aerospace applications. Double-node upset (DNU) and bias-temperature instability (BTI) are typical soft errors and aging, respectively. First, this article presents a C-elements (CEs) based DNU-recoverable latch, namely the basic latch, without aging mitigation to ensure low overhead. Second, in order to alleviate BTI-induced aging, the BTI-mitigated CEs are proposed so as to construct the aging-mitigated CEs based DNU-recoverable latch, namely ACDRL, for long-term reliability enhancement. By optimizing the key CEs internal structure, the stress time of transistors in feedback loops can be effectively reduced to mitigate the impact of BTI on the latch. Pertinent simulation results demonstrate that the proposed latches have DNU recoverability; the soft error rate increase due to BTI is reduced by roughly 35% for ACDRL compared with the basic latch; the delay of ACDRL is almost not affected, and the area and power increase of ACDRL are limited compared with the BTI-unmitigated latches.

DOI： 10.1109/TAES.2026.3665491

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Algorithm-Aided Design and Verification for Multiple-Node-Upset-Recovery Latches 査読有り国際誌

Pei Z., Li J., Waris H., Younis M.S., Yan A., Deng J., Gui Y., Wen X.

Proceedings IEEE International Symposium on Circuits and Systems 4063 - 4067 2026年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In advanced CMOS technologies, integrated circuits are becoming increasingly sensitive to soft errors in radiation environments. The design process of existing latches heavily relies on electronic design automation (EDA) tools with comprehensive error-injection-based robustness verification. In this paper, algorithm-aided design and verification for robust latches are proposed and then, three algorithm-aided latches (i.e., SURLAD, DURLAD, and TURLAD) respectively providing SNU-, DNU-, and TNU-recovery are proposed. These latches are recoverable from single-node-upsets (SNUs) and multiple-node upsets (MNUs), respectively. Verification results demonstrate the robustness and advantages in terms of delay and power overhead of the proposed latches compared with state-of-the-art latches.

DOI： 10.1109/ISCAS66217.2026.11562619

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Automated Co-Optimization Framework of Feature Selection and Ensemble Learning for Wafer Yield Prediction 査読有り国際誌

Ni T., Wu H., Cheng M., Bian J., Wang S., Wen X., Nie M.

IEEE Transactions on Automation Science and Engineering 23 11245 - 11257 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Efficient and automated wafer yield prediction is central to cost control and process optimization in intelligent semiconductor manufacturing. As the initial testing stage in wafer inspection, Wafer Acceptance Testing (WAT) data contain critical process-related information. However, its high dimensionality, redundancy, and nonlinear inter-dependencies pose significant challenges to conventional yield prediction models, such as high computational overhead and limited generalization capability. Moreover, existing approaches often lack an automated framework capable of jointly addressing feature redundancy and model complexity. This paper proposes a collaborative and automated prediction framework that integrates feature selection and machine learning. First, an enhanced Binary Zebra Population Optimization Algorithm (BZPOA) is introduced, which incorporates redesigned exploration and development mechanisms to automatically identify key feature subsets from high-dimensional parameters, substantially reducing data redundancy and computational dimensionality. Second, a Bayesian hyperparameter-optimized XGBoost model is constructed, utilizing the Tree-structured Parzen Estimator (TPE) to achieve deep co-optimization of model parameters and feature space, thereby overcoming the inefficiency and overfitting issues commonly associated with manual parameter tuning. Experiments on a real-world dataset demonstrate that the proposed framework achieves average Recall, Precision, and F1-scores of 0.872, 0.917, and 0.902, respectively. Compared with the full-feature baseline, the BZPOA-selected feature subset improves predictive performance by 5%-10%, attains an AUC of 0.904, and significantly reduces per-wafer prediction time. Cross-factory transfer experiments further confirm the robustness of the proposed system. Note to Practitioners - In semiconductor manufacturing, wafer yield prediction is a critical link for ensuring production capacity and reducing costs. Traditional methods face challenges such as high-dimensional test data redundancy and complex model tuning, resulting in low prediction efficiency and weak generalization ability. This paper proposes a collaborative automation framework that achieves end-to-end optimization from raw data to yield prediction by integrating feature selection and machine learning. This method is applicable to early yield monitoring during the wafer testing stage and can be integrated into existing automated testing systems, facilitating real-time quality feedback and process adjustments.

DOI： 10.1109/TASE.2026.3700731

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FN2LD: FeFET-based nonvolatile and node-upset-recovery latch designs with cost optimization 査読有り国際誌

Yan A. (Heifei University of Technology), Jiang W. (Heifei University of Technology), Wang H. (Heifei University of Technology), Kang B. (Heifei University of Technology), Huang Z. (Heifei University of Technology), Ni T., Wen X., Girard P.

Microelectronics Journal 167 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Nonvolatile memory based on FeFETs demonstrates outstanding energy management capabilities, making it highly promising for energy-harvesting and battery-powered Internet of Things applications. Concurrently, the reduction in transistor dimensions and the increased integration of semiconductor circuits are intensifying the requirements for circuit robustness with protection against soft errors. In this paper, an innovative nonvolatile and single-node-upset-recovery latch, namely FN<sup>2</sup>LD-1, which does not require any additional control signals, is proposed. In addition, to further address the double-node-upset (DNU) threat in radiative environments, this paper also presents for the first time a FeFET-based nonvolatile and DNU-tolerant latch, namely FN<sup>2</sup>LD-2. Simulation results based on Cadence Virtuoso validate that the proposed latches provide nonvolatility and node-upset-recovery with low overhead. Compared with alternative nonvolatile latches, FN<sup>2</sup>LD-1 reduces delay by 67.54 % and delay-power-area product by 25.47 % on average, and FN<sup>2</sup>LD-2 reduces delay by 82.87 % and delay-power-area by 9.88 % on average, respectively.

DOI： 10.1016/j.mejo.2025.106975

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105021471135&origin=inward

Locating Hotspots based on Switching Probability Calculation and Functional Analysis with Partial Truth Table 査読有り国際誌

OGATA Yuusei, YAMASHITA Tomoya, MIYASE Kohei, LU Shyue-Kung, WEN Xiaoqing

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人電子情報通信学会 ) advpub ( 0 ) 1638 - 1648 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

<p>When IR-drop in LSI testing becomes excessive in a certain area of LSI, it causes excessive delay, resulting in test malfunction (over-testing). This is because power consumption in the test mode is generally much higher than in the normal mode. Excessive IR-drop does not occur in the entire area of a circuit, but in certain areas where a large number of switching activities occur (such areas are called hotspots in this work). In order to avoid test malfunction, it is important to develop a method to reduce or control IR-drop in the hotspots. Locating hotspots is a necessary technique to reduce or control IR-drop effectively and efficiently. In this work, we propose a method to locate hotspots caused in the test mode by switching probability calculation and functional analysis with partial truth table. Experimental results for IWLS2005 OpenCores circuits demonstrate the proposed method can support to locate hotspots.</p>

DOI： 10.1587/transfun.2025eap1221

その他リンク： https://www.jstage.jst.go.jp/article/transfun/advpub/0/advpub_2025EAP1221/_pdf

Low-Delay, High-Robustness DNU Self-Healing Latch Based on the C-Element Feedback Loop 査読有り国際誌

Bai N., Xu P., Xu Y., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 62 5974 - 5985 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the impact of various radiations in the space environment on the reliability of latch circuits increases, this article proposes a low-delay double node upset (DNU) self-healing latch (LDDSL). The LDDSL latch is implemented based on a C-element feedback loop, enabling all internal node pairs to undergo DNU self-healing. The incorporation of high-speed channels between inputs and outputs significantly reduces delay time. The LDDSL latch achieves the lowest delay compared to existing latches with DNU-hardening, in terms of 15.59% less power consumption, a reduced 42.61% delay, and a remarkable 38.11% reduction in PDAP. Furthermore, the LDDSL latch demonstrates lower or comparable sensitivity to process, voltage, and temperature variations when compared to the reference latch designs.

DOI： 10.1109/TAES.2026.3660817

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105029957023&origin=inward

RMC PUF: A Highly Reliable PUF Architecture Based on Recursive Markov Chain Obfuscation 査読有り国際誌

Huang Z., Yang Z., Sun X., Lu Y., Bian J., Ouyang Y., Ni T., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 34 ( 8 ) 2558 - 2570 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Physical unclonable functions (PUFs) are critical hardware security primitives that extract entropy from intrinsic manufacturing process variations (MPVs) to generate unique cryptographic responses. They have demonstrated extensive application prospects in lightweight encryption and authentication for Internet of Things (IoT) devices. However, the classic arbiter PUF (APUF) is inherently vulnerable to machine learning (ML) modeling attacks due to the linear mathematical model of its delay circuits. To address this challenge, this article proposes a novel postprocessing obfuscation architecture named recursive Markov chain PUF (RMC PUF). The proposed architecture couples an APUF core with Markov obfuscation modules. By exploiting the intermediate stage responses of the APUF as an entropy source, the system constructs a 1-D recursive stochastic state transition mechanism. This approach recursively transforms and obfuscates the raw entropy based on Markov Chain theory, achieving a PUF system with stability and robust resistance against ML attacks. Through this efficient recursive obfuscation strategy, the design achieves precise utilization of the APUF’s intrinsic entropy. The work is validated through both numerical simulation and FPGA prototyping. Experimental results show that the prototype maintains a high reliability of 98.9%–99.9% within a voltage range of 0.8–1.2 V, and a reliability of 96.1%–99.7% within a temperature range from −10 <sup>◦</sup>C to 80 <sup>◦</sup>C. Comparative analysis indicates that the proposed RMC PUF significantly outperforms existing structures in security, limiting the prediction accuracy of four ML attack models [logistic regression (LR), artificial neural networks (ANNs), deep neural networks (DNNs), and covariance matrix adaptive evolutionary strategy (CMA-ES)] to no more than 54.72%.

DOI： 10.1109/TVLSI.2026.3693479

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A Challenge-Response Remapping Reliability Enhancement Method for APUF Based on Adjacent Challenge-Bit Flipping 査読有り国際誌

Lin Y., Gao B., Bian J., Liang H., Huang Z., Wen X.

IEEE Internet of Things Journal 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the rapid development of the Internet of Things (IoT), security issues in resource-constrained devices have become increasingly critical. Physical Unclonable Function (PUF) exploits unavoidable process variations introduced during IC manufacturing to generate unique responses and has been widely used for device authentication and cryptographic key generation. Among various PUF architectures, the Arbiter PUF (APUF) can generate a large number of challenge-response pairs (CRPs) with low hardware overhead. However, its reliability is highly sensitive to environmental variations and device aging, which may degrade the security of authentication protocols. In this paper, a challenge-response remapping reliability enhancement method for APUF based on adjacent challenge-bit flipping is proposed. First, a machine learning (ML) algorithm is employed to construct a software model of the APUF. A delay difference threshold is then introduced to identify challenges whose accumulated propagation delay differences fall below the threshold. Subsequently, specific adjacent bits in these challenges are flipped to transform them into highly reliable challenges. The proposed method is evaluated through Python-based simulations and FPGA-based hardware measurements. Experimental results show that the simulated reliability of the APUF can be improved to 100% under three environmental noise conditions. Moreover, within a temperature range from −20°C to 80°C, the measured reliability of the APUF can also reach 100% without reducing the number of available CRPs. Therefore, the proposed method significantly improves the reliability of APUFs without introducing additional hardware overhead or reducing the number of available CRPs, providing an effective solution for high-reliability authentication in IoT devices.

DOI： 10.1109/JIOT.2026.3731598

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A method for integrated circuit trimming focused on separation of trim codes 査読有り国際誌

Zhan W., Zhou Y., Zheng J., Wen X.

Microelectronics Reliability 174 2025年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In advanced processes, the addition of trimming circuits can effectively improve the yield of high-end chips. However, the mapping relationship between trimming parameters and trim codes in traditional methods is often segmented and discontinuous. This paper proposes a method that separates the trim codes into computational trim codes and applied trim codes. By reconstructing the mapping relationships between trimming parameters and computational trim codes, as well as between computational trim codes and applied trim codes, the proposed method achieves a linear mapping relationship between trimming parameters and computational trim codes, and a logical relationship between computational trim codes and applied trim codes. This novel method effectively reduces the number of trimming iterations and trimming time, thereby improving trimming efficiency. Two different hardware and software-based implementations have been designed to validate its feasibility. Experiments using two optimization algorithms demonstrate that trimming time can be reduced by an average of 44.97% and 40.00%, respectively, fully validating the effectiveness of the proposed method.

DOI： 10.1016/j.microrel.2025.115889

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A lightweight general PUF framework for resisting machine learning attacks 査読有り国際誌

Ni T., Li F., Huang Z., Yan A., Wang S., Wen X., Nie M., Bian J.

Integration 104 2025年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

Physical Unclonable Function (PUF) is an attractive and low-cost security primitive that requires no storage and is resistant to reverse engineering. However, classical PUFs are highly vulnerable to machine learning attacks, and most attempts to resist these attacks consume excessive resources. To address this challenge, a lightweight general PUF framework is proposed in this paper. Firstly, the framework adopts segmentation processing to introduce structural nonlinearities for the purpose of self-protection. Secondly, the pre-segment response, pre-segment challenges and post-segment challenges undergo XOR processing to introduce challenges obfuscation, which greatly enhances the machine learning resistance of the PUF. In addition, for configurable RO PUF, a novel MUX-based RO (called MRO) is proposed in this paper, which can save resources by 50 %. Implementing a two-segment MRO-MRO instance based on the proposed PUF framework results in reliability, uniformity, and uniqueness that are close to the ideal values. Comprehensive experiments demonstrate that the proposed PUF has the advantages of scalable framework, low resource overhead, and strong resistance to machine learning attacks.

DOI： 10.1016/j.vlsi.2025.102459

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SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices 査読有り国際誌

OKAMOTO Hisashi, WEI Shaoqi, WANG Senling, KAI Hiroshi, TAKAHASHI Hiroshi, HIGAMI Yoshinobu, SHIMIZU Akihiro, NI Tianming, WEN Xiaoqing

Journal of Communications ( Engineering and Technology Publishing ) 20 ( 2 ) 214 - 220 2025年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

Joint Test Action Group (JTAG) interface is widely used in integrated circuits for functional testing and in-system debugging, ensuring high reliability throughout the silicon life cycle. However, it has also been identified as a potential vulnerability to the cyberattacks. Traditional security countermeasures such as adding authentication mechanism to restrict access to authorized users, often rely on uniform authentication credentials. This approach poses challenges for edge devices with varying computational capacities. Moreover, strengthening authentication security can lead to compatibility issues with embedded hardware on client devices, limiting scalability. To address these challenges, we propose Simple and Secure password authentication protocol, Light processing version based Joint Test Action Group plus Version (SASL-JTAG+), an enhanced JTAG authentication mechanism utilizing the Simple and Secure Password Authentication Protocol, Light Processing Version (SAS-L) protocol that enables one-time password authentication with adjustable bit lengths, tailored to the computational capacities of authenticators and target devices. The new approach provides robust security for devices with performance and cost constraints, offering flexible authentication data within a unified system. As a result, SASL-JTAG+ provides a scalable, long-term solution for securing IoT systems accommodating both legacy and modern devices while adapting to evolving technological demands.

その他リンク： https://ehime-u.repo.nii.ac.jp/records/2003018

An enhanced interlocked feedback structure-based dual-node upset resilient latch 査読有り国際誌

Bai N., Liu Z., Wen X., Xu Y., Wang Y., Chen J., Zhu W.

Microelectronics Journal 157 2025年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the integrated circuit technology continues to scale down, the design of Double Node Upset (DNU) resilient latches has become a critical challenge in radiation-hardened design. Traditional designs of resilient latches are primarily based on the Dual Interlocked Storage Cell (DICE) and novel feedback mechanisms. However, these conventional approaches often suffer from significant limitations, such as instability or errors in logic states due to charge sharing during latching, or trade-offs among power consumption, delay, and area. To overcome these challenges, this paper proposes a DNU-resilient latch based on an enhanced interlocked feedback structure. The proposed ISR latch leverages its interlocked feedback mechanism to achieve self-recovery for the maximum number of double-node upset pairs. Simulation results based on the SMIC 28 nm process model demonstrate that the proposed latch can achieve self-recovery under any double-node disturbance. Compared to existing advanced DNU-resilient latches, the proposed design shows superior performance and power efficiency, achieving an average reduction of 81.67% in PDAP.

DOI： 10.1016/j.mejo.2025.106555

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85215210615&origin=inward

A Method for Grading Failure Rates Within the Dynamic Effective Space of Integrated Circuits After Testing 査読有り国際誌

Zhan W., Zhou Y., Zheng J., Cai X., Zhang Q., Wen X.

Applied Sciences Switzerland 15 ( 4 ) 2025年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

Integrated circuits that pass testing still have quality differences, thus making grading necessary. Traditional grading methods rely on static testing and electrical measurements, which are challenging to achieve precise grading, time-consuming, and costly. A new grading method based on the failure rate within a dynamically effective space is proposed. This method dynamically adjusts the evaluation space and uses an exponential decay function to calculate the influence weight of each neighboring chip on the evaluated chip, thereby computing the weighted failure rate of the evaluated chip and quantitatively grading the chips after wafer testing based on the scores. Experiments show that this method not only accurately captures quality differences and ensures grading accuracy but also significantly improves grading efficiency.

DOI： 10.3390/app15042009

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85218465975&origin=inward

TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications 査読有り国際誌

Yan A. (合肥工業大学), Zhang J., Xu X., Li H., Bai N., Huang Z., Wang X., Wen X., Girard P.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 10 ) 2783 - 2794 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In nanoscale CMOS technology, harsh radiations in the environment can now easily cause soft errors, e.g., single-event transients (SETs) and triple node upsets (TNUs), severely affecting the reliability of space applications. In this article, TNUs tolerant and SET-pulses filtered latch (TUTPFL) with low power is proposed, which comprises from four input-stage C-elements (CEs), four inverters, and three output-stage CEs. The CEs’ delay differential enables the TUTPFL latch to effectively filter SET-pulse, while the CEs’ multilevel error-interception property enables the TUTPFL latch to tolerate any possible TNU. The results of HSPICE-based simulations and FPGA-based emulations demonstrate the TNU tolerance and SET filterability of the TUTPFL latch. Meanwhile, compared to the alternative radiation-hardened latches, the TUTPFL latch reduces power dissipation by roughly 20.43% on average.

DOI： 10.1109/TVLSI.2025.3571607

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RHT_NoC: A Reconfigurable Hybrid Topology Architecture for Chiplet-Based Multicore System 査読有り国際誌

Xu D., Zhou W., Huang Z., Liang H. (合肥工業大学), Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 8 ) 2104 - 2117 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Chiplet-based system-on-chip (SoC) architectures, leveraging 2.5-D/3-D integration technologies, provide scalable solutions for a wide range of applications. Achieving high performance and cost-effectiveness in these systems relies heavily on optimizing die-to-die interconnect topologies and designs, which are essential for seamless interchiplet communication. This article introduces a reconfigurable hybrid topology (RHT) architecture designed for chiplet-based multicore systems. RHT achieves high performance and energy efficiency by dynamically reconfiguring the network topology to traffic variations, adaptively selecting transport subnets, and optimizing link bandwidth allocation, thereby minimizing congestion and maximizing packet throughput. Furthermore, RHT leverages global traffic information to dynamically combine Torus loops, maximizing opportunities for rapid packet transmission delivery while guaranteeing minimal hop counts. Moreover, RHT accelerates packet transmission via bufferless combined loops, extending the continuous sleeping periods of routers, improves power gating efficiency, and significantly reduces static power consumption. Simulation results indicate that the Mesh-DyRing achieves over a 40% reduction in network latency and more than a 20% decrease in power consumption overhead compared to the baseline design. When compared to WiNoC, an advanced hybrid wired-wireless topology design, the Mesh-DyRing-PG configuration reduces power consumption by 56.2% while maintaining equivalent average network latency.

DOI： 10.1109/TVLSI.2025.3572112

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SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices 査読有り国際誌

Okamoto H., Wei S., Wang S., Kai H., Takahashi H., Higami Y., Shimizu A., Ni T., Wen X.

Journal of Communications 20 ( 2 ) 214 - 220 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Joint Test Action Group (JTAG) interface is widely used in integrated circuits for functional testing and in-system debugging, ensuring high reliability throughout the silicon life cycle. However, it has also been identified as a potential vulnerability to the cyberattacks. Traditional security countermeasures such as adding authentication mechanism to restrict access to authorized users, often rely on uniform authentication credentials. This approach poses challenges for edge devices with varying computational capacities. Moreover, strengthening authentication security can lead to compatibility issues with embedded hardware on client devices, limiting scalability. To address these challenges, we propose Simple and Secure password authentication protocol, Light processing version based Joint Test Action Group plus Version (SASL-JTAG+), an enhanced JTAG authentication mechanism utilizing the Simple and Secure Password Authentication Protocol, Light Processing Version (SAS-L) protocol that enables one-time password authentication with adjustable bit lengths, tailored to the computational capacities of authenticators and target devices. The new approach provides robust security for devices with performance and cost constraints, offering flexible authentication data within a unified system. As a result, SASL-JTAG+ provides a scalable, long-term solution for securing IoT systems accommodating both legacy and modern devices while adapting to evolving technological demands.

DOI： 10.12720/jcm.20.2.214-220

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Segmentation-Enhanced Overlapped Defect Identification for Multipatterns Wafer Maps 査読有り国際誌

Ni T., Jiang W., Liang H. (合肥工業大学), Wen X., Nie M.

IEEE Transactions on Instrumentation and Measurement 74 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Due to the high complexity of the semiconductor manufacturing process, failures frequently occur. Moreover, there is a rising likelihood of multipattern defects appearing and overlapping on the wafer maps (WMs). Previous studies on defect patterns mainly focus on the classification of wafer defects, and these methods cannot provide effective defect location information for overlapped defect types. To solve this problem, a segmentation-enhanced overlapped defect identification (SEODI) framework is proposed in this article. This framework adeptly extracts and learns features from overlapped wafer defects and detects defects on WMs. Specifically, the wafer defects are categorized into two types—non-overlapped and overlapped and the model is subsequently trained accordingly. The trained model exhibits the capability to detect the non-overlapped defects, identify the overlapped defects, and send them into the U-net network for segmentation. After segmentation, the data is fed back into the detection model for further training. Additionally, we propose a data augmentation method to improve the efficiency of overlapped defect recognition. This method effectively addresses the challenge of detecting the multipattern defects in the semiconductor industry. Experimental findings, utilizing the universal defect dataset MixedWM38, demonstrate that the proposed method achieves an accuracy of 89.3% for overlapped type recognition, coupled with an impressive 89% mean average precision (mAP) for defect localization.

DOI： 10.1109/TIM.2025.3565049

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Test and Diagnosis Strategies for Interchiplet Interconnects 査読有り国際誌

Liu X., Yang D., Zhang L., Ji S., Yan D., Wang Z., Guo Y., Wen X., Cai Z.

IEEE Transactions on Instrumentation and Measurement 74 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

The irregular through-silicon via (TSV) layout complicates the crosstalk's effect, making parallel testing more difficult. For efficient testing and diagnosis of irregular TSV layouts in postbonding, a novel test grouping algorithm based on neural networks is proposed. The influence range of crosstalk faults and the hardware overhead are both considered in the algorithm, maximizing the number of TSVs that can be tested simultaneously, thereby shortening both the test and diagnosis time. Based on the grouping results, an efficient built-in self-test (BIST) architecture with low hardware overhead for testing and diagnosing TSVs is proposed. Die wrapper register (DWR) cells of the IEEE Std 1838 are enhanced and diagnosis is embedded into the test process by improving test patterns and using an on-chip feature compression circuit. This approach supports testing, locating, and identifying stuck-at, bridge, delay, and crosstalk faults. Experimental results show that the test grouping algorithm reduces the average number of groups by 0.371, with more significant reductions observed in large-scale and highly complex settings. The proposed architecture achieves shorter test and diagnosis time to 7G+GN with lower hardware overhead, where G and N are the number of groups and TSVs, respectively.

DOI： 10.1109/TIM.2025.3548248

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Triple-Node-Upset Recovery High-Impedance-State Insensitive and Single-Event-Transient Filtering Latch for Aerospace Applications 査読有り国際誌

Yan A. (合肥工業大学), Lin Z., Xu Y., Bai N., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 4 ) 10847 - 10854 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a 4×4-device-Matrix-based Cost-optimized Triple-node-upset (TNU)-recovery High-impedance-state (HIS)-insensitive and Single-event-transient (SET)-filtering Latch, namely MCTHSL, designed for aerospace applications. The MCTHSL latch comprises a 4×4-device matrix to completely provide TNU recovery and thus it is HIS-insensitive. The input of a Schmitt Trigger (ST) is split to create an input-split ST, namely ISST, to simultaneously provide the functions of a C-element (CE), a SET-filtering device and a delay element. The matrix comprises 15 mutually interlocking 2-input CEs as well as an ISST to store values, recover from TNUs and filter SETs with HIS-insensitivity and cost-optimization. Simulation results demonstrate the above-mentioned features as well as moderate sensitivity to the impacts of process, voltage and temperature (PVT) variations of our proposed MCTHSL latch in comparison with existing latches with TNU-recovery. The features are achieved at the cost of moderate overhead in terms of area, delay, and power.

DOI： 10.1109/TAES.2025.3546581

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Reconfigurable Radiation-Hardened SRAM Cell Design for Different Radiation Environments 査読有り国際誌

Bai N., Wang F., Xu Y., Wang S., Wen X.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 44 ( 9 ) 3581 - 3591 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a novel and effective 14T (14-transistors) reconfigurable radiation-hardened static-random access-memory (SRAM) cell design under the SMIC 65nm process, featuring a unique memory reconfigurability architecture with two operation modes, namely the high reliability (HR) mode and the triple-time memory (TTM) mode for meeting different radiation environmental requirements. The proposed HR mode provides strong protection of the memory arrays in harsh radiation environments. Compared with the traditional triple modular redundancy (TMR) structure, the proposed HR mode reduces area overhead by 30%, delay by 37%, and power consumption by 16%. The TTM mode uses the EN (enable) circuit to expand the capacity threefold in less harsh radiation environments, avoiding the area wastage caused by the traditional TMR structure. By implementing the two innovative operation modes, the proposed design overcomes the limitations of the traditional TMR structure, reducing area overhead while retaining the radiation hardening capability. In addition, this paper presents a mode-switching mechanism composed of a detection circuit and an EN circuit. The detection circuit can detect errors in the reconfigurable architecture. With the proposed mode-switching mechanism, two operation modes can switch in response to different radiation environments. Besides, to ensure the normal operations of the TTM mode in radiation environments, the proposed 14T cell serves as a bitcell in the memory reconfigurable architecture. Compared with typical existing designs, such as radiation-hardened based design (RHBD), writability enhanced (WE-Quatro), and dual interlocked storage cell (DICE) cells, the proposed 14T cell design has better delay, critical charge, and HSNM.

DOI： 10.1109/TCAD.2025.3541010

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NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead 査読有り国際誌

Yan A. (合肥工業大学), Jiang W., Bao H., Huang Z., Ni T., Wen X., Girard P.

Proceedings Design Automation and Test in Europe Date 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a FeFET-based non-volatile and single-event upset (SEU) recoverable latch, namely NVSRLO, which does not require any extra control signals. Simulation results show that the proposed latch provides non-volatility and SEU-recovery with optimized overhead. Compared with existing non-volatile latches, NVSRLO significantly reduces delay, power, and delay-power-area product at the cost of area.

DOI： 10.23919/DATE64628.2025.10993239

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A Low Cost Triple-Node-Upset Self-Recoverable Latch Design for Nanoscale CMOS 査読有り国際誌

Bai N., Zhang P., Xu Y., Guo Y., Li H., Wang Y., Wen X.

IEEE Transactions on Device and Materials Reliability 25 ( 2 ) 296 - 307 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Due to the constant reduction of semiconductor feature sizes, the charge sharing effect is getting worse. The occurrence probability of triple-node upset (TNU), which has a significant impact on the circuit’s reliability, is rising in nanoscale digital circuits. This paper proposes a low overhead and TNU self-recovery latch (TNU-SR) based on the 28 nm CMOS technology to efficiently tolerate TNU and reduce the power dissipation and latency of the latch. The latch design proposed in this article adopts stacked transistors to reduce sensitive nodes and area overhead. The TNU-SR latch uses clock gating and high-speed transfer path technology, resulting in low power dissipation and low delay. For simulation results, compared with existing latches, it can be known that the TNU-SR latch performs well in terms of delay, power consumption, and area, so it is a good choice for radiation-hardened design for space applications. In addition, compared with the latest TNU self-recovery latch (HLTNURL), the TNU-SR latch proposed in this paper reduces the Power-Area-Delay Product (PADP) metric by 111.13%.

DOI： 10.1109/TDMR.2025.3561519

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A Low-Cost QuadrupleNode-Upset Tolerant Latch Design and Recovery Rate Optimization Algorithm 査読有り国際誌

Huang Z., Jiang X., Zhang Y., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 5 ) 13858 - 13870 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the continuous shrinking of nanoscale CMOS technology, the critical charge of circuit nodes has significantly decreased, rendering the nodes highly susceptible to soft errors. In this paper, a high-performance single-node-upset recovery memory cell (HSRM) is proposed. Based on four HSAMs, a latch namely QUAD-HSRM is introduced, which can completely tolerate quadruple-nodeupset (QNU). Additionally, a circuit matrix-based verification algorithm is proposed, which is not limited to C-element, and can automatically detect the multi-node-upset recovery rate and blocking rate of latches. Based on this algorithm, an optimization algorithm for automatically improving the recovery rate of latches was proposed, and using this algorithm, the QUAD-HSRM was optimized to obtain the QUAD-HSRM-PRO. Compared to the QUAD-HSRM, the QNU recovery rate of the QUAD-HSRM-PRO has increased from 54.94% to 95.76%. Compared to other QNU hardened latches (LC-QNUTL, QRHIL, LDAVPM, MURLAV), the QUAD-HSRM-PRO shows an average power reduction of 45.02%, an average PDP reduction of 33.07%, an average setup time reduction of 8.00%, an average Q<inf>cirt</inf> increase of 80.56%.

DOI： 10.1109/TAES.2025.3581546

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A Response-Nonlinearized DEMUX-TDC PUF for Resistance Against Modeling Attacks and Secure Authentication Protocols 査読有り国際誌

Ni T., Wu H., Nie M., Yan A. (合肥工業大学), Wang S., Wen X., Bian J.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 10 ) 2606 - 2619 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As a critical hardware security primitive for the authentication within the Internet of Things (IoT), the physical unclonable function (PUF) represents an innovative security design paradigm for integrated circuits. However, the linear challenge-response mapping of the arbiter PUF (APUF) and variants render these structures more susceptible to modeling attacks due to their delayed linear structure. In this article, we propose a nonlinearized demultiplexer time-to-digital converter (DEMUX-TDC) PUF. This PUF uses a quantized delay difference technique to alter the traditional response generation mechanism, demonstrating robust resistance against modeling attacks. First, the proposed PUF employs a segmented APUF variant structure configured in both front and back segmented modes to generate a source of delay difference entropy. Additionally, the scheme incorporates a multilayer differential tapped TDC circuit to quantize the delay differences into digital codes, followed by a linear feedback shift register (LFSR) to obfuscate the final output response. We further propose a highly secure mutual authentication protocol based on reconfigurable PUF, by leveraging the characteristics of front and back segments of the PUF’s challenge. Evaluation of the proposed scheme on the implementation of Xilinx Virtex-7 and Spartan-6 field-programmable gate array (FPGA) demonstrates that the uniqueness and uniformity can reach ideal value, in the condition of prediction accuracy across six modeling attacks remaining around 50%.

DOI： 10.1109/TVLSI.2025.3575056

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BF PUF: A Modeling Attack-Resistant Strong PUF Based on Bent Functions 査読有り国際誌

Huang Z. (合肥工業大学), Zeng F., Chi Y., Lin Y., Lu Y., Liang H., Bian J., Ouyang Y., Ni T., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 8 ) 2299 - 2311 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Strong physical unclonable functions (PUFs) are promising circuits for lightweight Internet of Things (IoT) authentication and security. However, existing strong PUFs exhibit very low cryptographic nonlinearity (NL), making them vulnerable to machine learning (ML) modeling and cryptanalytic attack. To address this issue, we propose the Bent function PUF (BF PUF) based on Maiorana-McFarland (M-M) constructed Bent functions, which obfuscates the responses of the strong PUF to enhance resistance against modeling attacks. The core idea is to employ the M-M construction method for Bent functions to ensure maximum cryptographic NL to resist modeling attacks. A Feistel network is configured using weak PUF responses as keys to achieve device-specific and unpredictable mappings of input challenges while meeting the requirements of the M-M Bent function construction. A Python-based model of the BF PUF was developed, and simulation results indicate that the cryptographic NL of the proposed BF PUF outperforms k-XOR arbiter PUFs (APUFs) (k =2 , 4, 6). The proposed BF PUF was also implemented and evaluated on the FPGA hardware platform. The experimental results show that under modeling attacks using four ML algorithms—logistic regression (LR), artificial neural networks (ANNs), deep neural networks (DNNs), and covariance matrix adaptation evolution strategies (CMA-ES)—the best prediction accuracy under these four modeling attack algorithms is 52.60%. The reliability under temperature fluctuations ranging from - 10°C to 80°C is between 84.20% and 99.78%.

DOI： 10.1109/TVLSI.2025.3569587

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Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications 査読有り国際誌

Yan A. (合肥工業大学), Zhou C., Ni T., Zhang J., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 3 ) 6202 - 6216 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the aggressive shrinking of transistor feature sizes, nanoscale complementary metal oxide semiconductor (CMOS) circuits are becoming more vulnerable to multinode upsets, e.g., triple-node upsets as well as quadruple-node upsets (QNUs), caused by the effects of harsh radiation. This article first presents a QNU completely tolerant latch based on the so-called triple-path dual-interlocked cell (TPDICE) and the soft-error-interception module, namely quadruple-node-upset hardened latch (QNUHL). We further propose an advanced latch, namely quadruple-node-upset recovery hardened latch (QNURHL), which mainly employs 24 interlocked C-elements, to provide complete QNU recovery. Simulations based on the HSPICE tool demonstrate the complete QNU tolerance as well as the reasonable overhead for the QNUHL latch and also show that the QNURHL latch is recoverable from any possible QNU and can roughly save silicon area by 11% and power dissipation by 16%, compared with the QNU hardened latch of the same type. Moreover, an algorithm-based method for the verification of error tolerance and recovery of latches is proposed. The proposed method can simplify the verifications to demonstrate the capability of node-upset tolerance and/or recovery for latches.

DOI： 10.1109/TAES.2024.3525448

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Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement 査読有り国際誌

Yan A., Hu C., Li J., Bai N., Huang Z., Ni T., Patrick G., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 6 ) 1765 - 1773 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the continuous advancement of CMOS technologies, soft errors, such as single-node upset (SNU) and double-node upset (DNU), caused by radiation in nanoscale integrated circuits, are becoming increasingly prominent. Meanwhile, transistor aging mitigation is indispensable for long-term robustness enhancement. First, to reduce the impact of radiation on circuits, we propose a novel DNU-recovery latch with low cost, namely, DURLC, only consisting of four dual-input C-elements (CEs) and four clock-gated input-split inverters for the storage of values. Second, we propose a DNU-recovery latch with moderate cost, namely, DURMC, based on seven CEs and four inverters, for convenience to optimize the latch to alleviate aging. The proposed DNU-recovery latch with mitigated aging is called DURMA. The latch employs a high-speed path to reduce delay without sacrificing performance when mitigating aging issues. Finally, we propose an algorithm-based verification method to validate the DNU recovery of the proposed latches. The simulation results show that, compared with the state-of-the-art robust latches, the proposed latches have the advantages of DNU recovery with moderate and even low cost, and meanwhile, aging is effectively mitigated for the DURMA latch.

DOI： 10.1109/TVLSI.2025.3554117

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Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS 査読有り国際誌

Yan A. (合肥工業大学), Xu Y., Zhang Y., Bai N., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 7 ) 2079 - 2083 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Spintronic devices, such as magnetic tunnel junctions (MTJs), are promising for space applications due to their radiation hardness and nonvolatility. However, as semiconductor technology advances, CMOS peripheral circuits are becoming vulnerable to double node upset (DNU) as well as triple node upset (TNU). This brief proposes two nonvolatile and robust latch designs primarily composed of MTJs and C-elements (CEs). Both designs offer nonvolatility and self-recovery from multiple-node upsets. Simulation results demonstrate that the proposed latches provide nonvolatility and complete protection against multiple-node upsets with balanced overhead.

DOI： 10.1109/TVLSI.2025.3562769

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Efficient Modulated State Space Model for Mixed-Type Wafer Defect Pattern Recognition 査読有り国際誌

Nie M., Zhu S., Yan A., Zhuo C., Wen X., Ni T.

Proceedings Design Automation and Test in Europe Date 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Accurate and efficient wafer defect detection is crucial in semiconductor manufacturing to maintain product quality and optimize yield. Traditional methods struggle with the complexity and diversity of modern wafer defect patterns. While deep learning approaches are effective, they are often resource-intensive, posing challenges for real-time deployment in industrial settings. To solve these problems, we propose an Efficient Modulated State Space Model (EM-SSM) for mixed-type wafer defect recognition, optimized with knowledge distillation to balance accuracy and efficiency. Our framework captures size-dependent relationships and improves defect-specific feature representation to recognize complex defects precisely. Specifically, we introduce an efficient directional modulation mechanism to refine spatial recognition of defect patterns. To further improve inference efficiency, we propose a deep-to-shallow distillation method that transfers knowledge from deeper networks to lighter networks, reducing inference time without compromising classification accuracy. Experimental results on the MixedWM38 wafer dataset with 38 defect types show that our model achieves 99.0% accuracy, outperforming traditional methods in both accuracy and efficiency. Our model offers a scalable solution for modern semiconductor defect detection.

DOI： 10.23919/DATE64628.2025.10992855

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Graph-Based Multitask Transfer Learning for Fault Detection and Diagnosis of Few-Shot Analog Circuits 査読有り国際誌

Gao Z., Yan A. (合肥工業大学), Huang Z., Cui J., Roh B.H., Liu G., Girard P., Wen X.

IEEE Internet of Things Journal 12 ( 12 ) 21264 - 21279 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Building an interpretable fault detection and diagnostic model based on few-shot circuit samples and prior information about circuit structures is of significant importance. To fill these gaps, we propose a graph-based multitask transfer learning (TL) method for fault detection and diagnosis of circuits under few-shot conditions. First, in order to model the interconnections of nodes in a circuit, the sample data is organized into a graph structure, and a semi-supervised graph-based structural feature fusion method is proposed. The proposed method can accept graph-structured data and process the data using feature fusion methods. Second, to improve the model performance under few-shot conditions, two TL mechanisms are proposed for the topological structure characteristics of analog circuits as well as circuit signal characteristics. Finally, through a parameter-shared strategy, we propose a task transfer-based fault diagnosis approach. Experimental results on three different circuits show that the proposed method has the best diagnostic accuracy compared to typical detection and diagnosis schemes.

DOI： 10.1109/JIOT.2025.3547957

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HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications 査読有り国際誌

Guo X., Zhang J., Meng X., Li Z., Wen X., Girard P., Liang B., Yan A. (合肥工業大学)

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 44 ( 6 ) 2367 - 2377 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the rapid advancement of semiconductor technologies, latches become increasingly sensitive to soft errors, especially triple node upsets (TNUs), in harsh radiation environments. In this article, we first propose a high-performance and area-efficient latch, namely, HALTRAV, featuring complete TNU-recovery. The storage portion of HALTRAV consists of 28 interlocked source-drain cross-coupled inverters (SCIs) for complete TNU-recovery with area efficiency and low delay. To mitigate the issue that node-upset-recovery verifications for existing latches highly relies on electronic design automation tools, we further propose an algorithm-based verification method that can automatically verify the node-upset-recovery of latches, which greatly simplifies the reliability-verification flow. Simulation results demonstrate the TNU-recovery of HALTRAV and also show that HALTRAV achieves 40.38%, 8.17%, and 31.89% reduction in delay, area, and delay-power–area product (DPAP) on average, respectively; however; it is at the cost of power as compared to typical latches that are TNU-recoverable. Comparison results also demonstrate the moderate sensitivity of HALTRAV to the impacts of the process, voltage, and temperature (PVT) variations.

DOI： 10.1109/TCAD.2024.3511335

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Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design 査読有り国際誌

Ma R., Holst S., Xu H., Wen X., Wang S., Li J., Yan A. (合肥工業大学)

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 2 ) 449 - 461 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Soft errors have been a severe threat to the reliability of modern integrated circuits (ICs), making hardened latch designs indispensable for masking soft errors with redundancy. However, the added redundancy also masks production defects as soft errors; this makes it hard to detect defects in hardened latches, thus significantly reducing their reliability. Our previous work proposed the scan-test-aware hardened latch (STAHL) design, the first for addressing the issue of low defect detectability of hardened latch designs. However, STAHL still suffers from two problems: 1) it is not self-resilient to soft errors and 2) a STAHL-based scan design requires one additional control signal. This article proposes a high defect detectable and single-event-upset (SEU)-resilient robust (HIDER) latch to address the issues of the low defect detectability of existing hardened latches and the STAHLs lack of SEU-resilient capability. Two scan designs [HIDER-based scan-cell-S (HIDER-SC-S) and HIDER-based scan-cell-F (HIDER-SC-F)], as well as two corresponding test procedures, are proposed to fully test HIDER latch with only one control signal. Simulation results show that the HIDER latch achieves the highest defect coverage (DC) in both single latch cell detection and scan tests among all existing hardened latch designs. In addition, the HIDER latch has much lower power and a smaller delay than STAHL.

DOI： 10.1109/TVLSI.2024.3467089

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Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Based on Cross-Interlocking 査読有り国際誌

Huang Z. (合肥工業大学), Ai L., Jiang X., Wang X., Lu Y., Pan J., Song T., Wen X., Yan A.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 44 ( 4 ) 1595 - 1608 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the CMOS technology continues to shrink, latches are becoming increasingly susceptible to multiple-node-upset caused by charge sharing in radiation environments. In this article, a low-cost quadruple-node-upset (QNU) self-recoverable latch based on cross-interlocking (Quad-CIRC) is proposed. By utilizing four cross-interlocking self-recoverable cells (CIRCs) for interlocking, complete QNU self-recovery is achieved with reduced sensitive nodes. Meanwhile, the majority of currently available QNU self-recoverable latches are primarily composed of C-elements-based redundancy, resulting in a significant increase in area overhead. However, Quad-CIRC effectively reduces area overhead while ensuring hardened capability through cross-interlocking of CIRCs. HSPICE-based simulations in 22 nm CMOS technology demonstrate that Quad-CIRC achieves a reduction of 69.08% on average of power consumption, an increase of 16.83% on average of delay, a reduction of 63.51% on average of power-delay-product (PDP), a reduction of 51.01% on average of area, a reduction of 83.44% on average of area-PDP (APDP), and an increase of 60.49% on average of critical charge, compared to five other QNU self-recoverable latches (QRHIL, MURLAV, LDAVPM, QR-R11-C2 , and low-delay QNU self-recoverable).

DOI： 10.1109/TCAD.2024.3471913

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TNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications 査読有り国際誌

Yan A., Pei Z., Guo X., Song J., Jiang C., Liang H., Wen X., Girard P.

Proceedings IEEE International Symposium on Circuits and Systems 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As semiconductor technology advances, radiative-particle-induced soft errors and power consumption are becoming major concerns for digital circuits in aerospace applications. Radiation hardening by design and magnetic tunnel junctions (MTJs) are widely employed to address these concerns. In this paper, a novel latch, called TNURML, that can completely recover from triple-node upsets (TNUs), is proposed. The embedded MTJs provide non-volatility and are compatible with traditional CMOS processes. The TNURML employs a TNU-recovery module as well as a pair of MTJs for backup and recovery operations. Extensive simulations demonstrate the excellent TNU-recovery capability and non-volatility of the TNURML latch at the cost of slightly increased area overhead. The proposed TNURML latch reduces 43.63% of delay and 48.23% of power on average when compared to the state-of-the-art latches.

DOI： 10.1109/ISCAS56072.2025.11043354

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QNUCPN: A Low-Power Single-Event Quadruple-Node-Upset Recovery Latch 査読有り国際誌

Huang Z., Qiu L., Yang S., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 45 ( 2 ) 855 - 866 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Integrated circuits are increasingly sensitive to radiation-induced multi-node upset in advanced CMOS technology. This paper proposes a novel low-power quadruple-node-upset recovery latch (QNU-CPN), which is based on the feedback interconnection of twenty-two input-split C-elements with P-input and N-input (CPNs) to achieve high reliability. Post-layout simulation results for 45nm CMOS by HSPICE technology show that the proposed QNU-CPN latch exhibits a reduction in power consumption by an average of 56.45%, a reduction in power-delay product (PDP) by an average of 56.92%, a reduction in area-power-delay product (APDP) by an average of 58.59%, and a reduction in setup time by an average of 11.11%, in comparison to four other existing quadruple-node upset recovery latch (LDAVPM, QRHIL, QRHIL-LC, MURLAV). Furthermore, this paper proposes the recovery rate calculation algorithm method that can calculate the recovery rate based on the configuration of multiple fault-tolerant components.

DOI： 10.1109/TCAD.2025.3590658

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A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments 査読有り国際誌

Bai N., Xia Y., Xu Y., Wang Y., Wang S., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 9 ) 2580 - 2591 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the advancement of semiconductor technology, circuits have become increasingly susceptible to errors induced by radiation. Traditional approaches to enhancing the resilience of circuits against single-node upsets (SNUs) are insufficient to meet the robustness standards of modern designs. This article proposes a high-performance, low-power latch, named high-performance low-power double-node upset resilient latch (HLDRL), which is designed to exhibit exceptional resilience against double-node upsets (DNUs). Its design has six intricately interconnected C-elements (CEs) and two three-input CEs, for error interception, ensuring robust performance even in the case of DNUs. The Technology Computer Aided Design (TCAD) tool is used to validate the effectiveness of the HLDRL. Besides, comprehensive simulations are conducted utilizing the advanced SMIC 55-nm process technology. These simulation results show that our proposed HLDRL latch can autonomously recover from any DNU and thereby ensure the integrity of the system. Moreover, compared with existing DNU-resilient latches, the proposed HLDRL latch exhibits substantial improvements in terms of multiple metrics. On average, the proposed latch achieves an impressive 29.39% dynamic power saving, a remarkable 40.04% increase in speed, a notable 4.81% reduction in area, and a substantial 53.96% decrease in the power-delay–area product (PDAP). In the post-layout simulation, the proposed latch achieves a 30.39% dynamic power saving, a 36.47% increase in speed, and an impressive 52.38% decrease in PDAP. Furthermore, the proposed latch demonstrates enhanced resilience against variations in process, supply voltage, and temperature (PVT).

DOI： 10.1109/TVLSI.2025.3585169

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Non-Volatile, Double and Triple Node Upsets Tolerant Latch Designs Based on FeFET and CMOS 査読有り国際誌

Yan A., Kang B., Jiang W., Ni T., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 6 ) 16981 - 16992 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Non-volatile memories (NVMs) are widely used in energy-harvesting Internet of Things (IoTs) systems, and ferroelectric field effect transistor (FeFET) devices present opportunities for NVM designs due to such important features as low power consumption, fast access speed and compatibility with the CMOS technology. However, rising soft error rates caused by radiation pose a severe reliability challenge, and state-of-the-art radiation hardening by design (RHBD) methods are urgently needed. This paper presents a non-volatile double-node-upset (DNU) tolerant latch (NVDTL) and its enhanced version, i.e., a non-volatile triple-node-upset (TNU) tolerant latch (NVTTL), which do not require auxiliary control signals to provide the non-volatility feature. The NVDTL utilizes two parallel single-node-upset (SNU) recovery units. Each unit integrates multiple 2-input C-elements and input-split inverters with embedded FeFETs to form interlocked feedback loops. Moreover, NVTTL enhances its robustness reliability through a two-stage error-blocking mechanism in the output module to provide TNU tolerance. Simulation results based on Cadence Virtuoso have validated the proposed latches' fault-tolerance and non-volatility and also show that the comprehensive delay-power-area product is reduced by approximately 77.21% for NVDTL and 61.67% for NVTTL, and the power-delay product is reduced by 23.45% and 11.15%, respectively, compared to the existing latches with the same level of radiation hardness.

DOI： 10.1109/TAES.2025.3599136

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Reconfigurable Fault-Tolerant Link With Bandwidth Expansion for 2.5-D Chiplet-Based Systems 査読有り国際誌

Zhou W., Xu D., Xu S., Luo L., Chen F., Ni T., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 11 ) 3043 - 3056 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

The 2.5-D chiplet-based systems offer a promising path toward higher performance and integration density, but the reliability of interchiplet links, particularly vertical links (VLs), poses a significant challenge. This article proposes reconfigurable bidirectional link (ReBL), a novel architecture providing robust fault tolerance and enhanced bandwidth for these critical interconnects. ReBL features three key innovations: 1) a robust fault-tolerant mechanism leveraging ReBLs that dynamically adapts to and mitigates permanent link failures; 2) a dynamic bandwidth expansion technique that significantly enhances the system efficiency by utilizing idle links to optimize resource allocation and throughput; and 3) a virtual channel (VC) allocation strategy that guarantees deadlock-free operations through strategic channel partitioning and assignment. Evaluations using synthetic traffic and PARSEC benchmarks demonstrate ReBL’s significant advantages under high fault rates. Compared with the state-of-the-art reliable and deadlock-free routing (ReD) approach, ReBL achieves an average reduction of 21.3% in packet latency and 4.9% in application execution time across the evaluated benchmarks. These benefits are achieved with only a 6.06% area overhead over baseline.

DOI： 10.1109/TVLSI.2025.3592915

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A Low-Cost Input-split Inverter-based Triple-Node-Upset Recoverable Latch Design 査読有り国際誌

Bai N., Xu P., Xu Y., Yan A., Wen X., Wang S., Xia Y.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 45 ( 4 ) 1963 - 1974 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the integration level of integrated circuits continues to increase and the feature size of nanoscale chips continues to shrink, the possibility of triple-node-upsets (TNUs) occurring in circuits increases significantly. This paper proposes a latch, namely CLTNUSL, which offers stable resilience against TNUs in radiative environments while achieving a good balance between reliability and overhead. Unlike the conventional latches consisting of multi-input C-elements, the proposed CLTNUSL latch mainly consists of 16 interlocked dual-input inverters. Due to the small number of transistors, CLTNUSL achieves low area overhead. Due to the use of high-speed paths and clock gating techniques, CLTNUSL achieves low latency and low power consumption. Simulation results demonstrate CLTNUSL's full recovery from TNU in all scenarios. Compared with the conventional TNU-hardened latch, CLTNUSL achieves minimal latency, power consumption, area overhead, and the delay-power-area product (DPAP). CLTNUSL reduces delay by 13.22%, power by 52.74%, area by 40.90%, and DPAP by 71.44% on average, compared with state-of-the-art latches. Process-Voltage-Temperature (PVT) and Monte Carlo simulation results show that the CLTNUSL latch is less sensitive to temperature, voltage and process variations compared with conventional TNU self-recovery latches.

DOI： 10.1109/TCAD.2025.3605516

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An Accelerated Newton-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization 査読有り国際誌

Zhou C., Cao Y., Yang F., Wen X., Shi Q., Rong R., Yang A.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 45 ( 3 ) 1535 - 1548 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

The advancement of technology nodes has intensified the focus on mixed-cell-height circuit design, posing challenges to traditional legalization techniques. In this paper, we propose a novel and efficient accelerated Newton-based matrix splitting (ANMS) iteration method to address the mixed-cell-height circuit legalization problem. Our approach reformulates this problem into a generalized absolute value equation and leverages matrix splitting and the latest estimate vector to enhance computational efficiency. We also introduce a relaxation variant within the ANMS framework, namely, the accelerated Newton-based successive overrelaxation (ANSOR) method, which is particularly effective in scenarios requiring high computational performance and precise parameter tuning. The proposed method achieves linear computational complexity. Furthermore, we perform an in-depth analysis of the sufficient convergence conditions for the ANMS method and optimize cells that have excessive displacement. Experimental results show that the proposed ANMS method achieves a speedup of 1.09× - 4.94× compared to state-of-the-art methods, while maintaining the quality of solution. This makes it highly suitable for addressing complex placement design challenges.

DOI： 10.1109/TCAD.2025.3593205

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NVLIM: MTJ and CMOS-Based Nonvolatile Latch Design With Protection Against Triple-Node-Upsets for Robust Computing 査読有り国際誌

Yan A., Zhang Y., Wang L., Huang Z., Zhang Q., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 34 ( 1 ) 268 - 279 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Soft errors and power dissipation emerge as critical challenges in developing high-reliability and cost-sensitive embedded systems. To address these issues, the magnetic tunnel junction (MTJ) is considered a promising solution due to its nonvolatility and its compatibility with traditional CMOS manufacturing processes. In this work, we propose a novel nonvolatile (NV) latch consisting of inverters and MTJs, namely, NVLIM, which provides nonvolatility and robust partial tolerance against triple-node-upsets (TNUs) at low cost. NVLIM integrates a TNU-tolerant block based on CMOS with a backup-restore block using MTJs. Simulation results incorporating process, voltage, and temperature (PVT) variations, bias temperature instability (BTI) impact, and Monte Carlo simulations demonstrate the balanced performance in terms of nonvolatility, robust partial TNU tolerance, and comprehensive overhead of the proposed latch.

DOI： 10.1109/TVLSI.2025.3614568

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QtNURAV: A Robust Latch Design with Quintuple Node Upset Recovery and Algorithm based Verifications for Aerospace Applications 査読有り国際誌

Yan A., Li J., Bao H., Ni T., Huang Z., Liang B., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 6 ) 18543 - 18554 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the continuous scaling of transistor feature sizes to the deep nano-scale, modern circuits have become increasingly sensitive to radiation-induced soft errors, such as multiple node upset (MNU). Especially, due to charge-sharing, the striking of one high-energy radiative particle can simultaneously impact multiple adjacent nodes of a highly integrated circuit causing MNU, e.g., quintuple node upset (QtNU) and even more node upsets. Existing MNU-hardened latch designs cannot provide QtNU recovery, and their robustness verification heavily depends on electronic-design-automation tools. In this paper, we present a robust latch, namely QtNURAV, to protect against QtNU for aerospace applications, along with an algorithm-based QtNU recovery verification method. The latch mainly employs four parallel dual-interlocked cells (DICEs) that feed each other through eight 3-input inverters to robustly retain values. The proposed algorithm simplifies the fault-tolerance verification process, demonstrating the QtNU recovery of QtNURAV. Simulation results based on HSPICE show that the QtNURAV latch can self-recover from any possible QtNU and has low delay and power consumption. Compared to existing Quadruple Node Upset hardened latches, the proposed QtNURAV latch provides QtNU recovery and effectively reduces delay, power and delay-power-area comprehensive product by 33.3%, 30.1%, and 53.3% on average, respectively.

DOI： 10.1109/TAES.2025.3612904

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A Parallel Feedback Obfuscation Strong PUF against Machine-Learning Modeling Attacks and Lightweight Authentication Protocol 査読有り国際誌

Huang Z., Lin Y., Wang Z., Lu Y., Liang H., Bian J., Ouyang Y., Ni T., Wen X.

IEEE Transactions on Dependable and Secure Computing 23 ( 2 ) 3051 - 3067 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Arbiter physical unclonable function (APUF) is a hardware security primitive that generates security keys by utilizing unavoidable process variations during chip manufacturing. However, the structure based on linear additive function makes it vulnerable to machine learning (ML) attacks. This paper proposes a parallel feedback obfuscation PUF (PFO PUF) design, which uses intermediate arbitration signals of the lower-layer APUF to generate the hidden challenge of the upper-layer APUF, enhancing the overall nonlinearity of the structure. The obfuscation module makes weight judgment for intermediate arbitration signals of upper-layer and lower-layer APUFs, which obfuscates the real response of PUF. We further design a variant of PFO PUF called reconfigured challenge obfuscation PFO PUF (RPFO PUF) and propose its lightweight device authentication protocol. RPFO PUF enhances the resistance of the original PFO PUF against reverse engineering (RE) and improves its Strict Avalanche Criterion (SAC) characteristic by reordering the challenges and incorporating weak PUF responses. The proposed PFO PUF and RPFO PUF were comprehensively evaluated via Python-based simulations and FPGA measurements. In Python simulations, both designs show strong resistance to state-of-the-art ML attacks, with logistic regression (LR), support vector machine (SVM), and covariance matrix adaptation evolution strategies (CMA-ES) yielding near 50% prediction accuracies under various PUF configurations. Although deep neural network (DNN) achieves up to 69.52% prediction accuracy on the PFO PUF, it drops to ∼50% on the RPFO PUF. FPGA results further confirm this, with the (32, 11)-RPFO PUF achieving a maximum prediction accuracy of only 51.47% across all four ML attacks. Moreover, both designs incur low hardware overheads, requiring just 743 and 2145 gate equivalents (GEs), respectively.

DOI： 10.1109/TDSC.2025.3632835

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Radiation-Hardened SRAM Designs for Self-Recovery From All Single-and Double-Node Upsets 査読有り国際誌

Yan A., Li J., Li K., Wang W., Huang Z., Ni T., Wang Q., Girard P., Wen X.

IEEE Transactions on Device and Materials Reliability 26 ( 1 ) 167 - 177 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the progress of semiconductor technology, transistor dimensions are continuously shrinking, and thus the sensitivity of static random-access memories (SRAMs) to radiation induced soft errors is increasingly severe. Single-node upsets (SNUs) as well as double-node upsets (DNUs) caused by high-energy radiative particles are typical soft errors. In order to solve this problem, this paper presents two radiation-hardened robust SRAM cells, i.e., RH33T and RH29T, based on multi-input inverters. They primarily use nine multi-input inverters to form the cross-coupled feedback mechanism for enabling the cells to recover quickly when impacted by SNUs or DNUs. HSPICE-based simulation results confirm that the RH29T and RH33T cells can fully tolerate SNUs and DNUs with good reliability and have moderate read/write access speeds and power overhead. In addition, Virtuoso-based simulation results show that the RH29T and RH33T have a moderate tolerance for static noise margin (SNM).

DOI： 10.1109/TDMR.2025.3641827

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LLM-Design Platform for Thermal-Failure-Aware 3D Chiplet Layout via Iterative Parameter Analysis 査読有り国際誌

Song T., Wang S., Wen X.

Proceedings 2025 IEEE 34th Asian Test Symposium Ats 2025 55 - 60 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Although advanced 3D chiplet packaging helps extend Moore's-Law gains through vertical stacking of heterogeneous dies, it simultaneously introduces unprecedented thermal challenges. Shrinking 3D interconnects and rising current densities trap heat at through-silicon vias (TSVs) and micro-bumps, causing steep temperature gradients and thermo-mechanical stress that directly trigger early failures. Existing methods interact with finite-element analysis (FEA) tools mainly through manual, experience-based parameter tuning, inevitably making hot-spot detection time-consuming and error-prone. This paper establishes a text-interactive, thermal-failure-aware design framework for 3D chiplets that couples large language model (LLM)-accelerated thermal analysis with FEA simulation. A Python-driven Automatic Code Generation Model (ACGM) is invoked to automate geometry drawing, meshing, and boundary-condition assignment, enabling rapid analysis and prediction of hot-spot locations within densely stacked chiplets and TSVs. The proposed ACGM eliminates domain-expert dependence by abstracting cumbersome FEA parameter setting into natural-language commands, thereby lowering the entry barrier and cutting operation time. Deployment of the proposed ACGM streamlines intricate FEA operations and Python scripting into concise natural-language commands, enabling accurate layout-parameter tuning and shortened design cy-cles-establishing an AI-centric design-verification paradigm for advanced 3D chiplets.

DOI： 10.1109/ATS66998.2025.00018

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Radiation-Resistant ZnO Thin-Film Transistor Voltage Reference 査読有り国際誌

Bai N., Ge G., Li H., Wu Y., Yan A., Wen X.

Proceedings 2025 IEEE 34th Asian Test Symposium Ats 2025 103 - 108 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a radiation-tolerant voltage reference circuit based on atomic layer-deposited zinc oxide thinfilm transistors (ZnO TFTs), where both active and floating gate layers utilize ZnO films. Employing a dual-exponential current source method, we accurately simulate single-event transient currents induced by high-energy particles. Measurement results demonstrate that the proposed circuit achieves 5 μs recovery time without radiation hardening, reducible to 1μs with hardening techniques. The circuit generates a 3.1 V reference voltage operating from 6 V to 10 V supply, with 18.78 mV/V line sensitivity and 0.72 μW static power consumption. Temperature stability is achieved through a complementary temperature coefficient. From 0°C to 80°C, the temperature coefficient of VREF is 79.56 ppm/°C, and the PSRR reaches -36.5 dB.

DOI： 10.1109/ATS66998.2025.00026

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Software-Defined Secure Island for Testing Chiplet Systems 査読有り国際誌

Okamoto H., Wang S., Kai H., Yotsuyanagi H., Higami Y., Ni T., Song T., Takahashi H., Wen X.

Proceedings 2025 IEEE 34th Asian Test Symposium Ats 2025 61 - 66 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Chiplet systems that stack heterogeneous dies via 2.5D/3D integration use JTAG-based test access ports (TAPs) to validate inter-die links and enable in-field diagnosis. However, these TAPs create a shared attack surface: penetrating a single die can potentially expose control of the entire stack. Current countermeasures involve embedding a complete cryptographic engine in each chiplet, which increases the area and locks the protocol at tape-out, leaving it susceptible to future unknown attacks. This paper proposes a Software-Defined Secure Island (SDSI) architecture that decouples security policies from hardwired logic while satisfying non-functional requirements. Each chiplet instantiates an ultra-lightweight Secure Island Controller (SIC) macro that performs only two XORs and two additions per handshake. Meanwhile, a centralized secure island runs heavyweight cryptography in firmware using the multi-round SASL-JTAG+ protocol. SDSI enables scalable, adaptable test access protection by decoupling security from hardware. An FPGA implementation shows that the SIC macro occupies 11% of the area of an AES- 128 core and 37% of a SHA256 core, yet it supports 256 - to 512-bit keys with negligible growth. A security analysis demonstrates immunity to replay attacks because the authentication data is refreshed with each session. All future upgrades, such as longer keys, stronger hashes, and additional rounds, are delivered via firmware, providing scalable, field-upgradable protection for heterogeneous chiplet systems.

DOI： 10.1109/ATS66998.2025.00019

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A Robust Newton Iteration Method for Mixed-Cell-Height Circuit Legalization under Technology and Region Constraints 査読有り国際誌

Zhou C., Cao Y., Shi Q., Wang L., Wen X.

ACM Transactions on Design Automation of Electronic Systems 29 ( 6 ) 2024年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

The evolution of advanced technology nodes has prompted a shift toward mixed-cell-height circuit design, while the introduction of technology and fence region constraints further increases the complexity of placement. In this article, we innovatively transform the mixed-cell-height circuit legalization problem into a generalized absolute value equation (GAVE) and propose a novel and effective robust Newton (RN) iteration method to address the challenge of the legalization problem.<sup>1</sup> First, the window-based cell insertion technique is applied to obtain the initial cell row allocation and cell order, and the cells are allocated to the matching region based on the R-tree structure. Then, the legalization problem of cells within the region is transformed into a GAVE, and an RN iteration method is proposed to solve the GAVE. Finally, the maximum displacement cells and technology violation cells are optimized based on a greedy method. Experimental results confirm the efficiency and robustness of the proposed method compared with the state-of-the-art methods.

DOI： 10.1145/3689436

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MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method 査読有り国際誌

Yan A. (合肥工業大学), Li Z., Gao Z., Zhang J., Huang Z., Ni T., Cui J., Wang X., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43 ( 7 ) 2205 - 2214 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability of latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. In this article, we propose a novel latch, namely, MURLAV, protected against quadruple node-upsets (QNUs) induced in harsh radiation environments, as well as an algorithmic error-recovery verification method. The latch provides complete recovery from all QNUs with a formed redundant structure. The algorithm can simplify the verification process and demonstrate the QNU recovery for the proposed MURLAV latch. Simulation results demonstrate that the proposed latch can recover from any QNU and that it has lower area and delay overhead. Compared with existing latches of the same type, the proposed MURLAV latch achieves an overhead reduction of 34% in silicon area and 15% in delay on average at the cost of moderate power consumption.

DOI： 10.1109/TCAD.2024.3357593

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A new die-level flexible design-for-test architecture for 3D stacked ICs 査読有り国際誌

Zhang Q., Zhan W., Wen X.

Integration 97 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

DOI： 10.1016/j.vlsi.2024.102190

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Efficient design approaches to CMOS full adder circuits 査読有り国際誌

Yan A., Bao H., Jiang W., Cui J., Huang Z., Wen X.

Microelectronics Journal 149 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %.

DOI： 10.1016/j.mejo.2024.106235

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IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications 査読有り国際誌

Yan A., Dong C., Guo X., Song J., Cui J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 19 - 24 2024年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Modern powerful CMOS chips are usually highly integrated and implemented with aggressively shrunk technology nodes. In radiation environment, under charge-sharing mechanism, one particle striking can simultaneously impact multiple nodes causing double-node-upsets (DNUs) and triple-node-upsets (TNUs). In this paper, we propose an Interlocked Dual-circle Latch Design, namely IDLD, with low cost and TNU recovery for aerospace applications. IDLD consists of four transmission gates and twelve 2-input C-elements (CEs) implemented in 22nm CMOS process. Simulation results demonstrate the complete TNU recovery as well as cost-effectiveness for the proposed IDLD latch.

DOI： 10.1145/3649476.3658761

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A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors 査読有り国際誌

Xu H., Li J., Ma R., Liang H. (合肥工業大学), Liu C., Wang S., Wen X.

IEEE Transactions on Device and Materials Reliability 24 ( 2 ) 302 - 312 2024年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations.

DOI： 10.1109/TDMR.2024.3386954

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FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell 査読有り国際誌

Yan A., Chen Y., Gao Z., Ni T., Huang Z., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 71 ( 4 ) 2299 - 2303 2024年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

The Von-Neumann memory wall bottleneck that keeps expanding is mainly caused by the frequent data transfer between the main memory and the processor. The processing in-memory (PiM) capabilities of emerging nonvolatile devices have the potential to partially alleviate the memory wall problem. In this brief, we use the ferroelectric field-effect transistor (FeFET), one of the emerging nonvolatile devices, to design a multifunctional processing in-memory cell, namely FeMPIM. It can perform multiple logic operations in computing mode as well as content searching in ternary content-addressable memory (TCAM) mode. Simulation results demonstrate the multifunctional capability of the proposed FeMPIM as well as its moderate overhead when compared with the complementary metal-oxide-semiconductor (CMOS) based and the existing FeFET-based devices.

DOI： 10.1109/TCSII.2023.3331267

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SwinT-ILT: Swin Transformer embedding end-To-end mask optimization model 査読有り国際誌

Xu H., Qi P., Tang F., Ma R., Liang H., Huang Z., Wen X.

Journal of Micro/Nanopatterning, Materials and Metrology 23 ( 1 ) 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Background: Resolution enhancement techniques (RETs) are widely used to improve the quality of masks in lithography flow. Optical proximity correction (OPC), such as inverse lithography technology (ILT), improves mask printability, but conventional ILT suffers from computational overhead. Advanced learning-based methods accelerate the optimization process, but the quality of its mask could be more satisfactory to academia and industry. Aim: To improve the quality of masks while accelerating the optimization process, we propose SwinT-ILT, an end-To-end ILT optimization framework embedded in the Swin Transformer. Approach: The framework consists of a feature extraction module and a feature construction module. Leveraging the Swin Transformer, the feature extraction module extracts deep features, and the feature construction module reconstruct masks based on in-depth features. To enhance the resolution of feature maps without introducing noise, we incorporate a pixel shuffle layer into the feature construction module. Furthermore, we set a specific training objective that introduces the domain knowledge of the imaging system, thereby accelerating the convergence. Results: Quantitative results show that our SwinT-ILT achieves exceptional mask printability with relative mask manufacturability in only 0.5 s turnaround time. Conclusions: Our work contributes to the industry by effectively reducing semiconductor manufacturing cycles and enhancing manufacturing quality.

DOI： 10.1117/1.JMM.23.1.013201

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Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS 査読有り国際誌

Yan A., Wang L., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32 ( 1 ) 116 - 127 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) are widely used to address these concerns. MTJs are nonvolatile (NV) and compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant and NV latch, i.e., M-TPDICE-V2, providing high reliability. In addition, we further propose an advanced latch, namely, M-8C, that is able to completely recover from single-node upsets (SNUs) and DNUs. M-8C uses a DNU recovery module and a backup and restore module based on a pair of MTJs. Furthermore, we propose a universal backup and restore module suitable for any latch providing nonvolatility. We simulate the proposed latches using the Synopsys HSPICE tool with a 45-nm CMOS process model. Simulation results confirm the superior capabilities of our proposed M-TPDICE-V2 and M-8C latches. M-TPDICE-V2 exhibits strong SNU and DNU tolerance and nonvolatility, while the M-8C latch provides complete DNU recovery capabilities.

DOI： 10.1109/TVLSI.2023.3323562

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Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs 査読有り国際誌

Wang S., Wei S., Okamoto H., Nishikawa T., Kai H., Higami Y., Yotsuyanagi H., Ma R., Ni T., Takahashi H., Wen X.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel Test Point Insertion (TPI) strategy to enhance the testability for multi-cycle Built-In Self-Test (BIST) for logic circuits. The approach leverages Multivariate Temporal-Spatial Graph Convolutional Neural Networks (MTS-GCN) and Reinforcement Learning to identify optimal Test Points (TPs). The proposed TPI method treats the testability information of a logic circuit as time-series data and employs Multivariate Time-Series Graph Neural Networks (MTGNN) to capture the relationship between the circuit's structural (spatial information) attributes and the temporal variability of signal line testability across capture cycles. A subsequent Multi-Layer Perceptron (MLP) computes the metric for each signal line to pinpoint potential TPs based on the extracted temporal-spatial features. Experimental evaluation based on benchmark circuits confirms the efficacy of the proposed model, which is trained with Deep Q-Networks (DQN), in improving the fault detection for multi-cycle logic BIST.

DOI： 10.1109/ITC-Asia62534.2024.10661324

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SHRCO: Design of an SRAM with High Reliability and Cost Optimization for Safety-Critical Applications 査読有り国際誌

Chang Y., Liu G., Ullah I., Shan G., Wen X., Yan A.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel radiation-hardened high-reliability SRAM cell, namely SHRCO, with 12 transistors for robust value storage as well as 6 transistors for parallel access operations. Using separated and error-interceptive feedback paths, the proposed cell has a complete self-recoverability from single-node upset (SNUs) at all single nodes and an excellent self-recoverability from double-node upsets (DNUs) at a part of node pairs. In addition, the proposed cell has superior access operation speed due to the inclusion of extra parallel access transistors. Simulation results show that the proposed cell has the largest number of node pairs that can self-recover from DNUs. Moreover, compared to the existing radiation-hardened SRAM cells, the proposed cell saves 28% of read time and 3% of write time on average.

DOI： 10.1109/ITC-Asia62534.2024.10661340

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SRBML: A Single-Event-Upset Recoverable and BTI-Mitigated Latch Design for Long-Term Reliability Enhancement 査読有り国際誌

Xia F., Zhang J., Ali J., Zhang C., Wen X., Yan A.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Soft-errors and aging are considered as two primary factors affecting the long-term reliability of aerospace integrated circuits (ICs). As one of the key components in aerospace ICs, latches play a pivotal role to ensure desirable circuit functionality. This paper presents a single-event-upset recovery latch, namely SRBML, with bias-temperature-instability (BTI)-mitigation. By optimizing its internal structure, the latch can recover from single-event-upsets (SEUs) and reduce the stress time of transistors in feedback loops to simultaneously mitigate the impact of BTI on the latch. Simulation results demonstrate that the soft error rate increase due to BTI is reduced by roughly 34% for SRBML after BTI-mitigation. In addition, the delay of SRBML is not affected, and the area and power increase are limited compared to BTI-unmitigated latches.

DOI： 10.1109/ITC-Asia62534.2024.10661343

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PFO PUF: A Lightweight Parallel Feed Obfuscation PUF Resistant to Machine Learning Attacks 査読有り国際誌

Huang Z., Lin Y., Zeng F., Bian J., Yang Z., Liang H., Lu Y., Yao L., Wen X., Ni T.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Arbiter Physically Unclonable Functions (APUFs) are hardware security primitives that leverage manufacturing process variation to generate security keys. They can produce exponential challenge-response pairs (CRPs) with minimal hardware overhead. However, the symmetric nature of linear additive functions makes them vulnerable to modeling attacks rooted in machine learning. To address this issue, this paper introduces a novel design called Parallel Feed Obfuscation PUF (PFO PUF). In this approach, the intermediate decision signals from the lower APUF are used as a concealed challenge for the upper APUF, enhancing the overall nonlinearity of the dual-APUF. Additionally, obfuscation modules are employed to determine the weights of the intermediate decision signals from both the upper and lower APUFs, protecting the actual response. Experimental results demonstrate that the proposed PFO PUF effectively withstands four advanced machine learning attack algorithms, including Logistic Regression (LR), Support Vector Machine (SVM), Deep Feedforward Neural Network (DFNN), and Efficient CANDECOMP/PARAFAC Tensor Regression Network (ECPTRN). The prediction accuracy of these four algorithms is consistently below 66.30%. Compared with other enhanced structures based on APUF, PFO-PUF only uses 493 LUTs and has lower resource overhead.

DOI： 10.1109/ITC-Asia62534.2024.10661356

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CQCTL: A Cost-Optimized and Quadruple-Node-Upset Completely Tolerant Latch Design for Safety-Critical Applications 査読有り国際誌

Shen Z., Zhang Q., Roh B.H., Song J., Wen X.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid development of semiconductor technologies, latches are becoming increasingly sensitive to multiple node upsets, such as triple node upsets and quadruple node upsets (QNUs). Therefore, they should be considered for safety-critical applications. To effectively tolerate QNUs, this paper proposes a QNU-tolerant latch design with moderate overhead. The latch mainly comprises two parallel storage cells, and three 2-input C-elements. When any four internal nodes are flipped at the same time, the output value of the latch will not be affected. Simulation results not only confirm the QNU tolerance of the proposed latch but also demonstrate that the latch can reduce by 40.93% delay, 40.73% area, 13.11% power, and 71.19% delay-area-power product (DAPP) on average compared to the existing QNU-tolerant latches.

DOI： 10.1109/ITC-Asia62534.2024.10661360

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Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based Reconfigurable Processor (MRP) 査読有り国際誌

Sasagawa K., Wang S., Nishikawa T., Kai H., Higami Y., Takahashi H., Yotsuyanagi H., Ni T., Wen X.

2024 International Technical Conference on Circuits Systems Computers and Communications Itc Cscc 2024 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The Memory-based Reconfigurable Processor (MRP) is a memory-centric reconfigurable device that offers advantages in processing speed and cost compared to other reconfigurable devices like FPGAs, making it a promising alternative device for Artificial Intelligence applications such as neural networks (NNs). However, due to the unique structure of MRP, the method for implementing NNs on it has not yet been established. In our previous work [8], we have proposed a sparse neural network model named MNN (MRP Neural Networks), specifically designed to align with the unique connection structure of MRP for neural network integration. This paper extends our research by proposing a binarization method for MNN referred to as the BMNN using XNOR-Net to facilitate practical NNs application (handwriting digits recognition) on MRP. To enhance the performance of BMNN, a novel implementation strategy Deep-BMNN is also proposed aimed at increasing both the layer depth and the neuron count of BMNN by folding the logic routing on the MRP device. Experimental results using MNIST dataset for handwritten digits recognition demonstrate that our proposed binary NNs for MRP can achieve comparable accuracy to those of fully connected NNs employing real numbers.

DOI： 10.1109/ITC-CSCC62988.2024.10628398

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ICLTR: A Input-split Inverters and C-elements based Low-Cost Latch with Triple-Node-Upset Recovery 査読有り国際誌

Zhang J., Li Z., Shan G., Song J., Guo X., Wen X.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the semiconductor technology continues to advance, integrated circuits (ICs) are becoming increasingly sensitive to soft errors, e.g., double-node upsets (DNUs) and triplenode upsets (TNUs), induced by harsh radiation. In this paper, a low-cost latch design, namely ICLTR, using input-split inverters (ISIs) and C-elements to provide complete TNU recovery, is proposed. ICLTR consists of seven ISIs, seven 2-input C-elements and a clock-gated inverter, and all these elements are interlocked. Simulation results show the complete TNU recovery for ICLTR. The simulation results also show that ICLTR can save 59.5% of the transmission delay, 36.1% of the power consumption and 81.6% of the delay-area-power product (DAPP) on average when compared with the same type of TNU recovery latch designs.

DOI： 10.1109/ITC-Asia62534.2024.10661358

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Multiple-Error Interceptive Voter Designs for Safety-Critical Applications 査読有り国際誌

Li X., Song J., Zhang C., He Y., Wen X., Huang Z.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes multiple-error interceptive voter designs for safety-critical applications. The proposed baseline voters comprise two-stage error-filters, in which the first stage includes two parallel C-elements (CEs) and the second stage includes one CE to filter soft errors. The voters have high-speed versions, any of which is embedded with a high-speed path from its original input to its output to reduce delay. Simulation results demonstrate the soft error tolerance of the proposed voters. Moreover, compared with the triple-modular-redundancy (TMR) voter that can only tolerate single soft errors, the proposed 3-input baseline and 4-input high-speed voters can tolerate double soft errors and can reduce the area-power-delay product by 77.03% and 95.05%, respectively, due to the use of a few transistors and a high-speed path. The voters are extended to intercept N-1 soft errors, N being the number of inputs of each voter. Note that the voters are also extended to make so that they can tolerate hard/permanent errors in addition to soft errors.

DOI： 10.1109/ITC-Asia62534.2024.10661339

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NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization 査読有り国際誌

Huang Z., Sun L., Wang X., Liang H., Lu Y., Yan A., Pan J., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 60 ( 4 ) 4590 - 4600 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Multi-node upset induced by radiation on integrated circuits has caused many circuit reliability issues. This paper proposes a single-event quadruple-node upset recovery latch (NEST), based on 4 circular feedback loops that are formed by 25 C-elements to realize high robustness. NEST achieves 29.02% reduction in power consumption compared to the LDAVPM latch and 51.44% reduction in setup time compared to the QRHIL latch. NEST also achieves a 99.29% quadruple-node upset recovery rate. Furthermore, a high-speed, high-precision optimization algorithm for multi-node upset recovery is also proposed and implemented. This algorithm achieves 99.84% reduction in simulation time for exhaustive fault injections having equivalent accuracy with HSPICE.

DOI： 10.1109/TAES.2024.3379962

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Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications 査読有り国際誌

Yan A., He Y., Huang Z., Yan W., Cui J., Wang X., Ni T., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44 ( 1 ) 390 - 394 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents radiation-hardened flip-flop (FF) designs capable of tolerating soft errors, e.g., single-node upsets (SNUs), double-node upsets (DNUs) and multiple-node upsets (MNUs). First, a 2-input FF and a 3-input FF are proposed as the baseline FFs that not only respectively tolerate SNUs and DNUs but also exhibit cost efficiency in terms of delay, power, and area. Through adding two stages of C-elements, a 4-input FF and a 5-input FF are proposed as the baseline FFs as well. Utilizing the structural characteristics of these FFs, an N-1 input FF and an N input FF are proposed as the extended FFs capable of tolerating more node upsets. Moreover, a highly efficient algorithm for verifying MNU-tolerance of these FFs is proposed. Algorithm and HSPICE-tool-based verification results both demonstrate the MNU-tolerance for the proposed FFs with more inputs.

DOI： 10.1109/TCAD.2024.3426271

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Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices 査読有り国際誌

Yan A., Lin Z., Liu G., Zhang Q., Huang Z., Cui J., Wen X., Girard P.

Proceedings - IEEE International Symposium on Circuits and Systems 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Nonvolatile memories are widely used in emerging energy-harvesting Internet-of-Things (IoT) applications, and nonvolatile memories constructed from FeFET devices hold great promise. This paper presents a nonvolatile and single-event-upset (SEU)-recoverable latch based on FeFET and CMOS for energyharvesting devices. The latch uses n-type FeFET devices to provide nonvolatility without any additional control signals. Moreover, since the soft error problem has become increasingly severe, radiation hardening by design gains a great attention as a promising approach to mitigate the reliability issue. The latch uses feedback interlocked loops with n-type FeFETs and C-elements, enabling it to provide nonvolatility and SEU-recovery simultaneously. Simulation results with Candence Virtuoso verifies that the proposed latch design has correct functioning with excellent performance compared to the state-of-the-art designs.

DOI： 10.1109/ISCAS58744.2024.10558033

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Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware 査読有り国際誌

Ni T., Wen X., Amrouch H., Zhuo C., Song P.

ACM Transactions on Design Automation of Electronic Systems 29 ( 1 ) 2023年12月

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness 査読有り国際誌

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wang S., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 70 ( 12 ) 5074 - 5085 2023年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the input changes too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses. We study the output of the XOR gate when facing different inputs. By modeling the time of a fibonacci ring oscillator (FIRO) as an example, we find that the loss of short pulses in an inverter chain is the reason for making the FIRO enter into periodic oscillation. This phenomenon suppresses the accumulation of jitter and occurs periodically in existing structures. Our proposed structure uses independent sub-rings to accumulate jitter, allowing the main-ring to quickly generate short pulses to provide analog randomness. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA. The experimental results show that it has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.

DOI： 10.1109/TCSI.2023.3287162

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RMC-NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel 査読有り国際誌

Xu D., Ouyang Y., Zhou W., Huang Z., Liang H., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 ( 12 ) 2061 - 2074 2023年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

As chip fabrication has advanced to the nano level, the increased link density has heightened the risk of failures. The potential performance drawbacks resulting from these link failures have become a critical challenge in the design of reliable network-on-chip (NoC) systems. Fault-tolerant routing algorithms have proven to be effective strategies for handling this issue by diverting packets away from failed links to prevent congestion. However, these algorithms often result in excessive packet diversion, especially in the presence of a higher failure rate, which can significantly constrain the network's behavior. This article introduces a novel NoC design with reconfigurable multifunctional channels (RMC-NoC). This design dynamically adapts the channel functions in response to network conditions to ensure that packets from failed links follow their original paths. In addition, it presents a channel buffer bubble flow control mechanism that can resolve congestion by redistributing congested traffic within the channel buffer. The evaluation results demonstrate that our approach ensures superior network communication even in the presence of permanent link failures, with minimal area overhead and power consumption. Moreover, our system exhibits lower latency and higher throughput compared to state-of-the-art fault-tolerant methods across various link failure rates. Notably, even at a severe failure rate of 30%, RMC-NoC exhibits only a 16.3% increase in latency compared to an ideal failure-free environment (Baseline) while still maintaining system communication capabilities to a considerable extent.

DOI： 10.1109/TVLSI.2023.3321598

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An AI-Driven VM Threat Prediction Model for Multi-Risks Analysis-Based Cloud Cybersecurity 査読有り国際誌

Saxena D., Gupta I., Gupta R., Singh A.K., Wen X.

IEEE Transactions on Systems, Man, and Cybernetics: Systems 53 ( 11 ) 6815 - 6827 2023年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Cloud virtualization technology, ingrained with physical resource sharing, prompts cybersecurity threats on users' virtual machines (VMs) due to the presence of inevitable vulnerabilities on the offsite servers. Contrary to the existing works which concentrated on reducing resource sharing and encryption/decryption of data before transfer for improving cybersecurity which raises computational cost overhead, the proposed model operates diversely for efficiently serving the same purpose. This article proposes a novel multiple risks analysis-based VM threat prediction model (MR-TPM) to secure computational data and minimize adversary breaches by proactively estimating the VMs threats. It considers multiple cybersecurity risk factors associated with the configuration and management of VMs, along with analysis of users' behavior. All these threat factors are quantified for the generation of respective risk score values and fed as input into a machine learning-based classifier to estimate the probability of threat for each VM. The performance of MR-TPM is evaluated using benchmark Google Cluster and OpenNebula VM threat traces. The experimental results demonstrate that the proposed model efficiently computes the cybersecurity risks and learns the VM threat patterns from historical and live data samples. The deployment of MR-TPM with existing VM allocation policies reduces cybersecurity threats up to 88.9%.

DOI： 10.1109/TSMC.2023.3288081

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Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications 査読有り国際誌

Yan A., Cao A., Huang Z., Cui J., Ni T., Girard P., Wen X., Zhang J.

IEEE Transactions on Emerging Topics in Computing 11 ( 4 ) 1070 - 1081 2023年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

The continuous advancement of complementary metal-oxide-semiconductor technologies makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as double-node upsets (DNUs), are typical soft errors. This article proposes two radiation-hardened FF designs, namely DNU-tolerant FF (DUT-FF) and DNU-recoverable FF (DUR-FF). First, the DUT-FF which mainly consists of four dual-interlocked-storage-cells (DICEs) and three 2-input C-elements, is proposed. Then, to provide complete self-recovery from DNUs, the DUR-FF which mainly uses six interlocked DICEs is proposed. They have the following advantages: 1) They can completely protect against SNUs as well as DNUs; 2) the DUT-FF is cost-effective but the DUR-FF can provide complete self-recovery from any DNU. Simulations show the complete SNU/DNU tolerance of DUT-FF and the complete SNU/DNU self-recovery of DUR-FF but at the cost of indispensable area overhead when compared to the SNU hardened FFs. Besides, compared to the FFs of the same-type, the proposed FFs achieve a low delay making them suitable for high-performance applications.

DOI： 10.1109/TETC.2023.3317070

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GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting<sup>∗</sup> 査読有り国際誌

Shi S., Holst S., Wen X.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E106.D ( 10 ) 1694 - 1704 2023年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC’99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

DOI： 10.1587/transinf.2023EDP7011

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An equivalent processing method for integrated circuit electrical parameter data using BP neural networks 査読有り国際誌

Zhan W., Zhang L., Feng X., Pan P., Cai X., Wen X.

Microelectronics Journal 139 2023年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

In response to the current problem of significant differences between old and new equipment in testing electrical parameter data, as well as the lack of a unified parameter measurement standard in the IC testing industry, we propose an equivalent processing method for electrical parameter data using BP neural networks. Firstly, the method involves mapping the electrical parameter data measured by both the old and new equipment and subsequently trimming the test data. Then, the BP neural network is applied to the equivalent processing of the dataset, aiming to unify the test limits and electrical parameter data. This approach facilitates the extrapolation of new data from old equipment data, enabling a seamless data transfer and the harmonization of industry standards. This method effectively reduces the testing difficulty and misjudgment rate, thereby improving the testing efficiency for semiconductor manufacturers. The experimental results demonstrate that the proposed algorithm can accurately infer the new equipment's test data from the old equipment's data, ensuring data smooth transition. Furthermore, the modification of electrical parameter data does not affect the yield.

DOI： 10.1016/j.mejo.2023.105912

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Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications 査読有り国際誌

Yan A., Xiang J., Chang Y., Huang Z., Cui J., Girard P., Wen X.

Microelectronics Journal 139 2023年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper first presents a double-node upset (DNU) protected and sextuple cross-coupled static-random-access memory (SRAM) cell, i.e., SCCS-18T, for aerospace applications. The cell can recover from each possible single-node upsets (SNUs) as well as partial DNUs due to its formed large feedback loop that can retain values and intercept errors. To improve DNU self-recoverability, an enhanced version of the SCCS-18T cell, namely SCCS-18T-EV, is proposed. Due to the new formed structure, the SCCS-18T-EV can recover from more DNUs. Since parallel access transistors are used, the proposed cells have optimized read/write performance. Simulation results demonstrate the node-upset tolerance as well as the optimized operation performance of the proposed SCCS-18T and SCCS-18T-EV cells compared to existing SRAM cells.

DOI： 10.1016/j.mejo.2023.105908

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Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata 査読有り国際誌

Yan A., Li X., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland) 12 ( 14 ) 2023年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

DOI： 10.3390/electronics12143189

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A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications 査読有り国際誌

Yan A., Wei S., Zhang J., Cui J., Song J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 167 - 171 2023年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose a double-node-upset recoverable latch that can completely recover from all possible double-node-upsets (DNUs) with low area and low delay. The latch consists of seven 2-input C-elements (CEs) implemented in 22nm complementary metal oxide semiconductor (CMOS) technology, making it area-efficient. The proposed latch employs the clock gating methodology and a high-speed transmission path, enabling it to perform with lower overhead in terms of transmission delay and power dissipation. Simulation results demonstrate that the proposed latch can provide complete DNU recovery. Compared with typical double-node-upset-recoverable latches, the proposed latch can save 89.74% of Area-Delay-Power Product (ADPP) on average.

DOI： 10.1145/3583781.3590281

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Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications 査読有り国際誌

Yan A., Chang Y., Xiang J., Luo H., Cui J., Huang Z., Ni T., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 293 - 298 2023年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose two Highly Reliable and High-Speed SRAM cells, namely HRHS18T and HRHS18T_EV. The proposed cells can be applied to safety-critical applications due to their excellent self-recoverability from node-upsets. Meanwhile, the proposed cells have smaller read/write delay than other state-of-the-art hardened SRAMs. Simulation and quantitative calculation results show that, the proposed HRHS18T cell can save 65.05% read time and 38.12% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs. The results also show that the HRHS18T_EV cell can save 65.05% read time and 73.28% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs.

DOI： 10.1145/3583781.3590261

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Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array 査読有り国際誌

Chen N., Cheng F., Han C., Jiang J., Wen X.

Tsinghua Science and Technology 28 ( 2 ) 330 - 343 2023年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

To solve the problem of grid coarse-grained reconfigurable array task mapping under multiple constraints, we propose a Loop Subgraph-Level Greedy Mapping (LSLGM) algorithm using parallelism and processing element fragmentation. Under the constraint of a reconfigurable array, the LSLGM algorithm schedules node from a ready queue to the current reconfigurable cell array block. After mapping a node, its successor's indegree value will be dynamically updated. If its successor's indegree is zero, it will be directly scheduled to the ready queue; otherwise, the predecessor must be dynamically checked. If the predecessor cannot be mapped, it will be scheduled to a blocking queue. To dynamically adjust the ready node scheduling order, the scheduling function is constructed by exploiting factors, such as node number, node level, and node dependency. Compared with the loop subgraph-level mapping algorithm, experimental results show that the total cycles of the LSLGM algorithm decreases by an average of 33.0% (PEA4×4) and 33.9% (PEA7×7). Compared with the epimorphism map algorithm, the total cycles of the LSLGM algorithm decrease by an average of 38.1% (PEA4×4) and 39.0% (PEA7×7). The feasibility of LSLGM is verified.

DOI： 10.26599/TST.2022.9010001

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Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning 査読有り国際誌

Nie M., Jiang W., Yang W., Wang S., Wen X., Ni T.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Defect diagnosis and localization in wafer maps are crucial tasks in semiconductor manufacturing. Existing deep learning methods often require pixel-level annotations, making them impractical for large-scale deployment. In this paper, we propose a novel weakly supervised learning approach to achieving high-precision defect identification and effective localization with only image-level labels. By leveraging the information of defect types and locations, we introduce a weighted fusion of activation maps, called Class Activation Map (CAM), to highlight classspecific regions. We further enhance defect localization accuracy and completeness by employing optimized region growing operations to eliminate noise in defect regions. Moreover, we present an optimized inference method that provides meaningful visual explanations for defect recognition. Experimental results on real-world wafer map images demonstrate the effectiveness of our approach in accurately segmenting defect patterns with no pixel-level annotations. By training the model solely on wafer map image classification labels, our proposed model significantly improves defect recognition, facilitating efficient defect analysis in semiconductor manufacturing. The proposed weakly supervised learning approach offers a practical solution for defect diagnosis and localization, with the potential of widespread adoption in the semiconductor industry.

DOI： 10.1109/ATS59501.2023.10317989

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Design of Low-Cost Approximate CMOS Full Adders 査読有り国際誌

Yan A., Wei S., Li Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2023-May 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Many applications have an inherent tolerance for insignificant inaccuracies. Full adders are key arithmetic functions for many error-tolerant applications. Approximate full adders are considered an efficient technique to trade off energy relative to performance and accuracy. In this paper, we propose four approximate full adders with low overhead. The proposed and the existing approximate full adders are classified into two groups according to their error distances. Simulation results show that, compared with the existing approximate full adders, in the first group, the proposed ones can reduce power-area-delay product (PADP) by 61.83%, power by 54.15%, area by 44.67%, and delay by 22.78% on average; in the second group, the proposed ones can reduce PADP by 97.01%, power by 93.43%, area by 24.98%, and delay by 36.14% on average.

DOI： 10.1109/ISCAS46773.2023.10181531

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Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness 査読有り国際誌

Yan A., Zhou C., Wei S., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As CMOS processes continue to shrink, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiation. To tolerate MNU, a novel quadruple-node-upset (QNU) self-recoverable latch is proposed in this paper. The proposed latch is mainly constructed from six blocks of three-level C-elements (TLCEs) and six inverters. With the mutual feedback of the various TLCEs, the proposed latch can recover from any QNU. Furthermore, due to the clock gating methodology and a high-speed transmission path, the proposed latch has lower overhead in terms of power dissipation and transmission delay. Simulation results show that the proposed latch achieves high reliability with moderate overhead compared to typical existing latches.

DOI： 10.1109/ITC-Asia58802.2023.10301187

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Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications 査読有り国際誌

Yan A., Xiang J., Huang Z., Ni T., Cui J., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

For high-speed operations, low power consumption and small silicon area, transistors are being scaled aggressively. Meanwhile, circuit reliability is facing greater challenges in advanced technologies. In this paper, a highly reliable and low-power SRAM with double-node-upset (DNU) recovery, namely HRLP16T, is proposed for safety-critical fields. HRLP16T can recover from single-node-upset (SNU) at all the sensitive nodes, and it has eight node pairs recoverable from DNUs. Simulation results demonstrate its advantages in terms of delay and power consumption over typical existing SRAM cell designs.

DOI： 10.1109/ITC-Asia58802.2023.10301170

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BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell 査読有り国際誌

Holst S., Ma R., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2023-May 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Ensuring the correct operation of modern VLSI circuits within safety-critical systems is essential since modern technology nodes are more susceptible to Early-Life Failures (ELFs) and radiation-induced Soft-Errors (SEs). Tackling both of these challenges leads to contradicting design requirements: Effective in-field ELF detection requires online-monitoring or periodic built-in self-Testing with excellent cell-internal defect coverage. SE-hardened latch designs, however, are less testable because they are designed to mask cell-internal failures. We propose BiSTAHL, a new SE-hardened scan-cell design that is fully built-in self-Testable for both production defects and ELFs.

DOI： 10.1109/ETS56758.2023.10174154

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Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications 査読有り国際誌

Yan A., Li X., Gao Z., Huang Z., Ni T., Wen X.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of CMOS technologies, integrated circuits are becoming more prone to soft errors, e.g., triple-node upsets (TNUs). In this paper, to effectively tolerate TNUs, an input-split C-element-based DICEs (IC-DICEs) based TNU-recovery latch is proposed. The latch employs three interlocked IC-DICEs to allow recovering from any TNU. Simulations demonstrate the TNU recovery of the latch, and also demonstrate that the proposed latch can reduce delay by 87.21%, area by 27.04%, and delay-area-power product (DAPP) by 87.44% on average, compared to the alternative latches.

DOI： 10.1109/ATS59501.2023.10317977

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A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery 査読有り国際誌

Yan A., Li X., Ni T., Huang Z., Wen X.

Proceedings - 2023 10th International Conference on Dependable Systems and Their Applications, DSA 2023 474 - 476 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The aggressive shrinking of CMOS makes flip-flops (FFs) vulnerable to single-node upset (SNU) as well as double-node upset (DNU). SNU and DNU are typical soft errors. This paper presents a highly reliable and low delay FF providing complete DNU-recovery. Simulations show the complete DNU-recovery as well as low-delay for our proposed FF making the FF suitable for high-robustness and high-performance applications.

DOI： 10.1109/DSA59317.2023.00065

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A Low Overhead and Double-Node-Upset Self-Recoverable Latch 査読有り国際誌

Yan A., Xia F., Ni T., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of semiconductor technologies, integrated circuits, especially storage elements (e.g., latches) have become increasingly vulnerable to soft errors. In order to effectively tolerate double-node-upsets (DNUs) caused by radiation and reduce the power and area of latches, this paper proposes a DNU self-recoverable latch with low overhead in terms of power and area. The proposed latch mainly comprises seven 2-input C-elements and two inverters to achieve DNU self-recovery. Simulation results show that the proposed latch can recover from all possible DNUs and that it can reduce delay by 45.7%, power by 29.1%, area by 65.9%, and area-power-delay-product by 87.4%, on average, compared to typical existing DNU self-recoverable latches.

DOI： 10.1109/ITC-Asia58802.2023.10301166

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A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges 査読有り国際誌

Ni T., Li F., Peng Q., Wang S., Wen X.

Proceedings of the 2023 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Physically unclonable functions (PUFs) are an attractive and low-cost security primitive because it requires no storage and is easy to implement. PUFs arise from changes in the manufacturing process of the device and can generate secure and unique keys for secure storage, authentication, and data encryption. In addition, the keys generated by PUFs should be reliable, independent, and themselves resistant to attacks and reverse engineering. In this paper, a new PUF framework is proposed, which segments the whole structure, introduces the non-linearity of the structure, uses the previous challenges and the later challenges are XOR with the previous response, which introduces the obfuscation of the challenges to improve the resistance to machine learning attack. The framework can be used for any kind of strong PUF implementation. In this paper, the whole framework is implemented with RO ring PUF, the PUF shows excellent performance, and the RO ring is modified with four input multiplexer and only a pair of counters and a comparator for multiple rings, which significantly reduces the hardware resource consumption. The PUF has passed machine learning attacks with significant resistance to Logistic Regression(LR) and Covariance Matrix Adaptation Evolutionary Strategies(CMA-ES).

DOI： 10.1109/AsianHOST59942.2023.10409383

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A High-Performance and P-Type FeFET-Based Non-Volatile Latch 査読有り国際誌

Yan A., Chen Y., Huang Z., Cui J., Wen X.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Non-volatile memory has a significant future in the Internet of Things and computation-in-memory applications. Among them, non-volatile memories using emerging FeFET devices have garnered significant attention. This paper proposes a novel P-type FeFET -based non-volatile latch. This design takes advantage of the unique characteristics of a P-type FeFET device to achieve non-volatility with no additional control signals. The Cadence simulation tool Virtuoso verifies that our proposed design has correct functioning with excellent power, area, and delay performance compared to state-of-the-art designs.

DOI： 10.1109/ATS59501.2023.10318017

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Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling 査読有り国際誌

Shi S., Holst S., Wen X.

Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 501 - 507 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scan shift causes a lot of switching activity in the combinational logic that in turn can lead to high IR-drop. Excessive IR-drop may corrupt test vectors or responses during shifting, leading to test-induced yield-loss. Power-aware X-filling is a widely used method to reduce the overall switching activity during shifting without modifying the scan infrastructure. While such untargeted approaches help reduce the average IR-drop during shifting, some hot-spots of worst-case IR-drop still remain. Through an innovative in-depth IR-drop analysis of high-risk shift cycles, we discovered that these hot-spots are caused by a few High-Impact scan-cell Transitions (HITs). In this paper, we propose to reduce the peak IR-drop during scan shift by using a novel X-filling strategy that (1) identifies HITs through GPU-accelerated IR-drop estimation, and (2) adjusts the X-filling of test vectors to mitigate the remaining worst-case IR-drop hotspots. The results on ITC'99 benchmark circuits demonstrate a 26% peak IR-drop reduction on average without impact on fault coverage or test vector count.

DOI： 10.1109/MCSoC60832.2023.00080

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SASL-JTAG: A Light-Weight Dependable JTAG 査読有り国際誌

Wang S., Wei S., Ma J., Kai H., Higami Y., Takahashi H., Shimizu A., Wen X., Ni T.

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper addresses the performance imbalance issue of IoT systems and proposes a lightweight JTAG authentication scheme for enhancing the dependability of IoT devices. We propose a one-time authentication protocol, called SAS-L(Simple And Secure Light authentication), to improve the dependability of the JTAG, referred to as SASL-JTAG. The architecture of the SASLJTAG authentication is designed and implemented on an FPGA to verify its functionality and evaluate hardware overhead. SASL-JTAG offers a cost-effective and scalable solution for securing JTAG systems in IoT devices while ensuring high reliability.

DOI： 10.1109/DFT59622.2023.10313532

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A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design 査読有り国際誌

Yan A., Wei S., Chen Y., Fan Z., Huang Z., Cui J., Girard P., Wen X.

Micromachines 13 ( 11 ) 2022年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.

DOI： 10.3390/mi13111802

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A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications 査読有り国際誌

Yan A., Qian K., Song T., Huang Z., Ni T., Chen Y., Wen X.

Integration 86 22 - 29 2022年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a novel radiation hardened latch (namely DCTELC) that can completely tolerate single-node upsets and double-node upsets (DNUs) for high-performance applications. The latch mainly consists of a clock-gating based dual-interlocked-cell (DICE), a 2-input C-element, and a clock-gating based 2-input C-element. The latch introduces isolated nodes to tolerate DNUs and the isolated nodes have no time to float for high-performance applications. Simulation results demonstrate the complete DNU tolerance for the latch and an 86% power-area-delay product (PADP) saving on average compared with state-of-the-art DNU-tolerant latches. Moreover, compared with the existing latches of the same type, the power dissipation, silicon area, transmission delay, and PADP of the proposed latch are the smallest.

DOI： 10.1016/j.vlsi.2022.04.008

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A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology 査読有り国際誌

Yan A., Zhou Z., Wei S., Cui J., Zhou Y., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 255 - 260 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input C-elements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively.

DOI： 10.1145/3526241.3530321

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Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications 査読有り国際誌

Yan A., He Z., Xiang J., Cui J., Zhou Y., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 261 - 266 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Aggressive scaling of CMOS technologies requires to pay attention to the reliability issues of circuits. This paper presents two highly reliable RHBD 10T and 12T SRAM cells, which can protect against single-node upsets (SNUs) and double-node upsets (DNUs). The 10T cell mainly consists of two cross-coupled input-split inverters and the cell can robustly keep stored values through a feedback mechanism among its internal nodes. It also has a low cost in terms of area and power consumption, since it uses only a few transistors. Based on the 10T cell, a 12T cell is proposed that uses four parallel access transistors. The 12T cell has a reduced read/write access time with the same soft error tolerance when compared to the 10T cell. Simulation results demonstrate that the proposed cells can recover from SNUs and a part of DNUs. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed 10T cell can save 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

DOI： 10.1145/3526241.3530312

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Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications 査読有り国際誌

Yan A., Chen Y., Song S., Zhai Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 333 - 338 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel sextuple cross-coupled dual-interlocked-storage-cell (DICE) based double-node-upset (DNU) recoverable and low-delay flip-flop (FF), namely SCDRL-FF, for aerospace applications. The SCDRL-FF mainly consists of sextuple cross-coupled DICEs controlled by clock-gating. The use of clock-gating based DICEs significantly reduces the CLK-Q transmission delay of the SCDRL-FF. Through the redundant and interlocked clock-gating based DICEs, the SCDRL-FF can provide complete DNU recoverability. Simulation results demonstrate the DNU recoverability of the SCDRL-FF and a 65% delay reduction on average compared with the state-of-the-art hardened FFs. The low delay overhead makes the proposed SCDRL-FF effectively applicable to high-performance applications and the DNU recoverability makes the proposed SCDRL-FF also suitable for aerospace applications.

DOI： 10.1145/3526241.3530355

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A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center 査読有り国際誌

Saxena D., Gupta I., Kumar J., Singh A.K., Wen X.

IEEE Systems Journal 16 ( 2 ) 3163 - 3174 2022年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

To facilitate cost-effective and elastic computing benefits to the cloud users, the energy-efficient and secure allocation of virtual machines (VMs) plays a significant role at the data center. The inefficient VM placement (VMP) and sharing of common physical machines among multiple users leads to resource wastage, excessive power consumption, increased intercommunication cost, and security breaches. To address the aforementioned challenges, a novel secure and multiobjective VMP (SM-VMP) framework is proposed with an efficient VM migration. The proposed framework ensures an energy-efficient distribution of physical resources among VMs, which emphasizes secure and timely execution of user application by reducing intercommunication delay. The VMP is carried out by applying the proposed Whale Optimization Genetic Algorithm (WOGA), inspired by whale evolutionary optimization and nondominated sorting based genetic algorithms. The performance evaluation for static and dynamic VMP and comparison with recent state of the arts observed a notable reduction in shared servers, intercommunication cost, power consumption, and execution time up to 28.81%, 25.7%, 35.9%, and 82.21%, respectively with increased resource utilization up to 30.21%.

DOI： 10.1109/JSYST.2021.3092521

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Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications 査読有り国際誌

Yan A., Xiang J., Cao A., He Z., Cui J., Ni T., Huang Z., Wen X., Girard P.

IEEE Transactions on Device and Materials Reliability 22 ( 2 ) 282 - 295 2022年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead.

DOI： 10.1109/TDMR.2022.3175324

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Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications 査読有り国際誌

Yan A., Fan Z., Ding L., Cui J., Huang Z., Wang Q., Zheng H., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 58 ( 1 ) 517 - 529 2022年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this article also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2, 32.8, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called high-impedance state-insensitive, TNU-tolerant, and SET-filterable latch can reduce delay, power, and area by 78.9, 15.8, and 28.6%, respectively, compared with the state-of-the-art TNU hardened latch.

DOI： 10.1109/TAES.2021.3103586

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A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications 査読有り国際誌

Yan A., Qian K., Cui J., Cui N., Huang Z., Wen X., Girard P.

Proceedings of the IEEE VLSI Test Symposium 2022-April 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In space, the impact of radiative particles, such as neutrons and heavy ions, can change the node states of a flip-flop, thus resulting in loss of data. In this paper, a Highly reliable and Low power Radiation-hardened-by-design (RHBD) Flip-Flop cell, namely HLRFF, completely hardened against double-node-upsets (DNUs), is proposed for aerospace applications. The HLRFF is a master-slave structure. The master latch is mainly constructed from two 2-input C-elements (CEs) and one 2-input clock-gating based CE, while the slave latch has an additional keeper at the output stage. The verification results demonstrate that the proposed HLRFF is completely DNU-tolerant. Furthermore, compared to the state-of-the-art radiation-hardened FF cells, the proposed HLRFF can reduce power consumption by approximately 69%. However, only the proposed HLRFF is not only completely DNU-tolerant but also insensitive to high-impedance-state.

DOI： 10.1109/VTS52500.2021.9794197

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SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Huang S., Zhai Z., Cheng X., Cui J., Ni T., Wen X., Girard P.

Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 1257 - 1262 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the CMOS technology is continuously scaling down, nano-scale integrated circuits are becoming susceptible to harsh-radiation induced soft errors, such as double-node upsets (DNUs) and triple-node upsets (TNUs). This paper presents a shuttle C-elements based low-cost and robust latch (namely SCLCRL) that can recover from any TNU in harsh radiation environments. The latch comprises seven primary storage nodes and seven secondary storage nodes. Each pair of primary nodes feeds a secondary node through one C-element (CE) and each pair of secondary nodes feeds a primary node through another CE, forming redundant feedback loops to robustly retain values. Simulation results validate all key TNUs' recoverability features of the proposed latch. Simulation results also demonstrate that the proposed SCLCRL latch can approximately save 29% silicon area and 47% D-Q delay on average at the cost of moderate power, compared with the state-of-the-art TNU-recoverable reference latches of the same-type.

DOI： 10.23919/DATE54114.2022.9774665

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Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments 査読有り国際誌

Yan A., Xu Z., Feng X., Cui J., Chen Z., Ni T., Huang Z., Girard P., Wen X.

IEEE Transactions on Emerging Topics in Computing 10 ( 1 ) 404 - 413 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.

DOI： 10.1109/TETC.2020.3025584

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Broadcast-TDMA: A Cost-Effective Fault Tolerance Method for TSV Lifetime Reliability Enhancement 査読有り国際誌

Ni T., Bian J., Yang Z., Nie M., Yao L., Huang Z., Yan A., Wen X.

IEEE Design and Test 39 ( 5 ) 34 - 42 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Electromigration and time-dependent dielectric breakdown induced through-silicon-via (TSV) aging, along with TSV thermal issues including thermo-mechanical stress and thermal cycling, may result in failure and affect the lifetime reliability of TSV. This paper proposes a cost-effective fault tolerance method for TSV lifetime reliability enhancement. In a honeycomb TSV group formed by six TSVs without the utilization of redundant TSVs, any faulty TSV can be bypassed and broadcasted to any other TSVs in the same group. The cost-effectiveness of the proposed fault tolerance method has been evaluated based on the IWLS’05 3D benchmark circuits using 45nm open cell library. Experimental results show that the proposed method has the highest lifetime reliability compared with state-of-art router-based, ring-based, and chain-TDMA based solutions for lifetime reliability enhancement, and the lifetime reliability of the proposed scheme can still remain more than 90% even at 10 years. Furthermore, compared with the methods mentioned above, the proposed method can achieve 34.05%~58.56%, 29.46%~55.55%, 4.75%~39.84% reductions in hardware overhead, respectively. All these promising attributes can facilitate this proposed architecture’s adoption in 3D IC designs.

DOI： 10.1109/MDAT.2022.3189827

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Power-Aware Testing in the Era of IoT 査読有り国際誌

Wen X.

Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022 2022年01月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

IoT devices are increasingly employed in various applications. Due to their intrinsic power supply limitation, IoT devices are usually designed with extremely low functional power dissipation. However, the testing of IoT devices has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper highlights the impact of excessive scan test power and points out the importance of power-aware testing for IoT devices.

DOI： 10.1109/ICSICT55466.2022.9963241

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Power and Energy Safe Real-Time Multi-Core Task Scheduling 査読有り国際誌

Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 16 - 21 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scheduling tasks in multi-core real-time systems (e.g. low power devices/appliances) while keeping energy in mind is a difficult design challenge. Extensive work has been done to overcome this issue, in which task instances (jobs) have varying levels of operation power. Different combinations of system energy (SE) and subsequent minimal SE have been attained based on the power levels. However, both system power (SP) and system energy (SE) are expensive to operate. As a result, task scheduling for multi-core systems based on balancing both the SP and the SE (referred to as feasible SP and feasible SE, respectively) to achieve the lowest system cost is an issue that has not been adequately addressed in the literature. The states or zones of feasible SP (FSP) and feasible SE (FSE) are thought to be possible zones/states of the system where the system's power configuration provides lowered SE with increased job accommodation, lowering the system's cost. We offer a unique scheduling approach in which we identify numerous FSP and FSE zones (feasible zones/states) to fit all jobs to cores while minimising system cost (including optimum cost) and meeting deadlines. By giving weights to the FSP and FSE, we present a mechanism for ranking the many viable system states. The model is tested using produced task sets (low power task sets), and the results reveal that our approach effectively finds feasible zones, including the best one.

DOI： 10.1109/VLSID2022.2022.00016

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Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits 査読有り国際誌

Utsunomiya T., Hoshino R., Miyase K., Lu S.K., Wen X., Kajihara S.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 43 - 48 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

High power consumption in LSI testing may cause excessive IR-drop. When IR-drop becomes excessive, it causes excessive delay, resulting in test malfunction (over-testing). Excessive IR-drop does not occur in the entire area of a circuit, but in certain areas where a large number of switching activities occur (such areas are called hotspots in this work). In order to avoid test malfunction, it is important to develop a method to reduce or control IR-drop in the hotspots. Locating hotspots is a necessary technique to reduce or control IR-drop effectively and efficiently. In this work, we propose a method to locate hotspots in a logic circuit by switching probability calculation. Experimental results for IWLS2005 OpenCores circuits demonstrate the proposed method can support to locate hotspots.

DOI： 10.1109/ITCAsia55616.2022.00018

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Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS 査読有り国際誌

Yan A., Song S., Zhang J., Cui J., Huang Z., Ni T., Wen X., Girard P.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 73 - 78 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the aggressive reduction of CMOS transistor feature sizes, the soft error rate of nano-scale integrated circuits increases exponentially. In this paper, we propose a novel cost-optimized and robust latch, namely CRLHQ, hardened against quadruple-node-upsets (QNUs) for nanoscale CMOS technologies. The latch mainly comprises a 5×5 matrix based on interlocked source-drain cross-coupled inverters to robustly store logic values. Owing to the redundant constructed feedback loops, the latch can recover from all possible QNUs. Simulation results demonstrate all key QNUs' recovery of the proposed CRLHQ latch. Simulation results also show that the proposed latch can approximately reduce the D-Q delay by 44.3%, the silicon area by 7.3% and the delay-area-power product (DAPP) by 14.2%, compared with the state-of-the-art same-type reference latches that can recover from any QNU.

DOI： 10.1109/ITCAsia55616.2022.00023

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A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters 査読有り国際誌

Yan A., Song S., Chen Y., Cui J., Huang Z., Wen X.

Proceedings of the IEEE Conference on Nanotechnology 2022-July 215 - 218 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel low-cost and robust latch, namely LRLPT, protected against triple-node upsets (TNUs) in nano-scale CMOS. The storage part of the latch comprises interlocked source-drain cross-coupled inverters forming redundant feedback loops to robustly store values. Simulation results demonstrate all key TNUs' recovery of the proposed latch. Simulation results also demonstrate that the proposed latch can save 69.67% delay, 37.51% silicon area and 71.77% delay-area-power product (DAPP) compared to the state-of-the-art TNU-recovery reference latch of the same-type.

DOI： 10.1109/NANO54668.2022.9928674

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A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC 査読有り国際誌

Ni T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40 ( 9 ) 1952 - 1956 2021年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%-99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%-86.85% (46.01%-55.96%), 66.89%-73.25% (29.41%-38.49%), 68.02%-74.20% (41.40%-52.20%), 60.60%-68.18% (18.09%-33.18%), and 75.86%-80.52% (3.05%-20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay.

DOI： 10.1109/TCAD.2020.3025169

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Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications 査読有り国際誌

Yan A., Cao A., Xu Z., Cui J., Ni T., Girard P., Wen X.

Journal of Electronic Testing: Theory and Applications (JETTA) 37 ( 4 ) 489 - 502 2021年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

DOI： 10.1007/s10836-021-05962-0

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A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments 査読有り

Yan A., Cao A., Fan Z., Xu Z., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 301 - 306 2021年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state (HIS) insensitive latch design, namely QRHIL, for highly robust computing in harsh radiation environments. The latch mainly comprises a 5×5 looped C-element matrix to store values and provide complete 4NU recovery. Owing to the multiple-level error-interception of the 5×5 C-element matrix, the latch can recover from all possible 4NUs; thus, the latch is insensitive to HIS. Simulation results demonstrate the 4NU-recovery of the proposed latch. The results also show that the latch can approximately save 46% D-Q delay and 46% CLK-Q delay owing to the use of a high-speed D-Q path and clock-gating, compared with the state-of-the-art 3NU-recoverable latch (TNURL) that is not 4NU-recoverable.

DOI： 10.1145/3453688.3461493

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Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications 査読有り

Yan A., He Z., Zhou J., Cui J., Ni T., Huang Z., Wen X., Girard P.

Microelectronics Journal 111 2021年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

DOI： 10.1016/j.mejo.2021.105034

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A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology 査読有り

Ni T., Yang Z., Chang H., Zhang X., Lu L., Yan A., Huang Z., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 2 ) 724 - 734 2021年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

Through-silicon-vias (TSVs) are prone to defects during the manufacturing process, which pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is too great to be ignored, and in order to not use any redundant TSVs, a chain-type time division multiplexing access (TDMA)-based fault tolerance technique is proposed. However, a double-TSV structure is used per group, resulting in a significant TSV hardware overhead under a given large-scaled circuit design. Furthermore, it is impossible for the chain-TDMA scheme to plan the rerouting path for the right-hand-most TSV per group, resulting in a decrease in the repair rate per TSV group as well as in the whole TSV yield. In the proposed technique, we bundle six TSVs per group in a honeycomb pattern and the TSVs on the edges are connected to each other, enhancing the repair rate per group as well as the whole TSV yield. Subsequently, an architecture based on the proposed technique is designed, evaluated, and validated on logic-on-logic 3D IWLS'05 benchmark circuits using 45 nm TSMC technology. The proposed technique is found to reduce the area overhead by 87.95-90.42 percent, compared to the chain-TDMA scheme, which results in a yield of 96.90-99.09 percent.

DOI： 10.1109/TETC.2020.2969237

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Reliability-Driven Neuromorphic Computing Systems Design 査読有り

Xu Q., Wang J., Geng H., Chen S., Wen X.

Proceedings -Design, Automation and Test in Europe, DATE 2021-February 1586 - 1591 2021年02月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have provided a promising solution to the acceleration of neural networks. However, stuck-at faults (SAFs) in the memristor devices significantly degrade the computing accuracy of NCS. Besides, memristors suffer from process variations, causing the deviation of actual programming resistance from its target resistance. In this paper, we propose a novel reliability-driven design framework for a memristive crossbar-based NCS in combination with general and chip-specific design optimizations. First, we design a general reliability-aware training scheme to enhance the robustness of NCS to SAFs and device variations; a dropout-inspired approach is developed to alleviate the impact of SAFs; a new weighted error function, including cross-entropy error (CEE), the l2-norm of weights, and the sum of squares of first-order derivatives of CEE with respect to weights, is proposed to obtain a smooth error curve, where the effects of variations are suppressed. Second, given the neural network model generated by the reliability-aware training scheme, we exploit chip-specific mapping and retraining to further reduce the computation accuracy loss incurred by SAFs. Experimental results clearly demonstrate that the proposed method can boost the computation accuracy of NCS and improve the NCS robustness.

DOI： 10.23919/DATE51398.2021.9473929

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Preface 査読有り国際誌

Wen X., Liou J.J.

Journal of Physics Conference Series 1729 ( 1 ) 2021年01月

Cellular Structure Based Fault-Tolerance TSV Configuration in 3D-IC 査読有り国際誌

Xu Q., Sun W., Chen S., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 5 ) 1196 - 1208 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement. But the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this paper, we propose an effective TSV repair strategy for the cellular TSV redundancy architecture, with taking account of the delay overhead. First, we prove that the cellular structure-based fault-tolerance TSV configuration with the delay constraint (CSFTC) is equivalent to the length-bounded multi-commodity flow (LBMCF) problem. Next, an integer linear programming formulation is presented to solve the LBMCF problem. Finally, to speed-up the fault-tolerance structure configuration process, an efficient Lagrangian relaxation based heuristic method is further proposed. Experimental results demonstrate that, compared with the state-of-the-art fault-tolerance structures, the proposed method can provide high yield and low delay overhead.

DOI： 10.1109/TCAD.2021.3084920

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Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS 査読有り

Yan A., Lai C., Zhang Y., Cui J., Huang Z., Song J., Guo J., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 1 ) 520 - 533 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39 percent and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

DOI： 10.1109/TETC.2018.2871861

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TPDICE and SIM based 4-node-upset completely hardened latch design for highly robust computing in harsh radiation 査読有り

Yan A., Ding L., Shan C., Cai H., Chen X., Wei Z., Huang Z., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2021-May 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Technology scaling and charge-sharing make nano-scale CMOS latches become severely vulnerable to multiple-node upsets (MNUs). This paper proposes a triple-path dual-interlocked-storage-cell (TPDICE) and soft-error interceptive module (SIM) based 4-Node-Upset (4NU) completely hardened latch, namely 4NUHL latch, that can completely tolerate soft errors, such as 4NUs. The latch mainly consists of 2 TPDICEs and a 3-level SIM which comprises six 2-input C-elements. Owing to the single-node-upset self-recoverability and multiple storage nodes of TPDICEs and the soft-error interception capability of the SIM, the latch can provide complete 4NU tolerance. Simulation results demonstrate that the proposed 4NUHL latch is completely 4NU hardened. Furthermore, we use a high-speed path, clock-gating, and a few transistors to reduce overhead of the proposed latch. We compared the proposed latch with state-of-the-art hardened latches in terms of reliability and overhead to demonstrate the advantages of the proposed latch.

DOI： 10.1109/ISCAS51556.2021.9401453

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On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption 査読有り国際誌

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E104D ( 6 ) 816 - 827 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

DOI： 10.1587/transinf.2020EDP7042

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Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing 査読有り国際誌

Yan A., Zhai Z., Wang L., Zhang J., Cui N., Ni T., Wen X.

Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of design and manufacturing technologies of nano-scale CMOS circuits, latches are becoming increasingly sensitive to multiple-node-upsets caused by harsh radiation effects. In this paper, a Parallel Dual-interlocked-storage-cells (DICEs) and Dual-level C-elements (CEs) based 3-node-upset (3NU)-Tolerant Latch, namely PDDCTL, design for highly robust computing, is proposed. The latch comprises five transmission gates, two DICEs and three CEs. Due to the use of two single-node-upset self-recoverable DICEs and three error-interceptive CEs, the latch can provide complete 3NU-tolerance with low cost. Simulation results not only confirm the 3NU-tolerance of the proposed latch but also demonstrate that the delay-power-area product of the PDDCTL latch is reduced by 68.82% on average compared with the state-of-the-art 3NU hardened latch designs.

DOI： 10.1109/ITC-Asia53059.2021.9808602

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LSI Testing: A Core Technology to a Successful LSI Industry 招待有り査読有り国際誌

Wen X.

Proceedings of International Conference on ASIC 2021年01月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Despite its ever-growing importance in all innovation fields, such as automotive and IoT applications, the LSI industry is fragile due to its a weak technology-business chain. In addition, its products, namely LSI chips, are vulnerable to six risks (defective chip escape, radiation, aging, malicious attack, counterfeiting). LSI testing is the technology that is indispensable to mitigate these risks. This paper highlights the intent of LSI testing as well as its impact on the LSI industry.

DOI： 10.1109/ASICON52560.2021.9620418

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GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning 査読有り国際誌

Xu Q., Geng H., Chen S., Yuan B., Zhuo C., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3492 - 3502 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Electronic Design Automation (EDA) comprises a series of computationally difficult optimization problems that require substantial specialized knowledge as well as a considerable amount of trial-and-error efforts. However, open challenges including long simulation runtime and lack of generalization continue to restrict the applications of existing EDA tools. Recently, learning-based algorithms especially reinforcement learning (RL) have been successfully applied to handle various combinatorial optimization problems by automatically acquiring knowledge from the past experience. In this paper, we formulate the floorplanning problem, the first stage of the physical design flow, as a Markov Decision Process (MDP). An end-toend learning-based floorplanning framework GoodFloorplan is proposed to explore the design space, which combines graph convolutional network (GCN) and RL. Experimental results demonstrate that, compared with state-of-the-art heuristic-based floorplanners, the proposed GoodFloorplan can provide better area and wirelength.

DOI： 10.1109/TCAD.2021.3131550

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Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure 査読有り国際誌

Xu Q., Ni T., Geng H., Chen S., Yu B., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3182 - 3187 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this paper, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration with the delay constraint (RFSC) is equivalent to the length-bounded multi-commodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. Experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead.

DOI： 10.1109/TCAD.2021.3133484

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A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch 査読有り国際誌

Yan A., Qian K., Cui J., Cui N., Ni T., Huang Z., Wen X.

2021 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As transistor feature sizes continue to scale down, the susceptibility of integrated circuits to harsh-radiation induced multiple-node-upsets (MNUs),such as double-node upsets (DNUs) and triple-node upsets (TNUs), is increasing. This paper presents an MNU self-recoverable hardened latch (namely SCDMSH) based on sextuple cross-coupled dual-interlocked-storage-cells (DICEs). The latch consists of eight transmission gates and six interlocked DICE cells. Due to the interlocking mechanism constructed from single-node-upset-self-recoverable DICE cells, the latch can self-recover from any possible single node upset (SNU), DNU and TNU. Simulation results validate the SNU, DNU and TNU self-recoverability of the proposed latch. Simulation results also demonstrate that the SCDMSH latch can approximately save 49% silicon area at the cost of moderate delay and power, compared with the state-of-the-art TNU self-recoverable reference latch (TNURL) of the same-type.

DOI： 10.1109/NANOARCH53687.2021.9642250

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A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets 査読有り国際誌

Yan A., Cao A., Qian K., Ding L., He Z., Fan Z., Wen X.

Proceedings - 2021 8th International Conference on Dependable Systems and Their Applications, DSA 2021 734 - 736 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a flip-flop (FF) that can tolerate double-node-upsets (DNUs). If the FF suffers from a DNU, it can still have a correct value on its output node. Simulation results demonstrate the FF's DNU tolerance, and also demonstrate that the proposed FF can save 92% delay, 55% power, and 28% area on average, compared to typical DNU hardened FFs, respectively.

DOI： 10.1109/DSA52907.2021.00108

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Novel Speed-and-Power-Optimized SRAM Cell Designs with Enhanced Self-Recoverability from Single- And Double-Node Upsets 査読有り国際誌

Yan A., Chen Y., Hu Y., Zhou J., Ni T., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 12 ) 4684 - 4695 2020年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

The continuous advancement of CMOS technologies makes SRAMs more and more sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-node upsets (DNUs). First, the S4P8N cell that has more redundant nodes and more access transistors is proposed. The cell has the following advantages: (1) it can self-recover from all possible SNUs; (2) it can self-recover from a part of DNUs; (3) it has small overhead in terms of power dissipation. Then, to reduce read and write access time, the S8P4N cell that uses a special feedback mechanism among its internal nodes is proposed. The cell has similar soft error tolerability as the S4P8N cell. Simulation results validate the high robustness of the proposed SRAM cells. These results also show that the write access time, read access time, and power dissipation of the S8P4N cell are reduced approximately by 29%, 20%, and 21% on average, at the cost of moderate silicon area, when compared with the state-of-the-art radiation-hardened SRAM cells.

DOI： 10.1109/TCSI.2020.3018328

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A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets 査読有り

Yan A., Chen Y., Zhou J., Cui J., Ni T., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2020-November 2020年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can provide self-recoverability from any single-node upsets (SNUs) and partial double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of six access transistors. Simulation results show that the SCCS18T cell can save approximately 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with typical hardened SRAM cells.

DOI： 10.1109/ATS49688.2020.9301569

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Logic Fault Diagnosis of Hidden Delay Defects 査読有り

Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

Proceedings - International Test Conference 2020-November 2020年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

DOI： 10.1109/ITC44778.2020.9325234

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Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC 査読有り国際誌

Ni T., Chang H., Song T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 67 ( 11 ) 2657 - 2661 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In this brief, a non-invasive online solution for 2.5D IC based on distributed pulse shrinking is proposed to test the faults of interconnects. Furthermore, a regression model based on artificial neural network (ANN) is proposed in order to judge whether the interconnects are faulty and quantify the degree of the faults in real time by online monitoring the delay of interconnects. Experiments on defect detection are presented through HSPICE simulation with realistic models for 45nm CMOS technology. The results show that the proposed method has features including: high resolution, low area overhead, high robustness, and be able to predict the class and the fault size.

DOI： 10.1109/TCSII.2019.2962824

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Design of double-upset recoverable and transient-pulse filterable latches for low-power and low-orbit aerospace applications 査読有り

Yan A., Chen Y., Xu Z., Chen Z., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 5 ) 3931 - 3940 2020年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a singleevent Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhancedversion of theDURTPF latch, namelyDURTPF-EV.TheDURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost ofmoderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.

DOI： 10.1109/TAES.2020.2982341

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Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors 査読有り

Dou Z., Yan A., Zhou J., Hu Y., Chen Y., Ni T., Cui J., Girard P., Wen X.

Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 35 - 40 2020年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

DOI： 10.1109/ITC-Asia51099.2020.00018

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A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications 査読有り

Yan A., Xu Z., Yang K., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 4 ) 2666 - 2676 2020年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node upsets (TNUs) are becoming more and more an issue in storage cells used for applications constrained by their environment, such as aerospace applications confronted to radiations. This article presents a novel triple-modular redundancy without voter based high-impedance state (HIS) insensitive and MNU-tolerant latch design, namely TMHIMNT, to ensure both high reliability and low cost. The TMHIMNT latch mainly comprises triple clock-gating (CG) based dual-interlocked-storage-cells (DICEs) and four inverters. Through three internal inverters, the values stored in DICEs converge to a common node feeding an output-level inverter, enabling the TMHIMNT latch to tolerate any possible MNU. Simulation results demonstrate the MNU tolerance of the proposed TMHIMNT latch. Due to the disuse of C-elements, the proposed TMHIMNT latch is insensitive to the HIS, making the latch more reliable for aerospace applications. Moreover, compared with the state-of-the-art TNU hardened latch, due to the use of a high-speed path, CG technologies, and fewer transistors, the proposed TMHIMNT latch can achieve 98% delay, 17% power, and 29% area reductions, respectively.

DOI： 10.1109/TAES.2019.2951186

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HITTSFL: Design of a cost-effective HIS-Insensitive TNU-Tolerant and SET-Filterable latch for safety-critical applications 査読有り

Yan A., Feng X., Zhao X., Zhou H., Cui J., Ying Z., Girard P., Wen X.

Proceedings - Design Automation Conference 2020-July 2020年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a cost-effective, high-impedance-state (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storage-cells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-the-art TNU hardened latch (TNUHL) that cannot filter SETs.

DOI： 10.1109/DAC18072.2020.9218704

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Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment 査読有り

Yan A., Hu Y., Cui J., Chen Z., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computers 69 ( 6 ) 789 - 799 2020年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

DOI： 10.1109/TC.2020.2966200

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Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments 査読有り

Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 2 ) 1163 - 1171 2020年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

In harsh radiation environments, nanoscale CMOS latches have become more and more vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm CMOS technology. The proposed latch is mainly constructed from seven mutually feeding-back soft-error-interceptive modules (SIMs), any of which consists of two three-input C-elements and one two-input C-element. Due to the mutual feedback mechanism of SIMs and the dual-level soft-error interception of each SIM, the latch can self-recover from any possible TNU. Simulation results demonstrate the TNU self-recoverability from any key TNU for the proposed latch using redundant silicon area. Furthermore, using a high-speed path, the proposed latch saves about 95.45% transmission delay and 86.97% delay-power-area product, compared with the state-of-the-art TNU-tolerant latch that cannot provide complete TNU self-recoverability at all.

DOI： 10.1109/TAES.2019.2925448

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Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs 査読有り国際誌

Yan A., Ling Y., Cui J., Chen Z., Huang Z., Song J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 3 ) 879 - 890 2020年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

DOI： 10.1109/TCSI.2019.2959007

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Dual-interlocked-storage-cell-based double-node-upset self-recoverable flip-flop design for safety-critical applications 査読有り

Yan A., Xu Z., Cui J., Ying Z., Huang Z., Liang H., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2020-October 2020年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a novel dual-interlocked storage-cell (DICE)-based double-node-upset (DNU) self-recoverable, namely DURI-FF, in the nano-scale CMOS technology. The master latch of the DURI-FF cell consists of three transmission gates (TGs) and three interlocked DICEs with three common nodes. The common nodes are connected to TGs for value initialization. The slave latch of the DURI-FF cell comprises six TGs, six inverters and three interlocked DICEs. The outputs of the inverters respectively feed the internal nodes of the slave latch. The interlocked DICEs make the master latch and the slave latch DNU self-recoverable. Simulation results validate the DNU self-recoverability of the proposed DURI-FF cell. Moreover, compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.

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Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications 査読有り

Yan A., Wu Z., Zhou J., Hu Y., Chen Y., Ying Z., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2019-December 55 - 60 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The Aggressive technology scaling makes modern advanced SRAMs more and more sensitive to soft errors that include single-node upsets (SNUs) and double-node upsets (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs. The cell mainly consists of six cross-coupled input-split inverters, constructing a large error-interceptive feedback loop to robustly retain stored values. Since the cell has many redundant storage nodes, the cell achieves the following robustness: (1) the cell can self-recover from all possible SNU; (2) the cell can self-recover from partial DNUs; (3) the cell can avoid the occurrence of other DNUs due to node-separation. Simulation results validate the excellent robustness of the proposed cell. Moreover, compared with the state-of-the-art typical existing hardened cells, the proposed cell achieves an approximate 61% read access time as well as 12% write access time reduction at the costs of 47% power dissipation as well as 44% silicon area on average.

DOI： 10.1109/ATS47505.2019.00006

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Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications 査読有り

Yan A., Wu Z., Lu L., Chen Z., Song J., Ying Z., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2019-December 43 - 48 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.

DOI： 10.1109/ATS47505.2019.000-2

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Targeted partial-shift for mitigating shift switching activity hot-spots during scan test 査読有り

Holst S., Shi S., Wen X.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2019-December 124 - 129 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

DOI： 10.1109/PRDC47002.2019.00042

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Variation-aware small delay fault diagnosis on compressed test responses 査読有り

Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings - International Test Conference 2019-November 2019年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

DOI： 10.1109/ITC44170.2019.9000143

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A fault-tolerant MPSoC for CubeSats 査読有り国際誌

Fuchs C., Chou P., Wen X., Murillo N., Furano G., Holst S., Tavoularis A., Lu S., Plaat A., Marinis K.

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 2019年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

DOI： 10.1109/DFT.2019.8875417

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A static method for analyzing hotspot distribution on the LSI 査読有り

Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 73 - 78 2019年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Performance degradation caused by high IR-drop in normal functional mode of LSI can be avoided by improving the power supply network in the layout design phase. However, while IR-drop increases much more in test mode than in normal functional mode, excessive IR-drop in test mode is not appropriately considered in the layout design phase. Excessive IR-drop in test mode causes over-testing, which wrongly determines a fault free LSI in normal functional mode to be faulty. In this work, we propose a method for analyzing high IR-drop areas (hotspot distribution), which is necessary to effectively and efficiently reduce excessive IR-drop.

DOI： 10.1109/ITC-Asia.2019.00026

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A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells 査読有り国際誌

Song Z., Yan A., Cui J., Chen Z., Li X., Wen X., Lai C., Huang Z., Liang H.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 139 - 144 2019年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81% for the proposed latch compared with the only existing SETU hardened latch.

DOI： 10.1109/ITC-Asia.2019.00037

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Power-Aware Testing for Low-Power VLSI Circuits 招待有り査読有り国際誌

X. Wen

15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits Paper S12-1 2019年06月

Small Delay Fault Diagnosis with Compacted Responses 査読有り国際誌

S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich

Poster at ACM Design Automation Conf. 2019年06月

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications 査読有り国際誌

Yan A., Hu Y., Song J., Wen X.

Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 1679 - 1684 2019年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 EDAA. This paper presents a single-event double-upset (SEDU) self-recoverable and single-event transient (SET) pulse filterable latch design for low power applications in 22nm CMOS technology. The latch mainly consists of eight mutually feeding back C-elements and a Schmitt trigger. Simulation results have demonstrated both the SEDU self-recoverability and SET pulse filterability for the latch using redundant silicon area. Using clock gating technology, the latch saves about 54.85% power dissipation on average compared with the up-to-date SEDU self-recoverable latch designs which are not SET pulse filterable at all.

DOI： 10.23919/DATE.2019.8714841

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STAHL: A novel scan-test-aware hardened latch design 査読有り国際誌

Ma R., Holst S., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2019-May 2019年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulner-ability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode.

DOI： 10.1109/ETS.2019.8791544

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Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout 査読有り国際誌

Yan A., Wu Z., Guo J., Song J., Wen X.

IEEE Transactions on Reliability 68 ( 1 ) 354 - 363 2019年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2018 IEEE. This paper presents two novel memory cell designs that can completely tolerate double-node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant storage nodes, the cell achieves the following robustness: 1) In the case of 1 being stored, the cell can self-recover from any double-node upset (DNU) as well as any single node upset (SNU); 2) in the case of 0 being stored, the cell can self-recover from any double-adjacent-node upset (DANU), partial double-separated-node upset (DSNU) as well as any SNU. Any other DSNU can be tolerated by the cell due to the use of the layout approach. Second, a layout-independent cell is proposed that can self-recover from any DNU as well as any SNU. Simulation results validate the robustness of the proposed cell designs. Furthermore, compared with typical existing radiation hardened memory cells, the proposed layout-dependent cell saves 55.60% read access time and 33.76% write access time at the costs of 4.28% power dissipation and 39.01% silicon area on average, still low compared with layout-independent cell designs.

DOI： 10.1109/TR.2018.2876243

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Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory 査読有り国際誌

Alioto M., Abadir M.S., Arslan T., Boon C.C., Burg A., Chang C.H., Chang M.F., Chang Y.W., Chen P., Corsonello P., Crovetti P., Dosho S., Drechsler R., Elfadel I.A.M., Han R., Hashimoto M., Heng C.H., Heo D., Ho T.Y., Homayoun H., Hwang Y.S., Joshi A., Joshi R.V., Karnik T., Kim C., Kim T.H.T., Kulkarni J., Kursun V., Lee Y., Li H.H., Li H., Mishra P., Mohammad B., Kermani M.M., Nagata M., Nii K., Pande P.P., Paul B.C., Pavlidis V.F., De Gyvez J.P., Savidis I., Schaumont P., Sebastiano F., Sengupta A., Seok M., Stan M.R., Tehranipoor M.M., Todri-Sanial A., Verhelst M., Vignoli V., Wen X., Xu J., Zhang W., Zhang Z., Zhou J., Zwolinski M., Weber S.

IEEE Transactions on Very Large Scale Integration VLSI Systems 27 ( 2 ) 253 - 280 2019年02月

記述言語：英語掲載種別：記事・総説・解説・論説等（学術雑誌）

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades [1] (see Fig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown in Fig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade [2], [3]. At the same time, the energy per task has been decreasing at 10-100 X/decade, as shown in Fig. 2, for several systems and system-on-chip subsystems [4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit [5].

DOI： 10.1109/TVLSI.2018.2886389

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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults 査読有り国際誌

Ni T., Yao Y., Chang H., Lu L., Liang H., Yan A., Huang Z., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 ( 10 ) 2938 - 2951 2019年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

IEEE Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the FTSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3D-ICs. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based RTSV architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this paper, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.

DOI： 10.1109/TCAD.2019.2946243

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Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets 査読有り

Yan A., Zhou J., Hu Y., Cui J., Huang Z., Girard P., Wen X.

IEEE Access 7 176188 - 176196 2019年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

DOI： 10.1109/ACCESS.2019.2958109

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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing 査読有り国際誌

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. High scan shift power often leads to excessive heat as well as shift timing failures. Partial shift (shifting a subset of scan chains at a time) is a widely adopted approach for avoiding excessive heat by reducing global switching activity, we show for the first time that it may actually cause excessive IR-drop on some clock buffers and worsen shift clock skews, thus increasing the risk of shift timing failures. This paper addresses this problem with an innovative method, namely Clock-Skew-Aware Scan Chain Grouping (CSA-SCG). CSA-SCG properly groups scan chains to be shifted simultaneously so as to reduce the imbalance of switching activity around the clock paths for neighboring scan flip-flops in scan chains. Experiments on large ITC'99 benchmark circuits demonstrate the effectiveness of CSA-SCG for reducing scan shift clock skews to lower the risk of shift timing failures in partial shift.

DOI： 10.1109/ATS.2018.00037

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Message from the Technical Program Co-Chairs 招待有り査読有り国際誌

Li H., Wen X., Huang Z.

Proceedings of the Asian Test Symposium 2018-October 2018年12月

Foreword 査読有り国際誌

Li X., Li H., Cheng K.T.T., Wen X.

Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018 2018年09月

The impact of production defects on the soft-error tolerance of hardened latches 査読有り国際誌

Holst S., Ma R., Wen X.

Proceedings of the European Test Workshop 2018-May 1 - 6 2018年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces the test coverage of cell-internal production defects. Moreover, the test escapes reduce the soft-error tolerance of the defective latches. This work introduces a new soft-error vulnerability metric called Post Test Vulnerability Factor that correctly measures the added vulnerability to transiant frults such as particle strikes caused by undiscovered production defects within hardened latches.

DOI： 10.1109/ETS.2018.8400694

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Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

Proceedings of the 27th International Workshop on Logic and Synthesis 124 - 131 2018年06月

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application 査読有り国際誌

A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

IEEE Transactions on Circuits and Systems II: Express Briefs 66 ( 2 ) 287 - 291 Early Access 2018年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.

DOI： 10.1109/TCSII.2018.2849028

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A Method to Detect Bit Flips in a Soft-Error Resilient TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 ( 6 ) 1185 - 1196 2018年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE. Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors k. KX-TCAM corrects up to k -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers.

DOI： 10.1109/TCAD.2017.2748019

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The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches 査読有り国際誌

S. Holst, R. Ma, X. Wen

Proceedings of IEEE European Test Symposium Paper 7A-1 2018年05月

Design Automation for Legacy Circuits 査読有り国際誌

I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies 174 - 179 2018年03月

Locating Hot Spot with Justification Techniques in a Layout Design 査読有り国際誌

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

Proceedings of IEEE Workshop on RTL and High Level Testing Paper S1.2 2017年11月

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption 査読有り国際誌

Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian

Proceedings of the Asian Test Symposium 140 - 145 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Taiwan Taipei 2017年11月27日 - 2017年11月30日

© 2017 IEEE. Loading and unloading test patterns during scan testing causes many scan flip-flops to trigger simultaneously. This instantaneous switching activity during shift in turn may cause excessive IR-drop that can disrupt the states of some scan flip-flops and corrupt test stimuli or responses. A common design technique to even out these instantaneous power surges is to design multiple scan chains and shift only a group of the scan chains at a same time. This paper introduces a novel algorithm to optimally group scan chains so as to minimize the probability of test data corruption caused by excessive instantaneous IR-drop on scan flip-flops. The experiments show optimal results on all large ITC'99 benchmark circuits.

DOI： 10.1109/ATS.2017.37

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Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors 査読有り国際誌

S. Holst, E. Schneider, H. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen

Proceedings - International Test Conference 2017-December 1 - 8 Paper 3.4 2017年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA Fort Warth 2017年10月29日 - 2017年11月03日

© 2017 IEEE. Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases of test data corruption are mitigated in a non-intrusive way by selective test data manipulation and masking of affected responses. Evaluation results show the computational feasibility of our method for large benchmark circuits, and demonstrate that a few targeted pattern changes provide large potential gains in shift safety and test time with negligible cost in fault coverage.

DOI： 10.1109/TEST.2017.8242055

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A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips 査読有り国際誌

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Transactions on Emerging Topics in Computing 8 ( 3 ) 591 - 601 Early Access 2017年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

DOI： 10.1109/TETC.2017.2767070

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Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs 査読有り国際誌

T. Ni, M. Nie, H. Liang, J. Bian, X. Xu, X. Fang, Z. Huang, X. Wen

IEICE Electronics Express 18 ( 14 ) Letter 20170590 2017年10月

GPU-Accelerated Simulation of Small Delay Faults 査読有り国際誌

E. Schneider, M. Kochte, S. Holst, X. Wen, H. Wunderlich

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 ( 5 ) 829 - 841 2017年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE.Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units (GPUs) with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.

DOI： 10.1109/TCAD.2016.2598560

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On Optimal Power-Aware Path Sensitization 査読有り国際誌

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian

Workshop of Test and Reliability for Circuits and Systems 2017年03月

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding 査読有り国際誌

D. Xiang., X. Wen, L.-T. Wang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 ( 3 ) 942 - 953 2017年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach.

DOI： 10.1109/TVLSI.2016.2606248

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Vernier ring based pre-bond through silicon vias test in 3D ICs 査読有り国際誌

Ni T., Nie M., Liang H., Bian J., Xu X., Fang X., Huang Z., Wen X.

IEICE Electronics Express ( 一般社団法人電子情報通信学会 ) 14 ( 18 ) 20170590 - 20170590 2017年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.

DOI： 10.1587/elex.14.20170590

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Logic-Path-and-Clock-Path-Aware at-Speed Scan Test Generation 査読有り国際誌

F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara

International Symposium on Applied Engineering and Sciences 2016年12月

Logic-path-and-clock-path-aware at-speed scan test generation 査読有り国際誌

Li F., Wen X., Miyase K., Holst S., Kajihara S.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人電子情報通信学会 ) E99A ( 12 ) 2310 - 2319 2016年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power- safety without significant test vector count inflation and test quality loss.

DOI： 10.1587/transfun.E99.A.2310

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A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST 査読有り国際誌

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Asian Test Symposium 203 - 208 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.

DOI： 10.1109/ATS.2016.59

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Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test 査読有り国際誌

S. Eggersglub, S. Holst, D. Tille, K. Miyase, X. Wen

IEEE Asian Test Symposium 173 - 178 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

Launch-Switching-Activity (LSA) is a serious problem during at-speed testing of integrated circuits, since localized LSA may lead to severe IR-drop and thus failures. The excessive LSA is conventionally mitigated by reducing the switching activity through special low-power test generation techniques, typically resulting in severe test pattern inflation and high test costs. This work introduces a novel concept of Low-Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power (HCP) regions. LCP-TPs also help in retaining high test compaction capability. An optimization- SAT based procedure is proposed to compute a small set of optimal LCP-TP locations for compact at-speed test sets with effective capture power reduction. Experimental results clearly demonstrate the advantages of LCP-TP insertion.

DOI： 10.1109/ATS.2016.41

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On Optimal Power-Aware Path Sensitization 査読有り国際誌

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian

IEEE Asian Test Symposium 179 - 184 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

Detailed knowledge of a circuit's timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit's inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls the switching activity in the circuit region surrounding the path. The procedure can maximize or minimize switching activity, or set it to a user-specified value. We study the accuracy-vs.-efficiency trade-offs for a hierarchy of timing models, from coarse zero-delay assumption to a waveformaccurate approach with sub-cycle resolution. For the first time, we present a MaxSAT formulation which guarantees maximization or minimization of switching activity, stemming from transitions and from glitches, simultaneously with path sensitization. We validate the quality of the generated test patterns using a mixed-mode IR-drop-aware timing simulator.

DOI： 10.1109/ATS.2016.63

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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test 査読有り国際誌

S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H. Wunderlich, M. Kochte

IEEE Asian Test Symposium 19 - 24 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.

DOI： 10.1109/ATS.2016.49

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Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures 査読有り国際誌

T. Chen, D. Shen, X. Yi, H. Liang, X. Wen

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E99D ( 11 ) 2672 - 2681 2016年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2016 The Institute of Electronics, Information and Communication Engineers.Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

DOI： 10.1587/transinf.2015EDP7289

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Power-Aware Testing For Low-Power VLSI Circuits 招待有り査読有り国際誌

X. Wen

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings 585 - 588 Paper S37-1 2016年10月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Hangzhou 2016年10月25日 - 2016年10月28日

© 2016 IEEE. Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely heat, false failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research topics in this field will also be discussed.

DOI： 10.1109/ICSICT.2016.7998986

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Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016-September 679 - 684 2016年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA Pittsburgh 2016年07月11日 - 2016年07月13日

© 2016 IEEE.Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys), called κ-TX. κ-TX corrects up to κ-bit flip errors and significantly enhances the tolerance of the TCAM against soft errors, where κ is the maximum number of bit flips in a word of a TCAM. κ-TX consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and an ECC-SRAM. First, κ-TX randomly selects a search key. After that, κ-TX detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and κ-TX refreshes the TCAM words by using a backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of κ-TX outperforms other schemes significantly. Moreover, the hardware overhead of k-TX is small due to the use of only a single TCAM. κ-TX can be easily implemented and is useful for fault-tolerant packet classifiers.

DOI： 10.1109/ISVLSI.2016.77

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SAT-Based Post-Processing for Regional Capture Power Reduction in at-speed scan test generation 査読有り国際誌

S. Eggersgluss, K. Miyase, X. Wen

IEEE European Test Symposium 2016-July 2016年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Netherlands Amsterdam 2016年05月23日 - 2016年05月27日

© 2016 IEEE.With more and more sophisticated low-power design techniques being applied to modern LSI chips for aggressive functional power reduction, the risk of fault-free chips falsely failing production test grows due to excessively high test power compared with functional power. Existing low-power ATPG methods, however, suffer from severe test data inflation and often use unfocused global test power reduction. This paper proposes a novel optimization-SAT-based at-speed scan test generation method that is explicitly targeted at eliminating high-capture-power test vectors in a pre-generated compact test set. This method employs layout information in reducing capture switching activity in a focused regional manner. Experiments demonstrate that the proposed method can effectively eliminate a large number of high-capture-power test vectors with neither test data inflation nor fault coverage loss.

DOI： 10.1109/ETS.2016.7519327

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Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill 査読有り国際誌

D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35 ( 3 ) 499 - 512 2016年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE.At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.

DOI： 10.1109/TCAD.2015.2474365

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Test Pattern Modification for Average IR-Drop Reduction 査読有り国際誌

W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen

IEEE Transactions on VLSI Systems 24 ( 1 ) 38 - 49 2016年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern. We propose a fast average IR drop estimation, which is very close to the time-averaged IR drop of time-consuming transient simulation (R2 =0.99). We calculate the contribution of every node to these nodes inside IR-drop hotspot so that we can effectively modify only a few don't care bits in the test patterns to reduce IR drop. The experimental results show that our technique successively reduces time-averaged IR drop by 10% with almost no fault coverage loss and no test pattern inflation.

DOI： 10.1109/TVLSI.2015.2391291

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Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch 査読有り国際誌

K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian

IEEE Asian Test Symposium 103 - 108 2015年11月

Power Supply Noise and Its Reduction in At-Speed Scan Testing 招待有り査読有り国際誌

X. Wen

IEEE International Conference on ASIC Paper B5-3 2015年11月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Chengdu 2015年11月03日 - 2015年11月06日

Scan testing tends to cause excessive switching activity in an LSI circuit, incurring significant power supply noise with severe impact on its timing. This may lead to over-test or under-test, resulting in test yield loss or low test quality. This paper describes the issue of power supply noise in at-speed scan testing, introduces typical techniques for its reduction, and discusses some important future research topics.

DOI： 10.1109/ASICON.2015.7516980

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A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

24th International Workshop on Logic and Synthesis 2015年06月

Identification of High Power Consuming Areas with Gate Type and Logic Level Information 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE European Test Symposium Paper 9.1 2015年05月

A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE European Test Symposium Poster 2.4 2015年05月

GPU-Accelerated Small Delay Fault Simulation 査読有り国際誌

E. Schneider, S. Holst, M.-A. Kochte, X. Wen, H.-J. Wunderlich

Design and Test in Europe 1174 - 1179 2015年03月

Towards Memory-Aware VLSI Simulation Algorithms for Heterogeneous Architectures 査読有り国際誌

S. Holst, J. Miyazaki, X. Wen

International Symposium on Applied Engineering and Sciences 2014年12月

Soft-Error Tolerant TCAMs for High-Reliability Packet Classification 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE Asia Pacific Conference on Circuits and Systems 471 - 474 2014年11月

Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り国際誌

E. Schneider, S. Holst, X. Wen, H. Wunderlich

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD 17 - 23 2014年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA San Jose 2014年11月02日 - 2014年11月06日

© 2014 IEEE.Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate timesimulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.

DOI： 10.1109/ICCAD.2014.7001324

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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り国際誌

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEICE Transactions on Information and Systems E97 ( 10 ) 2706 - 2718 2014年10月

低キャプチャ電力スキャンテスト生成のためのX埋め込み手法

李富強, 温暁青, 宮瀬紘平, ホルストシュテファン, 梶原誠司

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 ( 一般社団法人電子情報通信学会 ) 114 ( 99 ) 15 - 20 2014年06月

記述言語：英語掲載種別：研究論文（研究会，シンポジウム資料等）

低キャプチャ電力のスキャンテストパターンを生成するため,セルの実効電圧降下(IR-Drop)との関わりの強いローカル信号値遷移量(LSA:Local Switching Activity)を抑えるX埋め込み手法を提案する.この手法では,レイアウトレベルの回路を単位区域に分割した上,各単位区域の遷移量を示すLSAによってテストキューブ中のXビットの優先順位を決めて,伝搬しやすい値を最適論理値として順次Xビットに割り当てる.実験結果によって,提案手法がLSAを効果的に低減できることが示された.

その他リンク： https://ci.nii.ac.jp/naid/110009925706

Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り国際誌

E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

ACM Design Automation Conference Poster 2014年06月

Low-power testing for 2D/3D devices and systems 査読有り国際誌

Lin X., Wen X., Xiang D.

Design of 3D Integrated Circuits and Systems 235 - 277 2014年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2015 by Taylor & Francis Group, LLC. Power dissipation has become a primary concern in large-scale integration (LSI) design [1]. Over the years, LSI designers have been tirelessly developing hardware and software techniques for effectively reducing functional power [2]. Functional constraints are often exploited at various levels to remove wasteful operations so that functional power is reduced. For example, a circuit designed for cell phone applications contains many functional blocks that do not need to be activated simultaneously, e.g., a block for audio and a block for phone calls. Dynamically disabling unnecessary circuit blocks significantly reduces functional power.

DOI： 10.1201/9781315215709

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85054660389&origin=inward

ATPG Enhancement Technology 査読有り国際誌

N.A. Zakaria, M.Z Khalid, X. Wen

IEEE Workshop on RTL and High Level Testing Paper IV.5.S 2013年11月

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り国際誌

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE Asian Test Symposium 19 - 24 2013年11月

Search Space Reduction for Low-Power Test Generation 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE Asian Test Symposium 171 - 176 2013年11月

Test Pattern Modification for Average IR-drop Reduction 査読有り国際誌

J. Li, W-S. Ding, H-Y. Hsieh, X. Wen

IEEE International Test Conference Poster 2013年09月

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing 査読有り国際誌

K. Miyase, R. Sakai, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

IEICE Transaction on Information and Systems E96-D ( 9 ) 2003 - 2011 2013年09月

SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop Paper 4.4 2013年07月

Controllability Analysis of Local Switching Activity for Layout Design 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

Workshop on Design and Test Methodologies for Emerging Technologies Paper 2 2013年05月

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE Design & Test of Computers 30 ( 4 ) 60 - 70 2013年04月

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression 査読有り国際誌

K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, L.-T. Wang

26th International Conference on VLSI Design 279 - 284 2013年01月

Fault Detection with Optimum March Test Algorithm 査読有り国際誌

N. Zakaria, W. Hassan, I. Halin, R. Sidek, X. Wen

Journal of Theoretical and Applied Information Technology 47 ( 1 ) 18 - 27 2013年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a research work aimed to detect previously-undetected faults, either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both in March Algorithm such as MATS++(6N), March C-(10N), March SR(14N), and March CL(12N). The main focus of this research is to improve fault coverage on Single Cell Faults as well as Static Double Cell Faults detection, using specified test algorithm. Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds) and Deceptive Read Destructive Faults (CFdrds) are types of faults mainly used in this research. The experiment result published in [1] shows BIST (Built-In-Self-Test) implementation with the new algorithm. It provides the same test length but with bigger area overhead, we therefore proposed a new 14N March Test Algorithm with fault coverage of more than 95% using solid 0s and 1s Data Background (DB). This paper reveals the design methodology to generate DB covers all memories function by applying non-transition data, transition data, and single read and double read data. The automation hardware was designed to give the flexibility to the user to generate other new March Algorithm prior to the selected algorithm and analyzed the performance in terms of fault detection and power consumption. © 2005 - 2013 JATIT & LLS. All rights reserved.

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Estimation of the Amount of Don't-Care Bits in Test Vectors 査読有り国際誌

K. Miyase, S. Kajihara, X. Wen

IEEE Workshop on RTL and High Level Testing 2012年11月

A Transition Isolation Scan Cell Design for Low Shift and Capture Power 査読有り国際誌

Y.-T. Lin, J.-L Huang, X. Wen

IEEE Asian Test Symposium 107 - 112 2012年11月

On Pinpoint Capture Power Management in At-Speed Scan Test Generation 査読有り国際誌

X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE International Test Conference Paper 6.1 2012年11月

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang

ACM Transactions on Design Automation of Electronic Systems 17 ( 4 ) Article No. 48 2012年10月

A Transition Isolation Scan Cell Design for Low Shift and Capture Power 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop 2012年07月

Power-Aware Testing: The Next Stage 招待有り査読有り国際誌

X. Wen

IEEE European Test Symposium Invited Talk 2012年05月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

France Annecy 2012年05月28日 - 2012年06月01日

Complex power management circuitry in low-power designs and the excessive gap between functional power and test power have made power-aware testing (DFT and test generation) a must. Although significant progress has been made in the past decade, more is still needed in order to achieve test power safety while maximizing test quality and minimizing test cost. This paper highlights the needs for moving to the next-stage of power-aware testing, primarily characterized by a shift of focus from global test power reduction to pinpoint test power management. © 2012 IEEE.

DOI： 10.1109/ETS.2012.6233000

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A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits 査読有り国際誌

K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara

IEEE VLSI Test Symposium 197 - 202 2012年04月

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns 査読有り国際誌

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

ASP Journal of Lower Power Electronics 8 ( 2 ) 248 - 258 2012年04月

Fault Detection with Optimum March Test Algorithm 査読有り国際誌

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE International Conference on Intelligent Systems, Modeling and Simulation Paper S8 2012年02月

Testing static single cell faults using static and dynamic data background 査読有り国際誌

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE Student Conference on Research and Development 1 - 6 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Malaysia Cyberjaya 2011年12月19日 - 2011年12月20日

This work proposes a bit-adjacent Data Background (DB) management scheme to improve fault coverage of March algorithms while simultaneously maintaining the shortest test cycle. Both static and dynamic DB transitions are used in order to detect Deceptive Read Destructive Faults (DRDFs) and Write Disturb Faults (WDFs) that are not detected by previous algorithms. A conventional March Test Algorithm can be modified by using the DB management scheme to form a new March Test Algorithm (referred to as Mod March Test Algorithm), e.g., MATS++(6N) becoming Mod MATS++(6N). This paper shows that Mod March SR (14N) and Mod March CL (12N) can detect DRDFs and WDFs while the corresponding conventional algorithms cannot. It is also shown that Mod March CL(12N) and Mod March SR(14N) with DB management can detect all Static Single Cell Faults based on the Bit-Oriented-Memories (BOM) test method. Comparisons on test cycle time for Mod March SR, March SR, and March SS in the context of memory Built-In-Self-Test (BIST) are also presented. From the simulation result, it shows that by including Data Backgrounds (DBs) management in Bit-Oriented Memories (BOM), the cycle test time is the same after a given multiple of DBs in the test algorithm. © 2011 IEEE.

DOI： 10.1109/SCOReD.2011.6148694

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84857880363&origin=inward

Additional Path Delay Fault Detection with Adaptive Test Data 査読有り国際誌

K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing 31 - 34 2011年11月

Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling 査読有り国際誌

K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard

IEEE Asian Test Symposium 90 - 95 2011年11月

Power-Aware Test Pattern Generation for At-Speed LOS Testing 査読有り国際誌

A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase, X. Wen

IEEE Asian Test Symposium 506 - 510 2011年11月

Efficient BDD-based Fault Simulation in Presence of Unknown Values 査読有り国際誌

M. A. Kochte, S. Kundu, K. Miyase, X. Wen, H.-J. Wunderlich

IEEE Asian Test Symposium 383 - 388 2011年11月

Towards the Next Generation of Low-Power Test Technologies 査読有り国際誌

X. Wen

IEEE International Conference on ASIC Paper 1E-1 2011年10月

Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing 査読有り国際誌

L.-T. Wang, N. A. Touba, M. S. Hsiao, J.-L. Huang, C.-M. Li, S. Wu, X. Wen, M. Bhattarai, F. Li, Z. Jiang

IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits Paper 5.4 2011年09月

A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE International Test Conference Paper 12.1 2011年09月

Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

IEEE International Test Conference Paper 2.3 2011年09月

SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures 査読有り国際誌

M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enokimoto, H.-J. Wunderlich

IEEE International Symposium on Low Power Electronics and Design 33 - 38 2011年08月

低消費電力LSIのための低消費電力テスト技術招待有り査読有り

温暁青

情報・システムソサイエティ誌 ( 電子情報通信学会　情報・システムソサイエティ ) 16 ( 2 ) 10 - 11 2011年08月

VLSI Testing and Test Power 査読有り国際誌

X. Wen

Workshop on Low Power System on Chip Paper 4.1 2011年07月

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing 査読有り国際誌

K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara

IEICE Transactions on Information and Systems E94-D ( 6 ) 1216 - 1226 2011年06月

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns 査読有り国際誌

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011年05月

Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011年05月

Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing 査読有り国際誌

X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, M. Tehranipoor

IEEE VLSI Test Symposium 166 - 171 2011年05月

Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era 1 - 6 2011年04月

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara

IEICE Transactions on Information and Systems E94-D ( 4 ) 833 - 840 2011年04月

Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation 査読有り国際誌

K. Miyase, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

Design, Automation and Test in Europe 895 - 898 2011年03月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

France Grenoble 2011年03月14日 - 2011年03月18日

Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. This paper presents a novel metric, called the TTR (Transition-Time-Relation-based) metric, which takes transition time relations into consideration in capture-safety checking. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation. © 2011 EDAA.

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79957551358&origin=inward

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

S. Wu,L.-T. Wang,X. Wen,Z. Jiang,M. Hsiao,W.-B. Jone,L. Tan,Y. Zhang,Y. Hu,C.-M. Li,Member,J.-L. Huang,L. Yu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30 ( 3 ) 455 - 463 2011年03月

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme 査読有り国際誌

K. Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara

IEEE Workshop on RTL and High Level Testing 125 - 129 2010年12月

Hybrid Memory Built-In Self-Test Architecture for Multi-port Static RAMs 査読有り国際誌

L. Yu, J. Hung, B. Sheu, B. Huynh, L. Nguyen, S. Wu, L.-T. Wang, X. Wen

IEEE Int Symposium on Defect and Fault Tolerance in VLSI Systems 331 - 339 2010年11月

Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver 査読有り国際誌

K. Miyase,M. A. Kochte,X. Wen,S. Kajihara,H.-J. Wunderlich

IEEE Workshop on Defect and Date Driven Testing 4 Pages 2010年11月

Is Test Power Reduction Through X-Filling Good Enough? 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Test Conference 805 - 805 Poster 2010年11月

On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test 査読有り国際誌

S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, X. Wen

10th International Symposium on Communications and Information Technologies 723 - 726 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Tokyo 2010年10月26日 - 2010年10月29日

This paper proposes a test compaction method for full scan circuits based on multiple capture clock cycles. The multiple cycle test applies more than one capture clock signals for a circuit after scan shift operation, while the capture clock cycle of the conventional scan test is one. Because every captured value at scan flip-flops is used for fault detection, the opportunity of fault detection for each fault increases. As a result, the number of test vectors would be decreased compared with the single cycle mode. Such a test compaction method would be useful in field test that requires less test data so as to store them on-chip. Experimental results show that the proposed method is effective for test compaction. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665084

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=78651251137&origin=inward

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains 査読有り国際誌

S. Wu,L.-T. Wang,L. Yu,H. Furukawa,X. Wen,W.-B. Jone,N. A. Touba,F. Zhao,J. Liu,H.-J. Chao,F. Li,Z. Jiang

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 358 - 366 2010年10月

Case Studies on Transition Fault Test Generation for At-Speed Scan Testing 査読有り国際誌

N. A. Zakariz, E. V. Bautista, S. M. Jusoh, W. F. Lee, X. Wen

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 180 - 188 2010年10月

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes 査読有り国際誌

F. Wu,L. Dilillo,A. Bosio,P. Girard,S. Pravossoudovitch,A. Virazel,M. Tehranipoor,X. Wen,N. Ahmed

ASP Journal of Lower Power Electronics 6 ( 2 ) 359 - 374 2010年08月

On Delay Test Quality for Test Cubes 査読有り国際誌

S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen

IPSJ Transactions on System LSI Design Methodology 3 283 - 291 2010年08月

A Study of Capture-Safe Test Generation Flow for At-Speed Testing 査読有り国際誌

K. Miyase, X. Wen, S. Kajihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja

IEICE Transactions on Information and Systems E93-A ( 7 ) 1309 - 1318 2010年07月

On Estimation of NBTI-Induced Delay Degradation 査読有り国際誌

M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura

IEEE European Test Symposium 107 - 111 2010年05月

Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, X. Wen

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 376 - 381 2010年04月

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme 査読有り国際誌

K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L. Wang, M. Tehranipoor

IEICE Transactions on Information and Systems E93-D ( 1 ) 2 - 9 2010年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock- Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design. Copyright © 2010 The Institute of Electronics.

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=77950234242&origin=inward

CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing 招待有り査読有り国際誌

X. Wen, K. Enokimoto, K. Miyase, S. Kajihara, M. Aso, H. Furukawa

Symposium II (International Semiconductor Technology Conference & China Semiconductor Technology International Conference) 197 - 202 2010年03月

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

L.-T. Wang,X. Wen,S. Wu,H. Furukawa,H.-J. Chao,B. Sheu,J. Guo,and W.-B. Jone

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29 ( 2 ) 299 - 312 2010年02月

A Path Selection Method for Delay Test Targeting Transistor Aging 査読有り国際誌

M. Noda,S. Kajihara,Y. Sato,K. Miyase,X. Wen,and Y. Miura

IEEE International Workshop on Reliability Aware System Design and Test 57 - 61 2010年01月

X-Identification According to Required Distribution for Industrial Circuits 査読有り国際誌

I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

IEEE Workshop on RTL and High Level Testing 76 - 81 2009年11月

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing 査読有り国際誌

K. Enokimoto,X. Wen,Y. Yamato,K. Miyase,H. Sone,S. Kajihara,M. Aso,and H. Furukawa

IEEE Asian Test Symposium 99 - 104 2009年11月

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing 査読有り国際誌

Y. Yamato,X. Wen,K. Miyase,H. Furukawa,and S. Kajihara

IEEE 15th Pacific Rim International Symposium on Dependable Computing 81 - 86 2009年11月

Optimizing the Percentage of X-Bits to Reduce Switching Activity 査読有り国際誌

I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

IEEE Workshop on Defect and Date Driven Testing 4 Pages 2009年11月

A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment 査読有り国際誌

K. Miyase,K. Noda,H. Ito,K. Hatayama,T. Aikyo,Y. Yamato,X. Wen,and S. Kajihara

IEEE/ACM International Conference on Computer Aided Design 97 - 104 2009年11月

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment 査読有り国際誌

M.-F. Wu,J.-L. Huang,X. Wen,K. Miyase

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28 ( 11 ) 1767 - 1776 2009年11月

シグナルインテグリティ考慮型LSIテストを目指して招待有り査読有り

温　暁青

信頼性学会誌 31 ( 7 ) 498 - 505 2009年10月

LSI回路の低キャプチャ電力テスト生成技術招待有り査読有り

温暁青

情報・システムソサイエティ誌 ( 電子情報通信学会　情報・システムソサイエティ ) 14 ( 2 ) 16 - 16 2009年08月

On Calculation of Delay Range in Fault Simulation for Test Cubes 査読有り国際誌

S. Oku,S. Kajihara,K. Miyase,X. Wen,Y. Sato

International Symposium on VLSI Design, Automation, and Test 64 - 67 2009年04月

Power-Aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing 招待有り査読有り国際誌

Y. Yamato,X. Wen,K. Miyase,H. Furukawa,S. Kajihara

Metrology, Reliability and Testing (International Semiconductor Technology Conference & China Semiconductor Technology International Conference) 231 - 236 2009年03月

Turbo1500: Core-Based Design for Test and Diagnosis Using IEEE Std. 1500 査読有り国際誌

L..-T. Wang,R. Apte,S. Wu,B. Sheu,K.-J. Lee,X. Wen,W.-B. Jone,C.-H. Yeh,J. Guo,J. Liu,Y.-C. Sung

IEEE Design & Test of Computers 26 ( 1 ) 26 - 35 2009年01月

On Delay Calculation in 3-valued Fault Simulation 査読有り国際誌

S. Oku,S. Kajihara,K. Miyase,X. Wen,Y. Sato

IEEE Workshop on RTL and High Level Testing 123 - 128 2008年11月

Practical Challenges in Logic BIST Implementation Case Studies 査読有り国際誌

S. Wu,H. Furukawa,B. Sheu,L.-T. Wang,H.-J. Chao,L. Yu,X. Wen,M. Murakami

IEEE Asian Test Symposium 265 - 265 2008年11月

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing 査読有り国際誌

H. Furukawa,X. Wen,K. Miyase,Yuta Yamato,S. Kajihara,Patrick Girard,L.-T. Wang,M. Teharanipoor

IEEE Asian Test Symposium 397 - 402 2008年11月

Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification 査読有り国際誌

K. Miyase,K. Noda,H. Ito,K. Hatayama,T. Aikyo,Y. Yamato,H. Furukawa,X. Wen,S. Kajihara

IEEE/ACM International Conference on Computer Aided Design 52 - 58 2008年11月

GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing 査読有り国際誌

Y. Yamato,X. Wen,K. Miyase,H. Furukawa,S. Kajihara

IEEE Workshop on Defect and Date Driven Testing 4 Pages 2008年10月

Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG 査読有り国際誌

J. Ma,J. Lee,M. Tehranipoor,X. Wen,A. Crouch

IEEE Workshop on Defect and Date Driven Testing 7 Pages 2008年10月

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing 査読有り国際誌

M.-F. Wu,J.-L. Huang,X. Wen,K. Miyase

IEEE International Test Conference Paper 13.1 2008年10月

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using IEEE Std. 1500 査読有り国際誌

L.-T. Wang,R. Apte,S. Wu,B. Sheu,K.-J. Lee,X. Wen,W.-B. Jone,C.-H. Yeh,J. Guo,J. Liu,Y.-C. Sung

IEEE International Test Conference Paper 29.3 2008年10月

On Optimizing Pattern Count and ATPG Time Using A Hybrid Single-Capture Scheme for Testing Scan Designs 査読有り国際誌

B. Sheu,L.-T. Wang,Z. Jiang,J. Soong,S. Wu,R. Apte,X. Wen,C.-M. Li

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 143 - 151 2008年10月

Test Strategies for Low-Power Devices 招待有り査読有り国際誌

C. P. Ravikumar,M. Hirech,X. Wen

Journal of Low Power Electronics 4 ( 2 ) 127 - 138 2008年08月

Estimation of Delay Test Quality and Its Application to Test Generation 査読有り国際誌

S. Kajihara,S. Morishima,M. Yamamoto,X. Wen,M. Fukunaga,K. Hatayama,T. Aikyo

IPSJ Transaction of System LSI Design Methodology 1 104 - 115 2008年08月

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing 査読有り国際誌

X. Wen,K. Miyase,S. Kajihara,H. Furukawa,Y. Yamato,A. Takashima,K. Noda,H. Ito,K. Hatayama,T. Aikyo,K. K. Saluja

IEEE European Test Symposium 55 - 60 2008年05月

Diagnosis of Realistic Defects Based on X-Fault Model 査読有り国際誌

I. Polian,Y. Nakamura,P. Engelke,S. Spinner,K. Miyase,S. Kajihara,B. Becker,X. Wen

IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems 263 - 266 2008年04月

Test Strategies for Low-Power Devices 招待有り査読有り国際誌

C. P. Ravikumar,M. Hirech,X. Wen

Design Automation, and Test in Europe 728 - 733 2008年03月

VirtualScan: A Test Compression Technology Using Combinational Logic and One-Pass ATPG 査読有り国際誌

L.-T. Wang,X. Wen,S. Wu,Z. Wang,Z. Jiang,B. Sheu,X. Gu

IEEE Design & Test of Computers 25 ( 2 ) 122 - 130 2008年03月

On Detection of Bridge Defects with Stuck-at Tests 査読有り国際誌

K. Miyase,K. Terashima,X. Wen,S. Kajiihara,and S. M Reddy

IEICE Transactions on Information and Systems E91-D ( 3 ) 683 - 689 2008年03月

A Novel Per-Test Fault Diagnosis Method Based On the Extended X-Fault Model for Deep-Submicron LSI Circuits 査読有り国際誌

Y. Yamato,Y. Nakamura,K. Miyase,X. Wen,and S. Kajihara

IEICE Transactions on Information and Systems E91-D ( 3 ) 667 - 674 2008年03月

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing 査読有り国際誌

X. Wen,K. Miyase,T. Suzuki,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing 24 ( 4 ) 379 - 391 2008年01月

Estimation of Delay Test Quality and Its Application to Test Generation 査読有り国際誌

S. Kajihara,S. Morishima,M. Yamamoto,X. Wen,M. Fukunaga,K. Hatayama,and T. Aikyo

IEEE/ACM International Conference on Computer Aided Design 413 - 417 2007年11月

A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set 査読有り国際誌

K. Miyase,X. Wen,S. Kajihara,M. Haraguchi,H. Furukawa

IEEE International Workshop on Defect Based Testing 51 - 56 2007年10月

A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing 査読有り国際誌

X. Wen,K. Miyase,S. Kajihara,T. Suzuki,Y. Yamato,P. Girard,Y. Ohsumi,and L.-T. Wang

IEEE International Test Conference 25.1 2007年10月

A Novel ATPG Method for Capture Power Reduction During Scan Testing 査読有り国際誌

X. Wen,S. Kajiihara,K. Miyase,T. Suzuki,K. K. Saluja,L.-T. Wang,K. Kinoshita

IEICE Transactions on Information and Systems E90-D ( 9 ) 1398 - 1405 2007年09月

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing 査読有り国際誌

X. Wen,K. Miyase,T. Suzuki,S. Kajihara,Y. Ohsumi,K. K. Saluja

IEEE/ACM Design Automation Conference 527 - 532 2007年06月

An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits 査読有り国際誌

X. Wen,Y. Yamato,K. Miyase,S. Kajihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE Workshop on RTL and High Level Testing 55 - 60 2006年11月

Test Data Compression Based on Clustered Random Access Scan 査読有り国際誌

Y. Hu,C. Li,J. Li,Y. Han,X. Li,W. Wang,H. Li,L.-T. Wang,X. Wen

IEEE Asian Test Symposium 231 - 236 2006年11月

A Per-Test Fault Diagnosis Method Based on the X-Fault Model 査読有り国際誌

X. Wen,S. Kajiihara,K. Miｙase,Y. Yamato,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEICE Transactions on Information and Systems E89-D ( 11 ) 2756 - 2765 2006年11月

A Framework of High-quality Transition Fault ATPG for Scan Circuits 査読有り国際誌

S. Kajihara,S. Morishima,A. Takuma,X. Wen,T. Maeda,S. Hamada,Y. Sato

IEEE International Test Conference Paper 2.1 2006年10月

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing 査読有り国際誌

H. Furukawa,X. Wen,L.-T. Wang,B. Sheu,Z. Jiang,S. Wu

IEEE International Test Conference Paper 17.2 2006年10月

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time 査読有り国際誌

Y. Hu,Y. Han,X. Li,H. Li,X. Wen

IEICE Transactions on Information and Systems E89-D ( 10 ) 2616 - 2625 2006年10月

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation 査読有り国際誌

X. Wen,K. Miyase,T. Suzuki,Y. Yamato,S. Kajihara,L.-T. Wang,K. K. Saluja

IEEE International Conference on Computer Design 251 - 258 2006年10月

Hybrid Fault Simulation with Compiled and Event-Driven Methods 査読有り国際誌

K. Taniguchi,H. Fujii,S. Kajihara,X. Wen

IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology 240 - 243 2006年09月

A New Method for Low-Capture-Power Test Generation for Scan Testing 査読有り国際誌

X. Wen,Y. Yamashita,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEICE Transactions on Information and Systems E89-D ( 5 ) 1679 - 1686 2006年05月

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing 査読有り国際誌

X. Wen,S. Kajihara,K. Miyase,T. Suzuki,K. K. Saluja,L.-T. Wang,K. S. Abdel-Hafez,K. Kinoshita

IEEE VLSI Test Symposium 58 - 63 2006年04月

A Dynamic Test Compaction Procedure for High-quality Path Delay Testing 査読有り国際誌

M. Fukunaga,S. Kajihara,X. Wen,T. Maeda,S. Hamada,Y. Sato

IEEE/ACM Asian and South Pacific Design Automation Conference 348 - 353 2006年01月

On Improving Defect Coverage of Stuck-at Fault Tests 査読有り国際誌

K. Miyase, K. Terashima, S. Kajihara, X. Wen, S. M. Reddy

IEEE Asian Test Symposium 216 - 223 2005年12月

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-In Power Dissipation and Test Application Time 査読有り国際誌

Y. Hu, Y. Han, X. Li, H. Li, X. Wen

IEEE Pacific Rim International Symposium on Dependable Computing 8 - 8 2005年12月

Efficient Test Set Modification for Capture Power Reduction 査読有り国際誌

X. Wen,T. Suzuki,S. Kajihara,K. Miyase,Y. Minamoto,L.-T. Wang,K. K. Saluja

Jounal of Low Power Electrnics 1 ( 3 ) 319 - 330 2005年12月

Low-Capture-Power Test Generation for Scan-Based At-Speed Testing 査読有り国際誌

X. Wen,Y. Yamashita,S. Morishima,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE International Test Conference Paper 39.2 2005年11月

UltraScan: Using Time-Division Demultiplexing/Multiplexing (TDDM/TDM) with VirtualScan for Test Cost Reduction 査読有り国際誌

S. Wu,L.-T. Wang,K. S. Abdel-Hafez,B. Sheu,F. Hsu,S. Lin,M. Chang,X. Wen

IEEE International Test Conference Paper 36.4 2005年11月

At-Speed Logic BIST Archtecture for Multiple-Clock Circuits 査読有り国際誌

L.-T. Wang,X. Wen,B. Hsu,S. Wu,J. Guo

IEEE International Conference on Computer Design 475 - 478 2005年10月

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores 査読有り国際誌

Y. Han, Y. Hu, X. Li, H. Li, A. Chandra, X. Wen

IEICE Transactions on Information and Systems E88-D ( 9 ) 2126 - 2134 2005年09月

A Method for Low-Capture-Power At-Speed Test Generation 査読有り国際誌

X. Wen,Y. Yamashita,S. Morishima,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE Workshop on RTL and High Level Testing 40 - 49 2005年07月

On Quantifying Observability for Fault Diagnosis of VLSI Circuits 査読有り国際誌

N. Toyota,X. Wen,S. Kajihara,M. Sanada

IEEE Workshop on RTL and High Level Testing 192 - 197 2005年07月

Path Delay Test Compaction with Process Variation Tolerance 査読有り国際誌

S. Kajihara,M. Fukunaga,X. Wen,T. Maeda,S. Hamada,Y. Sato

IEEE/ACM Design Automation Conference 845 - 850 2005年06月

On the Extraction of a Minimum Cube to Justify Signal Line Values 査読有り国際誌

K. Miyase,S. Nagayama,S. Kajihara,X. Wen,S. M. Reddy

IEEE European Test Symposium 79 - 84 2005年05月

On Low-Capture-Power Test Generation for Scan Testing 査読有り国際誌

X. Wen,Y. Yamashita,S. Kajiihara,L.-T. Wang,K. K. Saluja,K. Kinoshita

IEEE VLSI Test Symposium 265 - 270 2005年05月

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies 査読有り国際誌

X. Wen,S. Kajihara,H. Tamamoto,K. K. Saluja,K. Kinoshita

IEICE Transactions on Information and Systems E88-D ( 4 ) 703 - 710 2005年04月

中間故障電圧値を扱う故障シミュレーションの高速化について査読有り

温暁青，梶原誠司，玉本英夫，K. K. Saluja，樹下行三

電子情報通信学会論文誌D-I J88-D-I ( 4 ) 906 - 907 2005年04月

At-Speed Logic BIST for IP Cores 査読有り国際誌

B. Cheon,E. Lee,L.-T. Wang,X. Wen,P. Hsu,J. Cho,J. Park,H. Chao,S. Wu

Design Automation, and Test in Europe 860 - 861 2005年03月

Fault Diagnosis for Physical Defects using Unknown Behavior Model 査読有り国際誌

X. Wen,H. Tamamoto,K. K. Saluja,K. Kinoshita

Journal of Computer Science and Technology 20 ( 2 ) 187 - 194 2005年03月

Test Compression for Scan Circuits Using Scan Polarity Adjustment and Pinpoint Test Relaxation 査読有り国際誌

Y. Doi,S. Kajihara,X. Wen,L. Li,and K. Chakrabarty

ACM Asian and South Pacific Design Automation Conference 59 - 64 2005年01月

On Extraction of a Cube with the Minimum Number of Literals from a Given Input Vector 査読有り国際誌

K. Miyase,S. Nagayama,S. Kajihara,X. Wen,and S. M. Reddy

IEEE Workshop on RTL and High Level Testing 71 - 76 2004年11月

On Per-Test Fault Diagnosis Using the X-Fault Model 査読有り国際誌

X. Wen,T. Miyoshi,S. Kajiihara,L. Wang,K. K. Saluja,and K. Kinoshita

IEEE/ACM International Conference on Computer Aided Design 633 - 640 2004年11月

VirtualScan: A New Compressed Scan Technology for Test Cost Reduction 査読有り国際誌

L.-T. Wang,X. Wen,H. Furukawa,F. Hsu,S. Lin,S. Tsai,K. S. Abdel-Hafez,S. Wu

IEEE International Test Conference 916 - 925 2004年10月

ロジックBIST技術の現状と課題招待有り査読有り

温暁青，梶原誠司

日本信頼性学会誌 ( 未設定 ) 26 ( 4 ) 252 - 262 2004年06月

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