研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 1 - 20 件目／全件表示 >>

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications 査読有り国際誌

Yan A., He Y., Niu X., Cui J., Ni T., Huang Z., Girard P., Wen X.

IEEE Design and Test 40 ( 4 ) 34 - 41 2023年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

This article proposes a robust and low power flip-flop cell with complete double-node-upset (DNU) tolerance for aerospace applications. The proposed cell is constructed from a master latch and a slave latch. The master latch comprises two C-elements as well as one clock-controlled C-element; the slave latch is similar to the master but has an extra keeper to avoid high-impedance state of the output-level C-element. The proposed cell can provide complete DNU-tolerance while reducing power dissipation by 65x0025; on average when compared with existing radiation-hardened flip-flop cells.

DOI： 10.1109/MDAT.2023.3267747

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Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata 査読有り国際誌

Yan A., Liu R., Cui J., Ni T., Girard P., Wen X., Zhang J.

IEEE Transactions on Circuits and Systems II: Express Briefs 70 ( 6 ) 2256 - 2260 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it a promising candidate to replace the complementary metal oxide semiconductor (CMOS) technology. Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this brief, we propose two types of excess-3 code (XS-3) based BCD adders (XS-3DAs). We use ripple-carry adders (RCA) and parallel binary adders (PBA) to construct XS-3DAs in QCA Designer tool, respectively. The PBA-based XS-3DA is constructed with a new correction logic. 4-bit, 8-bit, and 16-bit XS-3DAs are constructed based on the two proposed XS-3DAs, respectively. Comparisons show that, with the increase of design scaling, the delay and area-delay product (ADP) of the PBA-based XS-3DAs can be significantly reduced in comparison with that of the RCA-based XS-3DAs. Compared with the 16-digit RCA-based XS-3DA, the cell count, area, delay and ADP of the proposed 16-digit PBA-based XS-3DA are reduced by 37.88%, 25.99%, 37.68% and 53.88%, respectively.

DOI： 10.1109/TCSII.2023.3237695

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LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42 ( 6 ) 2069 - 2073 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

DOI： 10.1109/TCAD.2022.3213212

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Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 59 ( 3 ) 2885 - 2897 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low-cost version of the QRHIL), for highly robust computing in harsh radiation environments. First, the QRHIL that mainly consists of a 5 × 5 looped C-element matrix is proposed. Then, to reduce overhead, the QRHIL-LC that mainly uses 24 interlocking C-elements is proposed. Both latches can self-recover from any QNU, while the QRHIL-LC has a low cost compared to the QRHIL. Simulation waveforms show the QNU-recoverability of the proposed QRHIL and QRHIL-LC latches. Moreover, compared with the QRHIL latch, the QRHIL-LC can approximately save power dissipation by 16% and silicon area by 5%.

DOI： 10.1109/TAES.2022.3219372

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Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion 査読有り国際誌

Zhou W., Ouyang Y., Xu D., Huang Z., Liang H., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 ( 4 ) 442 - 455 2023年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

As technology feature sizes diminish to the nanometer regime, the leakage power crisis has become a major challenge in network-on-chip (NoC) design. Power gating (PG) is used to mitigate growing leakage power as an effective static power-saving technique. Applying PG in a multiple NoC (Multi-NoC) rather than a traditional NoC is a promising solution. However, limited by the channel width of the subnets, the increase in packet length will bring a severe serialization issue and performance loss. Previous Multi-NoC schemes have to wake up more subnets to minimize the performance loss, which also sacrifices their energy efficiency. In this article, we introduce an architecture, namely, BandExp, which allows subnets to expand their bandwidth by utilizing the idle physical links of other subnets. More bandwidth helps subnets mitigate the serialization issue and reduce the performance loss. Meanwhile, other subnets gain longer sleep cycles and thus save more energy. Evaluation results indicate that compared to the state-of-the-art Catnap, the proposed architecture reduces the average packet latency and execution time of different benchmarks by 19.3% and 3.2%, respectively. Also, the net static energy of the network is reduced by 23.2% on average, while the incurred area overhead is only 1.3%.

DOI： 10.1109/TVLSI.2023.3244859

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High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology 査読有り国際誌

Yan A., Zhou Z., Ding L., Cui J., Huang Z., Wen X., Girard P.

Proceedings -Design, Automation and Test in Europe, DATE 2023-April 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the advancement of CMOS technologies, circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). To effectively provide nonvolatility as well as tolerance against DNUs caused by radiation, this paper proposes a nonvolatile and DNU resilient latch that mainly comprises two magnetic tunnel junction (MTJ), two inverters and eight C-elements. Since two MTJs are used and all internal nodes are interlocked, the latch can provide nonvolatility and recovery from all possible DNUs. Simulation results demonstrate the nonvolatility, DNU recovery and high performance of the proposed latch.

DOI： 10.23919/DATE56975.2023.10136927

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Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates 査読有り国際誌

Yan A., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland) 11 ( 10 ) 2022年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata is a novel nanotechnology that has the advantages of low energy dissipation, easy integration, and high computing speed. It is regarded as one of the powerful alternative technologies for the next generation of integrated circuits because of its unique implementation concept. In this paper, two XOR/XNOR gates are proposed. Level-sensitive T flip-flops, negative edge-trigger T flip-flops, two-to-one multiplexers, reversible gates, and (8, 4) polar encoders are implemented based on these two proposed logic gates. Simulation results show that, compared with the existing level-sensitive T flip-flops, the second proposed level-sensitive T flip-flop has fewer cells and lower energy dissipation; compared with the best (8, 4) polar encoder, the cell count and area of the second proposed (8, 4) polar encoder are decreased by 13.67% and 12.05%, respectively. The two XOR/XNOR gates have a stable output and low energy dissipation, which can be flexibly designed into complex quantum-dot cellular automata circuits.

DOI： 10.3390/ELECTRONICS11101658

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Evaluation and Test of Production Defects in Hardened Latches 査読有り国際誌

Ma R., Holst S., Wen X., Yan A., Xu H.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E105D ( 5 ) 996 - 1009 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (PTVF), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed PTVF metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.

DOI： 10.1587/transinf.2021EDP7216

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A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage 査読有り

Yan A., Dingl L., Zhou Z., Huang Z., Cui J., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2022-November 1 - 6 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With technology scaling down, the vulnerability of circuits to radiation and the increase of static power have become severe concerns. Spintronic devices such as magnetic tunnel junction (MTJ) have been developed to cope with many concerns, among which reliability concerns [1]. Spintronic devices have attractive properties, such as non-volatility and compatibility with conventional CMOS fabrication process. Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magnetic latch, namely M-TPDICE, that can completely tolerate single-node upsets (SNUs) and double-node upsets (DNUs). Simulations of the proposed latch with the HSPICE tool with a 45 nm CMOS technology model have demonstrated the effectiveness of the proposed latch.

DOI： 10.1109/ATS56056.2022.00013

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MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator 査読有り国際誌

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wen X.

Proceedings of the 2022 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2022 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the potential at the input flips too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses propagating in the circuit. We study the effect of jitter on the output of the XOR gate when the XOR gate has high-speed changing inputs. Excessively small short pulses will be eliminated in the circuit and suppresses the accumulation of jitter in the oscillator. Our proposed TRNG cleverly avoids the concatenation of the short pulses with the inverter so that the short pulses are only input to the XOR gate, affecting the oscillation of the circuit by interfering with the change of the XOR gate output by another input change. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA, making it comparable to the state-of-the-art TRNG also implemented on FPGAs. The results show that this TRNG has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.

DOI： 10.1109/AsianHOST56390.2022.10022291

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GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators 査読有り国際誌

Holst S., Bumun L., Wen X.

Proceedings of the Asian Test Symposium 2021-November 127 - 132 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Systolic arrays are currently used in autonomous systems such as self-driving cars to accelerate the enormous amount of matrix operations necessary for DNN inference. The reliability of such accelerators are of utmost importance since any loss in DNN accuracy due to erroneous calculations can have dire consequences. We propose a novel method to measure accuracy losses caused by arbitrary timing faults in systolic arrays. Our GPU-based simulation system enables for the first time a complete and accurate timing simulation of all inference-related matrix operations on large systolic arrays. A single consumer-grade GPU can simulate a LeNet-5 at a throughput of about 13s per inference. Furthermore, our simulation approach readily scales to larger DNNs and multiple GPUs.

DOI： 10.1109/ATS52891.2021.00034

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QART: A low-power quadruple-node-upset hardened latch based on asymmetric ring topology 査読有り国際誌

Huang Z., Yang S., Wu J., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

Microelectronics Journal 176 2026年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

As CMOS technology continues to scale down, the charge sharing effect has made multiple-node upsets a critical challenge to the reliability of integrated circuits. Existing quadruple-node upset (QNU) hardened latches commonly suffer from large area, high power consumption, and excessive overall overhead. This paper proposes a highly robust, low-power quadruple-node upset self-recoverable latch named QART (Quadruple-upset Asymmetric Ring Topology). The latch adopts an asymmetric bipartite graph architecture, consisting of 11 four-input variant C-elements (CE-4) and 11 two-input inverter (PN) cells interleaved into a ring network. It utilizes node parity isolation and ring-offset mapping to sever cascaded fault paths within the same group. HSPICE simulation based on a 45 nm CMOS process shows that the QART latch achieves complete QNU self-recovery. Compared with conventional QNU self-recovery structures (QRHIL, MURLAV, RS-QTRL), the power consumption, area-power-delay product (APDP), and setup time are reduced by averages of 60.57%, 60.61%, and 18.51%, respectively, and the overall overhead is significantly superior to that of similar self-recovery structures. In addition, for latches composed of heterogeneous cells, this paper proposes a heterogeneous worst-case path tracing algorithm based on discrete state convergence, which improves the self-recovery rate verification efficiency by more than 99.9% compared to conventional SPICE fault injection simulation.

DOI： 10.1016/j.mejo.2026.107358

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LOSTA: A low-overhead high-defect-detectability test-aware hardened latch with layout-aware short-defect modeling 査読有り国際誌

Xu H., Zhao Z., Ma R., Holst S., Wang S., Liang H., Wen X.

Microelectronics Journal 175 2026年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

Many hardened latch designs employ cell-internal redundancy to mitigate soft errors. However, this redundancy tends to mask manufacturing defects, rendering them difficult to detect. Furthermore, such undetected defects can compromise the soft-error resilience of hardened latches. To enhance defect-detectability while preserving high soft-error tolerance, several scan-test-aware hardened latch designs integrate Design-For-Test (DFT) techniques, which inevitably incur substantial overhead. Moreover, existing short-defect models used to evaluate the defect detectability of test-aware hardened latches are derived from netlist node combinations, without accounting for actual physical wire placement. To address these challenges, this paper proposes a novel low-overhead, high-defect-detectability scan-test-aware hardened latch (LOSTA), and introduces a layout-aware short-defect-modeling method based on the open-source tool KLayout to evaluate test-aware hardened latch designs. In addition, within the proposed defect-modeling framework, tailored net-pair spacing guidelines are incorporated into the layout design of LOSTA to increase defect coverage (DC). Simulation results demonstrate that, compared to state-of-the-art test-aware hardened latches, the proposed LOSTA latch achieves the highest DC while realizing an average reduction of 40.90% in power consumption, 33.26% in delay, 52.96% in area overhead, and 85.83% in power-delay-area product (PDAP), respectively.

DOI： 10.1016/j.mejo.2026.107314

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A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values 査読有り国際誌

Ni T., Rui W., Zhuo C., Li Y., Wen X., Nie M.

ACM Transactions on Design Automation of Electronic Systems 31 ( 4 ) 2026年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

Wafer acceptance testing (WAT) is a process that is used to assess the quality and reliability of manufactured wafers. This technique for the early detection and screening of chips allows for improvements in their reliability and performance during the manufacture of semiconductor devices. The automatic test equipment (ATE) used for processing millions of wafers is susceptible to a number of issues, including the absence of data values, the presence of redundant parameters, and categorical imbalance. These issues increase the cost of data processing and impede an investigation into the relationship between WAT and feature diagnostics. In this study, we propose a method with a low test escape rate based on a multi-objective optimization algorithm to reduce the cost of testing and minimize the number of defective dice that go undetected. The proposed method retains outliers, dynamically selects the range of the neighborhood to reduce the cost of testing, and uses Shapley values to analyze a WAT dataset to determine the importance of features of the data. The multi-objective optimization algorithm ranks features by their importance and applies an adaptive method to eliminate features with a low overall correlation, thereby reducing the risk that defective dice are undetected.

DOI： 10.1145/3716826

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LTTL: A Low-Overhead and Triple-Node-Upset-Tolerant Latch Design for Aerospace Applications 査読有り国際誌

Ma Z., Gao Z., Guo X., Liu Q., Man Y., Liang H., Wen X.

Glsvlsi 2026 Proceedings of the Great Lakes Symposium on VLSI 2026 187 - 193 2026年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the feature size of the CMOS technology keeps scaling down, the charge sharing caused by radiation is becoming more and more prominent, and the occurrence possibility of the triple-node upset (TNU) increases significantly. In this paper, we propose a low-overhead and TNU-tolerant latch (LTTL) that leverages three parallel storage cells and an output-level error interceptive module to achieve complete TNU tolerance while minimizing design overhead. The optimized structure eliminates redundant devices and employs a high-speed D-to-Q path, significantly reducing delay-area-power product (DAPP). Even any three nodes of the latch are flipped at the same time, the output of the latch can retain the original value. Simulation results not only confirm the TNU tolerance of the proposed latch but also demonstrate that the latch can provide a 57% reduction in delay, 20% reduction in area, and 62% reduction in DAPP on average compared to state-of-the-art TNU-tolerant latches.

DOI： 10.1145/3787109.3815297

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High-Accuracy, Low-Utilization Multichannel 2-ps Bin Size FPGA Digital-to-Time Converter Based on Compact Multidimensional Delay Array 査読有り国際誌

Chen P., Wijaya J.A., Chen C., Wen X., Holst S.

IEEE Transactions on Very Large Scale Integration VLSI Systems 34 ( 6 ) 1930 - 1939 2026年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Digital-to-time converter (DTC) or digital delay/timing generator has been developed for quite many years and plays a crucial role in automatic test equipment (ATE) and built-in self-test (BIST) industries. This study proposes a compact multidimensional delay array DTC based on phase shift in a phase-locked loop (PLL) to further extend field-programmable gate array (FPGA) applications into the analog domain. All internal delay cells are precisely controlled by PLL from the beginning to make the output phases distributed within the reference clock period as uniformly as possible. For further resolution enhancement, a hybrid structure based on PLL and a multidimensional delay array is presented to ensure high enough accuracy and substantially reduce logic utilization through phase sorting and selection. For concept proving, the proposed four-channel DTC is implemented on an Altera Stratix IV FPGA board to achieve 20 internal control bits, 2-ps resolution with very low integral nonlinearity (INL) and differential nonlinearity (DNL) of -2.06 to 2.01 and -2.50 to 2.31 LSB, respectively. In addition, the circuit has been successfully implemented on a much cheaper Cyclone IV platform also for cost reduction to achieve the same resolution with the best fine stage INL and DNL of -3.81 to 3.56 and -3.93 to 4.41 LSB, respectively. The DTC performance has demonstrated improvements to that of prior arts by one order finer resolution and higher accuracy compared to non-Vernier prior works, while eliminating the serious dead time issues inherent in Vernier DTCs.

DOI： 10.1109/TVLSI.2026.3676373

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Design of Quintuple-Node-Upset Hardened Latches Based on C-Element Voting and an Analog Voter 査読有り国際誌

Huang Z., Yang S., Wu J., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

IEEE Transactions on Device and Materials Reliability 26 ( 2 ) 604 - 615 2026年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

As nanometer-scale CMOS technology continues to advance, the susceptibility of memory cells to soft errors has significantly increased. Single-event multiple-node upsets (MNUs) have become a critical factor affecting integrated circuit reliability. This paper first proposes a self-recoverable double-node-upset (DNU) hardened latch (DSAR) based on the Soft-Error Aware Read-Decoupled (SAR) latch. Building upon this, a Quad-SAR latch capable of tolerating Quintuple-node upset (QtNU) is designed through dual DSAR redundancy and a two-stage C-element (CE) voting mechanism, achieving an optimized balance in area, power consumption, and delay. Furthermore, to address the high-impedance-state (HIS) sensitivity issue of C-elements, a Quint-SAR latch is achieved in this paper through the implementation of Quintuple-modular redundancy (QMR) combined with an Analog Voter (AV). This structure not only effectively tolerates QtNUs, but its incorporated Analog Voter features HIS insensitivity and offers significant low-overhead advantages compared to traditional voters. Extensive fault injection, PVT fluctuation, and negative bias temperature instability (NBTI) aging effect simulations verify the reliability of the proposed designs. HSPICE simulation results show that both the Quad-SAR and Quint-SAR latches possess QtNU tolerance capability and achieve a good balance in hardware overhead. Quad-SAR is suitable for low-power and low-delay requirements in non-HIS-sensitive scenarios, while Quint-SAR, with its HIS immunity, becomes the preferred solution for high-robustness scenarios. Compared to QNU-hardened and QtNU-hardened latches, their area-power-delay product (APDP) exhibits a decrease of 49.41% and 17.16%, respectively, and their setup time exhibits a decrease of 35.10% and 49.71%, respectively.

DOI： 10.1109/TDMR.2026.3680306

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Hi-ILT: A hybrid End-to-End framework of lightweight hierarchical VAE and physics-Guided ILT for inverse lithography technology 査読有り国際誌

Xu H., Wang T., Zhao Z., Ma R., Wen X., Liang H.

Optics and Lasers in Engineering 200 2026年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

Optical Proximity Correction (OPC) is a core technology for compensating lithographic diffraction effects in advanced manufacturing processes. Although Inverse Lithography Technology (ILT) enables high-precision mask optimization, it faces challenges in balancing mask printability and optimization efficiency due to three key problems: (1) low-quality initial solutions, (2) high computational overhead, and (3) the inability of pure data-driven methods to accurately model Sub-Resolution Assist Features (SRAF). To address these problems, this paper proposes Hi-ILT, an end-to-end OPC framework that integrates lightweight deep learning and physical ILT correction. A lightweight Convolutional Neural Network (CNN) first generates a high-precision initial mask at low resolution, with a Binary-Straight-Through Estimator (BSTE) resolving binarization gradient vanishing to stabilize training and achieve fast convergence. Subsequently, a gradient descent based ILT correction layer performs fine-grained optimization of mask details (especially SRAF) at high resolution and models process variations. Experiments on 32 nm node M1 layouts (ICCAD 2013 benchmark) and 10 large-scale datasets demonstrate that Hi-ILT outperforms state-of-the-art methods. Compared to deep learning-based ILT methods, it reduces L<inf>2</inf> error by up to 30.1%, Process Variation Band (PVB) by up to 19.8%, and Edge Placement Error (EPE) violations by up to 73.4%; compared to gradient descent-based ILT methods, it shortens end-to-end Turn Around Time (TAT) by up to 69.4% while maintaining higher precision. Hi-ILT effectively achieves a balance between high printability and efficient optimization, making it suitable for advanced lithography requirements.

DOI： 10.1016/j.optlaseng.2026.109621

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Functional Fault Impact Probability Prediction using Spatio-Temporal Graph Convolutional Network 査読有り国際誌

Wei S., Wang S., Kai H., Higami Y., Ma R., Ni T., Wen X., Takahashi H.

ACM Transactions on Design Automation of Electronic Systems 31 ( 5 ) 2026年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

Logic-level defects that escape manufacturing tests pose reliability risks in modern systems and require functional testing to identify their activation and propagation behaviors. However, effective functional testing is limited by the high cost of long-cycle fault simulations. To address this challenge, we propose a Spatio-Temporal Graph Convolutional Network framework to efficiently and accurately predict the Fault Impact Probability on the circuit's function cross-over multiple function cycles, enabling rapid quantitative assessment of functionally possible faults. Our method represents gate-level netlists as spatio-temporal graphs, capturing both structural connectivity and short-range signal-propagation dynamics. With dedicated spatial and temporal encoders, the proposed ST-GCN enables accurate prediction of multi-cycle circuit-level FIP. Experiments on ISCAS’89 benchmarks show that the approach reduces fault-simulation cost by over an order of magnitude while maintaining high accuracy (mean absolute error as low as 0.024 for 5-cycle predictions). The framework supports both testability-metric-based and simulation-based feature construction, enabling a tunable balance between efficiency and accuracy. A case study on test point selection further demonstrates that using predicted FIPs to guide observation-point placement improves the detectability of multi-cycle, hard-to-detect circuit-level faults. Overall, this work provides a scalable solution for circuit-level multi-cycle fault-impact assessment and can be readily integrated into functional test generation and other Electronic Design Automation workflows.

DOI： 10.1145/3798106

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105042557905&origin=inward

Nonvolatile Flip-Flop Designs with Soft Error Recovery Based on Magnetic Tunnel Junction and CMOS for Aerospace Applications 査読有り国際誌

Gao Z., Liu H., Song J., Pei Z., Jiang W., Wang Q., Wen X.

Journal of Electronic Testing Theory and Applications JETTA 42 ( 2 ) 249 - 257 2026年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the semiconductor technology advances, soft errors caused by radiative particles are becoming a major concern for power-sensitive digital circuits in aerospace applications. Radiation hardening by design (RHBD) and magnetic tunnel junction (MTJ) are employed to cope with these issues. In this paper, two novel non-volatile flip-flops (FFs) are proposed, both of which can fully recover from all single- and double-node upsets (DNUs). The embedded MTJs are non-volatile and compatible with the conventional CMOS process. Comprehensive simulations show that the proposed flip-flops have excellent DNU-recovery and non-volatility at the cost of a low increase in area overhead. The proposed flip-flops reduce the delay by 21.99% and the power by 46.18%, on average, compared to state-of-the-art non-volatile flip-flops.

DOI： 10.1007/s10836-026-06226-5

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105038156070&origin=inward

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