研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 1 - 20 件目／全件表示 >>

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications 査読有り国際誌

Yan A., He Y., Niu X., Cui J., Ni T., Huang Z., Girard P., Wen X.

IEEE Design and Test 40 ( 4 ) 34 - 41 2023年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

This article proposes a robust and low power flip-flop cell with complete double-node-upset (DNU) tolerance for aerospace applications. The proposed cell is constructed from a master latch and a slave latch. The master latch comprises two C-elements as well as one clock-controlled C-element; the slave latch is similar to the master but has an extra keeper to avoid high-impedance state of the output-level C-element. The proposed cell can provide complete DNU-tolerance while reducing power dissipation by 65x0025; on average when compared with existing radiation-hardened flip-flop cells.

DOI： 10.1109/MDAT.2023.3267747

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Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata 査読有り国際誌

Yan A., Liu R., Cui J., Ni T., Girard P., Wen X., Zhang J.

IEEE Transactions on Circuits and Systems II: Express Briefs 70 ( 6 ) 2256 - 2260 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it a promising candidate to replace the complementary metal oxide semiconductor (CMOS) technology. Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this brief, we propose two types of excess-3 code (XS-3) based BCD adders (XS-3DAs). We use ripple-carry adders (RCA) and parallel binary adders (PBA) to construct XS-3DAs in QCA Designer tool, respectively. The PBA-based XS-3DA is constructed with a new correction logic. 4-bit, 8-bit, and 16-bit XS-3DAs are constructed based on the two proposed XS-3DAs, respectively. Comparisons show that, with the increase of design scaling, the delay and area-delay product (ADP) of the PBA-based XS-3DAs can be significantly reduced in comparison with that of the RCA-based XS-3DAs. Compared with the 16-digit RCA-based XS-3DA, the cell count, area, delay and ADP of the proposed 16-digit PBA-based XS-3DA are reduced by 37.88%, 25.99%, 37.68% and 53.88%, respectively.

DOI： 10.1109/TCSII.2023.3237695

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LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42 ( 6 ) 2069 - 2073 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

DOI： 10.1109/TCAD.2022.3213212

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Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 59 ( 3 ) 2885 - 2897 2023年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low-cost version of the QRHIL), for highly robust computing in harsh radiation environments. First, the QRHIL that mainly consists of a 5 × 5 looped C-element matrix is proposed. Then, to reduce overhead, the QRHIL-LC that mainly uses 24 interlocking C-elements is proposed. Both latches can self-recover from any QNU, while the QRHIL-LC has a low cost compared to the QRHIL. Simulation waveforms show the QNU-recoverability of the proposed QRHIL and QRHIL-LC latches. Moreover, compared with the QRHIL latch, the QRHIL-LC can approximately save power dissipation by 16% and silicon area by 5%.

DOI： 10.1109/TAES.2022.3219372

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Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion 査読有り国際誌

Zhou W., Ouyang Y., Xu D., Huang Z., Liang H., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 ( 4 ) 442 - 455 2023年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

As technology feature sizes diminish to the nanometer regime, the leakage power crisis has become a major challenge in network-on-chip (NoC) design. Power gating (PG) is used to mitigate growing leakage power as an effective static power-saving technique. Applying PG in a multiple NoC (Multi-NoC) rather than a traditional NoC is a promising solution. However, limited by the channel width of the subnets, the increase in packet length will bring a severe serialization issue and performance loss. Previous Multi-NoC schemes have to wake up more subnets to minimize the performance loss, which also sacrifices their energy efficiency. In this article, we introduce an architecture, namely, BandExp, which allows subnets to expand their bandwidth by utilizing the idle physical links of other subnets. More bandwidth helps subnets mitigate the serialization issue and reduce the performance loss. Meanwhile, other subnets gain longer sleep cycles and thus save more energy. Evaluation results indicate that compared to the state-of-the-art Catnap, the proposed architecture reduces the average packet latency and execution time of different benchmarks by 19.3% and 3.2%, respectively. Also, the net static energy of the network is reduced by 23.2% on average, while the incurred area overhead is only 1.3%.

DOI： 10.1109/TVLSI.2023.3244859

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High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology 査読有り国際誌

Yan A., Zhou Z., Ding L., Cui J., Huang Z., Wen X., Girard P.

Proceedings -Design, Automation and Test in Europe, DATE 2023-April 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the advancement of CMOS technologies, circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). To effectively provide nonvolatility as well as tolerance against DNUs caused by radiation, this paper proposes a nonvolatile and DNU resilient latch that mainly comprises two magnetic tunnel junction (MTJ), two inverters and eight C-elements. Since two MTJs are used and all internal nodes are interlocked, the latch can provide nonvolatility and recovery from all possible DNUs. Simulation results demonstrate the nonvolatility, DNU recovery and high performance of the proposed latch.

DOI： 10.23919/DATE56975.2023.10136927

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Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates 査読有り国際誌

Yan A., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland) 11 ( 10 ) 2022年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata is a novel nanotechnology that has the advantages of low energy dissipation, easy integration, and high computing speed. It is regarded as one of the powerful alternative technologies for the next generation of integrated circuits because of its unique implementation concept. In this paper, two XOR/XNOR gates are proposed. Level-sensitive T flip-flops, negative edge-trigger T flip-flops, two-to-one multiplexers, reversible gates, and (8, 4) polar encoders are implemented based on these two proposed logic gates. Simulation results show that, compared with the existing level-sensitive T flip-flops, the second proposed level-sensitive T flip-flop has fewer cells and lower energy dissipation; compared with the best (8, 4) polar encoder, the cell count and area of the second proposed (8, 4) polar encoder are decreased by 13.67% and 12.05%, respectively. The two XOR/XNOR gates have a stable output and low energy dissipation, which can be flexibly designed into complex quantum-dot cellular automata circuits.

DOI： 10.3390/ELECTRONICS11101658

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Evaluation and Test of Production Defects in Hardened Latches 査読有り国際誌

Ma R., Holst S., Wen X., Yan A., Xu H.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E105D ( 5 ) 996 - 1009 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (PTVF), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed PTVF metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.

DOI： 10.1587/transinf.2021EDP7216

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A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage 査読有り

Yan A., Dingl L., Zhou Z., Huang Z., Cui J., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2022-November 1 - 6 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With technology scaling down, the vulnerability of circuits to radiation and the increase of static power have become severe concerns. Spintronic devices such as magnetic tunnel junction (MTJ) have been developed to cope with many concerns, among which reliability concerns [1]. Spintronic devices have attractive properties, such as non-volatility and compatibility with conventional CMOS fabrication process. Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magnetic latch, namely M-TPDICE, that can completely tolerate single-node upsets (SNUs) and double-node upsets (DNUs). Simulations of the proposed latch with the HSPICE tool with a 45 nm CMOS technology model have demonstrated the effectiveness of the proposed latch.

DOI： 10.1109/ATS56056.2022.00013

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MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator 査読有り国際誌

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wen X.

Proceedings of the 2022 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2022 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the potential at the input flips too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses propagating in the circuit. We study the effect of jitter on the output of the XOR gate when the XOR gate has high-speed changing inputs. Excessively small short pulses will be eliminated in the circuit and suppresses the accumulation of jitter in the oscillator. Our proposed TRNG cleverly avoids the concatenation of the short pulses with the inverter so that the short pulses are only input to the XOR gate, affecting the oscillation of the circuit by interfering with the change of the XOR gate output by another input change. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA, making it comparable to the state-of-the-art TRNG also implemented on FPGAs. The results show that this TRNG has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.

DOI： 10.1109/AsianHOST56390.2022.10022291

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GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators 査読有り国際誌

Holst S., Bumun L., Wen X.

Proceedings of the Asian Test Symposium 2021-November 127 - 132 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Systolic arrays are currently used in autonomous systems such as self-driving cars to accelerate the enormous amount of matrix operations necessary for DNN inference. The reliability of such accelerators are of utmost importance since any loss in DNN accuracy due to erroneous calculations can have dire consequences. We propose a novel method to measure accuracy losses caused by arbitrary timing faults in systolic arrays. Our GPU-based simulation system enables for the first time a complete and accurate timing simulation of all inference-related matrix operations on large systolic arrays. A single consumer-grade GPU can simulate a LeNet-5 at a throughput of about 13s per inference. Furthermore, our simulation approach readily scales to larger DNNs and multiple GPUs.

DOI： 10.1109/ATS52891.2021.00034

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MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method 査読有り国際誌

Yan A., Li Z., Gao Z., Zhang J., Huang Z., Ni T., Cui J., Wang X., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43 ( 7 ) 2205 - 2214 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability of latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. In this article, we propose a novel latch, namely, MURLAV, protected against quadruple node-upsets (QNUs) induced in harsh radiation environments, as well as an algorithmic error-recovery verification method. The latch provides complete recovery from all QNUs with a formed redundant structure. The algorithm can simplify the verification process and demonstrate the QNU recovery for the proposed MURLAV latch. Simulation results demonstrate that the proposed latch can recover from any QNU and that it has lower area and delay overhead. Compared with existing latches of the same type, the proposed MURLAV latch achieves an overhead reduction of 34% in silicon area and 15% in delay on average at the cost of moderate power consumption.

DOI： 10.1109/TCAD.2024.3357593

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A new die-level flexible design-for-test architecture for 3D stacked ICs 査読有り国際誌

Zhang Q., Zhan W., Wen X.

Integration 97 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

DOI： 10.1016/j.vlsi.2024.102190

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Efficient design approaches to CMOS full adder circuits 査読有り国際誌

Yan A., Bao H., Jiang W., Cui J., Huang Z., Wen X.

Microelectronics Journal 149 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %.

DOI： 10.1016/j.mejo.2024.106235

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IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications 査読有り国際誌

Yan A., Dong C., Guo X., Song J., Cui J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 19 - 24 2024年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Modern powerful CMOS chips are usually highly integrated and implemented with aggressively shrunk technology nodes. In radiation environment, under charge-sharing mechanism, one particle striking can simultaneously impact multiple nodes causing double-node-upsets (DNUs) and triple-node-upsets (TNUs). In this paper, we propose an Interlocked Dual-circle Latch Design, namely IDLD, with low cost and TNU recovery for aerospace applications. IDLD consists of four transmission gates and twelve 2-input C-elements (CEs) implemented in 22nm CMOS process. Simulation results demonstrate the complete TNU recovery as well as cost-effectiveness for the proposed IDLD latch.

DOI： 10.1145/3649476.3658761

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A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors 査読有り国際誌

Xu H., Li J., Ma R., Liang H., Liu C., Wang S., Wen X.

IEEE Transactions on Device and Materials Reliability 24 ( 2 ) 302 - 312 2024年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations.

DOI： 10.1109/TDMR.2024.3386954

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FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell 査読有り国際誌

Yan A., Chen Y., Gao Z., Ni T., Huang Z., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 71 ( 4 ) 2299 - 2303 2024年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

The Von-Neumann memory wall bottleneck that keeps expanding is mainly caused by the frequent data transfer between the main memory and the processor. The processing in-memory (PiM) capabilities of emerging nonvolatile devices have the potential to partially alleviate the memory wall problem. In this brief, we use the ferroelectric field-effect transistor (FeFET), one of the emerging nonvolatile devices, to design a multifunctional processing in-memory cell, namely FeMPIM. It can perform multiple logic operations in computing mode as well as content searching in ternary content-addressable memory (TCAM) mode. Simulation results demonstrate the multifunctional capability of the proposed FeMPIM as well as its moderate overhead when compared with the complementary metal-oxide-semiconductor (CMOS) based and the existing FeFET-based devices.

DOI： 10.1109/TCSII.2023.3331267

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SwinT-ILT: Swin Transformer embedding end-To-end mask optimization model 査読有り国際誌

Xu H., Qi P., Tang F., Ma R., Liang H., Huang Z., Wen X.

Journal of Micro/Nanopatterning, Materials and Metrology 23 ( 1 ) 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Background: Resolution enhancement techniques (RETs) are widely used to improve the quality of masks in lithography flow. Optical proximity correction (OPC), such as inverse lithography technology (ILT), improves mask printability, but conventional ILT suffers from computational overhead. Advanced learning-based methods accelerate the optimization process, but the quality of its mask could be more satisfactory to academia and industry. Aim: To improve the quality of masks while accelerating the optimization process, we propose SwinT-ILT, an end-To-end ILT optimization framework embedded in the Swin Transformer. Approach: The framework consists of a feature extraction module and a feature construction module. Leveraging the Swin Transformer, the feature extraction module extracts deep features, and the feature construction module reconstruct masks based on in-depth features. To enhance the resolution of feature maps without introducing noise, we incorporate a pixel shuffle layer into the feature construction module. Furthermore, we set a specific training objective that introduces the domain knowledge of the imaging system, thereby accelerating the convergence. Results: Quantitative results show that our SwinT-ILT achieves exceptional mask printability with relative mask manufacturability in only 0.5 s turnaround time. Conclusions: Our work contributes to the industry by effectively reducing semiconductor manufacturing cycles and enhancing manufacturing quality.

DOI： 10.1117/1.JMM.23.1.013201

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Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS 査読有り国際誌

Yan A., Wang L., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32 ( 1 ) 116 - 127 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) are widely used to address these concerns. MTJs are nonvolatile (NV) and compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant and NV latch, i.e., M-TPDICE-V2, providing high reliability. In addition, we further propose an advanced latch, namely, M-8C, that is able to completely recover from single-node upsets (SNUs) and DNUs. M-8C uses a DNU recovery module and a backup and restore module based on a pair of MTJs. Furthermore, we propose a universal backup and restore module suitable for any latch providing nonvolatility. We simulate the proposed latches using the Synopsys HSPICE tool with a 45-nm CMOS process model. Simulation results confirm the superior capabilities of our proposed M-TPDICE-V2 and M-8C latches. M-TPDICE-V2 exhibits strong SNU and DNU tolerance and nonvolatility, while the M-8C latch provides complete DNU recovery capabilities.

DOI： 10.1109/TVLSI.2023.3323562

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NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization 査読有り国際誌

Huang Z., Sun L., Wang X., Liang H., Lu Y., Yan A., Pan J., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 60 ( 4 ) 4590 - 4600 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Multi-node upset induced by radiation on integrated circuits has caused many circuit reliability issues. This paper proposes a single-event quadruple-node upset recovery latch (NEST), based on 4 circular feedback loops that are formed by 25 C-elements to realize high robustness. NEST achieves 29.02% reduction in power consumption compared to the LDAVPM latch and 51.44% reduction in setup time compared to the QRHIL latch. NEST also achieves a 99.29% quadruple-node upset recovery rate. Furthermore, a high-speed, high-precision optimization algorithm for multi-node upset recovery is also proposed and implemented. This algorithm achieves 99.84% reduction in simulation time for exhaustive fault injections having equivalent accuracy with HSPICE.

DOI： 10.1109/TAES.2024.3379962

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