研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 121 - 140 件目／全件表示 >>

On Optimal Power-Aware Path Sensitization 査読有り国際誌

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian

Workshop of Test and Reliability for Circuits and Systems 2017年03月

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding 査読有り国際誌

D. Xiang., X. Wen, L.-T. Wang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 ( 3 ) 942 - 953 2017年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach.

DOI： 10.1109/TVLSI.2016.2606248

Scopus

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Vernier ring based pre-bond through silicon vias test in 3D ICs 査読有り国際誌

Ni T., Nie M., Liang H., Bian J., Xu X., Fang X., Huang Z., Wen X.

IEICE Electronics Express ( 一般社団法人電子情報通信学会 ) 14 ( 18 ) 20170590 - 20170590 2017年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.

DOI： 10.1587/elex.14.20170590

Scopus

CiNii Article

CiNii Research

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Logic-Path-and-Clock-Path-Aware at-Speed Scan Test Generation 査読有り国際誌

F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara

International Symposium on Applied Engineering and Sciences 2016年12月

Logic-path-and-clock-path-aware at-speed scan test generation 査読有り国際誌

Li F., Wen X., Miyase K., Holst S., Kajihara S.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人電子情報通信学会 ) E99A ( 12 ) 2310 - 2319 2016年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power- safety without significant test vector count inflation and test quality loss.

DOI： 10.1587/transfun.E99.A.2310

Scopus

CiNii Article

CiNii Research

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A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST 査読有り国際誌

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Asian Test Symposium 203 - 208 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.

DOI： 10.1109/ATS.2016.59

Kyutacar

Scopus

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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test 査読有り国際誌

S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H. Wunderlich, M. Kochte

IEEE Asian Test Symposium 19 - 24 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.

DOI： 10.1109/ATS.2016.49

Scopus

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On Optimal Power-Aware Path Sensitization 査読有り国際誌

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian

IEEE Asian Test Symposium 179 - 184 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

Detailed knowledge of a circuit's timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit's inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls the switching activity in the circuit region surrounding the path. The procedure can maximize or minimize switching activity, or set it to a user-specified value. We study the accuracy-vs.-efficiency trade-offs for a hierarchy of timing models, from coarse zero-delay assumption to a waveformaccurate approach with sub-cycle resolution. For the first time, we present a MaxSAT formulation which guarantees maximization or minimization of switching activity, stemming from transitions and from glitches, simultaneously with path sensitization. We validate the quality of the generated test patterns using a mixed-mode IR-drop-aware timing simulator.

DOI： 10.1109/ATS.2016.63

Scopus

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Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test 査読有り国際誌

S. Eggersglub, S. Holst, D. Tille, K. Miyase, X. Wen

IEEE Asian Test Symposium 173 - 178 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

Launch-Switching-Activity (LSA) is a serious problem during at-speed testing of integrated circuits, since localized LSA may lead to severe IR-drop and thus failures. The excessive LSA is conventionally mitigated by reducing the switching activity through special low-power test generation techniques, typically resulting in severe test pattern inflation and high test costs. This work introduces a novel concept of Low-Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power (HCP) regions. LCP-TPs also help in retaining high test compaction capability. An optimization- SAT based procedure is proposed to compute a small set of optimal LCP-TP locations for compact at-speed test sets with effective capture power reduction. Experimental results clearly demonstrate the advantages of LCP-TP insertion.

DOI： 10.1109/ATS.2016.41

Scopus

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Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures 査読有り国際誌

T. Chen, D. Shen, X. Yi, H. Liang, X. Wen

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E99D ( 11 ) 2672 - 2681 2016年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2016 The Institute of Electronics, Information and Communication Engineers.Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

DOI： 10.1587/transinf.2015EDP7289

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Power-Aware Testing For Low-Power VLSI Circuits 招待有り査読有り国際誌

X. Wen

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings 585 - 588 Paper S37-1 2016年10月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Hangzhou 2016年10月25日 - 2016年10月28日

© 2016 IEEE. Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely heat, false failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research topics in this field will also be discussed.

DOI： 10.1109/ICSICT.2016.7998986

Kyutacar

Scopus

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Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016-September 679 - 684 2016年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA Pittsburgh 2016年07月11日 - 2016年07月13日

© 2016 IEEE.Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys), called κ-TX. κ-TX corrects up to κ-bit flip errors and significantly enhances the tolerance of the TCAM against soft errors, where κ is the maximum number of bit flips in a word of a TCAM. κ-TX consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and an ECC-SRAM. First, κ-TX randomly selects a search key. After that, κ-TX detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and κ-TX refreshes the TCAM words by using a backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of κ-TX outperforms other schemes significantly. Moreover, the hardware overhead of k-TX is small due to the use of only a single TCAM. κ-TX can be easily implemented and is useful for fault-tolerant packet classifiers.

DOI： 10.1109/ISVLSI.2016.77

Scopus

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SAT-Based Post-Processing for Regional Capture Power Reduction in at-speed scan test generation 査読有り国際誌

S. Eggersgluss, K. Miyase, X. Wen

IEEE European Test Symposium 2016-July 2016年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Netherlands Amsterdam 2016年05月23日 - 2016年05月27日

© 2016 IEEE.With more and more sophisticated low-power design techniques being applied to modern LSI chips for aggressive functional power reduction, the risk of fault-free chips falsely failing production test grows due to excessively high test power compared with functional power. Existing low-power ATPG methods, however, suffer from severe test data inflation and often use unfocused global test power reduction. This paper proposes a novel optimization-SAT-based at-speed scan test generation method that is explicitly targeted at eliminating high-capture-power test vectors in a pre-generated compact test set. This method employs layout information in reducing capture switching activity in a focused regional manner. Experiments demonstrate that the proposed method can effectively eliminate a large number of high-capture-power test vectors with neither test data inflation nor fault coverage loss.

DOI： 10.1109/ETS.2016.7519327

Scopus

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Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill 査読有り国際誌

D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35 ( 3 ) 499 - 512 2016年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE.At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.

DOI： 10.1109/TCAD.2015.2474365

Scopus

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Test Pattern Modification for Average IR-Drop Reduction 査読有り国際誌

W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen

IEEE Transactions on VLSI Systems 24 ( 1 ) 38 - 49 2016年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern. We propose a fast average IR drop estimation, which is very close to the time-averaged IR drop of time-consuming transient simulation (R2 =0.99). We calculate the contribution of every node to these nodes inside IR-drop hotspot so that we can effectively modify only a few don't care bits in the test patterns to reduce IR drop. The experimental results show that our technique successively reduces time-averaged IR drop by 10% with almost no fault coverage loss and no test pattern inflation.

DOI： 10.1109/TVLSI.2015.2391291

Scopus

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Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch 査読有り国際誌

K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian

IEEE Asian Test Symposium 103 - 108 2015年11月

Power Supply Noise and Its Reduction in At-Speed Scan Testing 招待有り査読有り国際誌

X. Wen

IEEE International Conference on ASIC Paper B5-3 2015年11月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Chengdu 2015年11月03日 - 2015年11月06日

Scan testing tends to cause excessive switching activity in an LSI circuit, incurring significant power supply noise with severe impact on its timing. This may lead to over-test or under-test, resulting in test yield loss or low test quality. This paper describes the issue of power supply noise in at-speed scan testing, introduces typical techniques for its reduction, and discusses some important future research topics.

DOI： 10.1109/ASICON.2015.7516980

Scopus

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A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

24th International Workshop on Logic and Synthesis 2015年06月

Identification of High Power Consuming Areas with Gate Type and Logic Level Information 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE European Test Symposium Paper 9.1 2015年05月

A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE European Test Symposium Poster 2.4 2015年05月

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論文 - 温　暁青