研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 121 - 140 件目／全件表示 >>

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications 査読有り国際誌

Yan A., Xiang J., Cao A., He Z., Cui J., Ni T., Huang Z., Wen X., Girard P.

IEEE Transactions on Device and Materials Reliability 22 ( 2 ) 282 - 295 2022年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead.

DOI： 10.1109/TDMR.2022.3175324

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Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications 査読有り国際誌

Yan A., Fan Z., Ding L., Cui J., Huang Z., Wang Q., Zheng H., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 58 ( 1 ) 517 - 529 2022年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this article also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2, 32.8, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called high-impedance state-insensitive, TNU-tolerant, and SET-filterable latch can reduce delay, power, and area by 78.9, 15.8, and 28.6%, respectively, compared with the state-of-the-art TNU hardened latch.

DOI： 10.1109/TAES.2021.3103586

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A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications 査読有り国際誌

Yan A., Qian K., Cui J., Cui N., Huang Z., Wen X., Girard P.

Proceedings of the IEEE VLSI Test Symposium 2022-April 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In space, the impact of radiative particles, such as neutrons and heavy ions, can change the node states of a flip-flop, thus resulting in loss of data. In this paper, a Highly reliable and Low power Radiation-hardened-by-design (RHBD) Flip-Flop cell, namely HLRFF, completely hardened against double-node-upsets (DNUs), is proposed for aerospace applications. The HLRFF is a master-slave structure. The master latch is mainly constructed from two 2-input C-elements (CEs) and one 2-input clock-gating based CE, while the slave latch has an additional keeper at the output stage. The verification results demonstrate that the proposed HLRFF is completely DNU-tolerant. Furthermore, compared to the state-of-the-art radiation-hardened FF cells, the proposed HLRFF can reduce power consumption by approximately 69%. However, only the proposed HLRFF is not only completely DNU-tolerant but also insensitive to high-impedance-state.

DOI： 10.1109/VTS52500.2021.9794197

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SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Huang S., Zhai Z., Cheng X., Cui J., Ni T., Wen X., Girard P.

Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 1257 - 1262 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the CMOS technology is continuously scaling down, nano-scale integrated circuits are becoming susceptible to harsh-radiation induced soft errors, such as double-node upsets (DNUs) and triple-node upsets (TNUs). This paper presents a shuttle C-elements based low-cost and robust latch (namely SCLCRL) that can recover from any TNU in harsh radiation environments. The latch comprises seven primary storage nodes and seven secondary storage nodes. Each pair of primary nodes feeds a secondary node through one C-element (CE) and each pair of secondary nodes feeds a primary node through another CE, forming redundant feedback loops to robustly retain values. Simulation results validate all key TNUs' recoverability features of the proposed latch. Simulation results also demonstrate that the proposed SCLCRL latch can approximately save 29% silicon area and 47% D-Q delay on average at the cost of moderate power, compared with the state-of-the-art TNU-recoverable reference latches of the same-type.

DOI： 10.23919/DATE54114.2022.9774665

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Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments 査読有り国際誌

Yan A., Xu Z., Feng X., Cui J., Chen Z., Ni T., Huang Z., Girard P., Wen X.

IEEE Transactions on Emerging Topics in Computing 10 ( 1 ) 404 - 413 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.

DOI： 10.1109/TETC.2020.3025584

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Broadcast-TDMA: A Cost-Effective Fault Tolerance Method for TSV Lifetime Reliability Enhancement 査読有り国際誌

Ni T., Bian J., Yang Z., Nie M., Yao L., Huang Z., Yan A., Wen X.

IEEE Design and Test 39 ( 5 ) 34 - 42 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Electromigration and time-dependent dielectric breakdown induced through-silicon-via (TSV) aging, along with TSV thermal issues including thermo-mechanical stress and thermal cycling, may result in failure and affect the lifetime reliability of TSV. This paper proposes a cost-effective fault tolerance method for TSV lifetime reliability enhancement. In a honeycomb TSV group formed by six TSVs without the utilization of redundant TSVs, any faulty TSV can be bypassed and broadcasted to any other TSVs in the same group. The cost-effectiveness of the proposed fault tolerance method has been evaluated based on the IWLS’05 3D benchmark circuits using 45nm open cell library. Experimental results show that the proposed method has the highest lifetime reliability compared with state-of-art router-based, ring-based, and chain-TDMA based solutions for lifetime reliability enhancement, and the lifetime reliability of the proposed scheme can still remain more than 90% even at 10 years. Furthermore, compared with the methods mentioned above, the proposed method can achieve 34.05%~58.56%, 29.46%~55.55%, 4.75%~39.84% reductions in hardware overhead, respectively. All these promising attributes can facilitate this proposed architecture’s adoption in 3D IC designs.

DOI： 10.1109/MDAT.2022.3189827

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Power-Aware Testing in the Era of IoT 査読有り国際誌

Wen X.

Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022 2022年01月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

IoT devices are increasingly employed in various applications. Due to their intrinsic power supply limitation, IoT devices are usually designed with extremely low functional power dissipation. However, the testing of IoT devices has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper highlights the impact of excessive scan test power and points out the importance of power-aware testing for IoT devices.

DOI： 10.1109/ICSICT55466.2022.9963241

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Power and Energy Safe Real-Time Multi-Core Task Scheduling 査読有り国際誌

Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 16 - 21 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scheduling tasks in multi-core real-time systems (e.g. low power devices/appliances) while keeping energy in mind is a difficult design challenge. Extensive work has been done to overcome this issue, in which task instances (jobs) have varying levels of operation power. Different combinations of system energy (SE) and subsequent minimal SE have been attained based on the power levels. However, both system power (SP) and system energy (SE) are expensive to operate. As a result, task scheduling for multi-core systems based on balancing both the SP and the SE (referred to as feasible SP and feasible SE, respectively) to achieve the lowest system cost is an issue that has not been adequately addressed in the literature. The states or zones of feasible SP (FSP) and feasible SE (FSE) are thought to be possible zones/states of the system where the system's power configuration provides lowered SE with increased job accommodation, lowering the system's cost. We offer a unique scheduling approach in which we identify numerous FSP and FSE zones (feasible zones/states) to fit all jobs to cores while minimising system cost (including optimum cost) and meeting deadlines. By giving weights to the FSP and FSE, we present a mechanism for ranking the many viable system states. The model is tested using produced task sets (low power task sets), and the results reveal that our approach effectively finds feasible zones, including the best one.

DOI： 10.1109/VLSID2022.2022.00016

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Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits 査読有り国際誌

Utsunomiya T., Hoshino R., Miyase K., Lu S.K., Wen X., Kajihara S.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 43 - 48 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

High power consumption in LSI testing may cause excessive IR-drop. When IR-drop becomes excessive, it causes excessive delay, resulting in test malfunction (over-testing). Excessive IR-drop does not occur in the entire area of a circuit, but in certain areas where a large number of switching activities occur (such areas are called hotspots in this work). In order to avoid test malfunction, it is important to develop a method to reduce or control IR-drop in the hotspots. Locating hotspots is a necessary technique to reduce or control IR-drop effectively and efficiently. In this work, we propose a method to locate hotspots in a logic circuit by switching probability calculation. Experimental results for IWLS2005 OpenCores circuits demonstrate the proposed method can support to locate hotspots.

DOI： 10.1109/ITCAsia55616.2022.00018

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Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS 査読有り国際誌

Yan A., Song S., Zhang J., Cui J., Huang Z., Ni T., Wen X., Girard P.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 73 - 78 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the aggressive reduction of CMOS transistor feature sizes, the soft error rate of nano-scale integrated circuits increases exponentially. In this paper, we propose a novel cost-optimized and robust latch, namely CRLHQ, hardened against quadruple-node-upsets (QNUs) for nanoscale CMOS technologies. The latch mainly comprises a 5×5 matrix based on interlocked source-drain cross-coupled inverters to robustly store logic values. Owing to the redundant constructed feedback loops, the latch can recover from all possible QNUs. Simulation results demonstrate all key QNUs' recovery of the proposed CRLHQ latch. Simulation results also show that the proposed latch can approximately reduce the D-Q delay by 44.3%, the silicon area by 7.3% and the delay-area-power product (DAPP) by 14.2%, compared with the state-of-the-art same-type reference latches that can recover from any QNU.

DOI： 10.1109/ITCAsia55616.2022.00023

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A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters 査読有り国際誌

Yan A., Song S., Chen Y., Cui J., Huang Z., Wen X.

Proceedings of the IEEE Conference on Nanotechnology 2022-July 215 - 218 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel low-cost and robust latch, namely LRLPT, protected against triple-node upsets (TNUs) in nano-scale CMOS. The storage part of the latch comprises interlocked source-drain cross-coupled inverters forming redundant feedback loops to robustly store values. Simulation results demonstrate all key TNUs' recovery of the proposed latch. Simulation results also demonstrate that the proposed latch can save 69.67% delay, 37.51% silicon area and 71.77% delay-area-power product (DAPP) compared to the state-of-the-art TNU-recovery reference latch of the same-type.

DOI： 10.1109/NANO54668.2022.9928674

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A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC 査読有り国際誌

Ni T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40 ( 9 ) 1952 - 1956 2021年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%-99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%-86.85% (46.01%-55.96%), 66.89%-73.25% (29.41%-38.49%), 68.02%-74.20% (41.40%-52.20%), 60.60%-68.18% (18.09%-33.18%), and 75.86%-80.52% (3.05%-20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay.

DOI： 10.1109/TCAD.2020.3025169

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Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications 査読有り国際誌

Yan A., Cao A., Xu Z., Cui J., Ni T., Girard P., Wen X.

Journal of Electronic Testing: Theory and Applications (JETTA) 37 ( 4 ) 489 - 502 2021年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

DOI： 10.1007/s10836-021-05962-0

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A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments 査読有り

Yan A., Cao A., Fan Z., Xu Z., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 301 - 306 2021年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state (HIS) insensitive latch design, namely QRHIL, for highly robust computing in harsh radiation environments. The latch mainly comprises a 5×5 looped C-element matrix to store values and provide complete 4NU recovery. Owing to the multiple-level error-interception of the 5×5 C-element matrix, the latch can recover from all possible 4NUs; thus, the latch is insensitive to HIS. Simulation results demonstrate the 4NU-recovery of the proposed latch. The results also show that the latch can approximately save 46% D-Q delay and 46% CLK-Q delay owing to the use of a high-speed D-Q path and clock-gating, compared with the state-of-the-art 3NU-recoverable latch (TNURL) that is not 4NU-recoverable.

DOI： 10.1145/3453688.3461493

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Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications 査読有り

Yan A., He Z., Zhou J., Cui J., Ni T., Huang Z., Wen X., Girard P.

Microelectronics Journal 111 2021年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

DOI： 10.1016/j.mejo.2021.105034

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A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology 査読有り

Ni T., Yang Z., Chang H., Zhang X., Lu L., Yan A., Huang Z., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 2 ) 724 - 734 2021年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

Through-silicon-vias (TSVs) are prone to defects during the manufacturing process, which pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is too great to be ignored, and in order to not use any redundant TSVs, a chain-type time division multiplexing access (TDMA)-based fault tolerance technique is proposed. However, a double-TSV structure is used per group, resulting in a significant TSV hardware overhead under a given large-scaled circuit design. Furthermore, it is impossible for the chain-TDMA scheme to plan the rerouting path for the right-hand-most TSV per group, resulting in a decrease in the repair rate per TSV group as well as in the whole TSV yield. In the proposed technique, we bundle six TSVs per group in a honeycomb pattern and the TSVs on the edges are connected to each other, enhancing the repair rate per group as well as the whole TSV yield. Subsequently, an architecture based on the proposed technique is designed, evaluated, and validated on logic-on-logic 3D IWLS'05 benchmark circuits using 45 nm TSMC technology. The proposed technique is found to reduce the area overhead by 87.95-90.42 percent, compared to the chain-TDMA scheme, which results in a yield of 96.90-99.09 percent.

DOI： 10.1109/TETC.2020.2969237

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Reliability-Driven Neuromorphic Computing Systems Design 査読有り

Xu Q., Wang J., Geng H., Chen S., Wen X.

Proceedings -Design, Automation and Test in Europe, DATE 2021-February 1586 - 1591 2021年02月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have provided a promising solution to the acceleration of neural networks. However, stuck-at faults (SAFs) in the memristor devices significantly degrade the computing accuracy of NCS. Besides, memristors suffer from process variations, causing the deviation of actual programming resistance from its target resistance. In this paper, we propose a novel reliability-driven design framework for a memristive crossbar-based NCS in combination with general and chip-specific design optimizations. First, we design a general reliability-aware training scheme to enhance the robustness of NCS to SAFs and device variations; a dropout-inspired approach is developed to alleviate the impact of SAFs; a new weighted error function, including cross-entropy error (CEE), the l2-norm of weights, and the sum of squares of first-order derivatives of CEE with respect to weights, is proposed to obtain a smooth error curve, where the effects of variations are suppressed. Second, given the neural network model generated by the reliability-aware training scheme, we exploit chip-specific mapping and retraining to further reduce the computation accuracy loss incurred by SAFs. Experimental results clearly demonstrate that the proposed method can boost the computation accuracy of NCS and improve the NCS robustness.

DOI： 10.23919/DATE51398.2021.9473929

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Preface 査読有り国際誌

Wen X., Liou J.J.

Journal of Physics Conference Series 1729 ( 1 ) 2021年01月

Cellular Structure Based Fault-Tolerance TSV Configuration in 3D-IC 査読有り国際誌

Xu Q., Sun W., Chen S., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 5 ) 1196 - 1208 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement. But the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this paper, we propose an effective TSV repair strategy for the cellular TSV redundancy architecture, with taking account of the delay overhead. First, we prove that the cellular structure-based fault-tolerance TSV configuration with the delay constraint (CSFTC) is equivalent to the length-bounded multi-commodity flow (LBMCF) problem. Next, an integer linear programming formulation is presented to solve the LBMCF problem. Finally, to speed-up the fault-tolerance structure configuration process, an efficient Lagrangian relaxation based heuristic method is further proposed. Experimental results demonstrate that, compared with the state-of-the-art fault-tolerance structures, the proposed method can provide high yield and low delay overhead.

DOI： 10.1109/TCAD.2021.3084920

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85107326845&origin=inward

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS 査読有り

Yan A., Lai C., Zhang Y., Cui J., Huang Z., Song J., Guo J., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 1 ) 520 - 533 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39 percent and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

DOI： 10.1109/TETC.2018.2871861

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85054282771&origin=inward

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