研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 141 - 160 件目／全件表示 >>

TPDICE and SIM based 4-node-upset completely hardened latch design for highly robust computing in harsh radiation 査読有り

Yan A., Ding L., Shan C., Cai H., Chen X., Wei Z., Huang Z., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2021-May 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Technology scaling and charge-sharing make nano-scale CMOS latches become severely vulnerable to multiple-node upsets (MNUs). This paper proposes a triple-path dual-interlocked-storage-cell (TPDICE) and soft-error interceptive module (SIM) based 4-Node-Upset (4NU) completely hardened latch, namely 4NUHL latch, that can completely tolerate soft errors, such as 4NUs. The latch mainly consists of 2 TPDICEs and a 3-level SIM which comprises six 2-input C-elements. Owing to the single-node-upset self-recoverability and multiple storage nodes of TPDICEs and the soft-error interception capability of the SIM, the latch can provide complete 4NU tolerance. Simulation results demonstrate that the proposed 4NUHL latch is completely 4NU hardened. Furthermore, we use a high-speed path, clock-gating, and a few transistors to reduce overhead of the proposed latch. We compared the proposed latch with state-of-the-art hardened latches in terms of reliability and overhead to demonstrate the advantages of the proposed latch.

DOI： 10.1109/ISCAS51556.2021.9401453

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On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption 査読有り国際誌

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E104D ( 6 ) 816 - 827 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

DOI： 10.1587/transinf.2020EDP7042

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Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing 査読有り国際誌

Yan A., Zhai Z., Wang L., Zhang J., Cui N., Ni T., Wen X.

Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of design and manufacturing technologies of nano-scale CMOS circuits, latches are becoming increasingly sensitive to multiple-node-upsets caused by harsh radiation effects. In this paper, a Parallel Dual-interlocked-storage-cells (DICEs) and Dual-level C-elements (CEs) based 3-node-upset (3NU)-Tolerant Latch, namely PDDCTL, design for highly robust computing, is proposed. The latch comprises five transmission gates, two DICEs and three CEs. Due to the use of two single-node-upset self-recoverable DICEs and three error-interceptive CEs, the latch can provide complete 3NU-tolerance with low cost. Simulation results not only confirm the 3NU-tolerance of the proposed latch but also demonstrate that the delay-power-area product of the PDDCTL latch is reduced by 68.82% on average compared with the state-of-the-art 3NU hardened latch designs.

DOI： 10.1109/ITC-Asia53059.2021.9808602

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LSI Testing: A Core Technology to a Successful LSI Industry 招待有り査読有り国際誌

Wen X.

Proceedings of International Conference on ASIC 2021年01月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Despite its ever-growing importance in all innovation fields, such as automotive and IoT applications, the LSI industry is fragile due to its a weak technology-business chain. In addition, its products, namely LSI chips, are vulnerable to six risks (defective chip escape, radiation, aging, malicious attack, counterfeiting). LSI testing is the technology that is indispensable to mitigate these risks. This paper highlights the intent of LSI testing as well as its impact on the LSI industry.

DOI： 10.1109/ASICON52560.2021.9620418

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GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning 査読有り国際誌

Xu Q., Geng H., Chen S., Yuan B., Zhuo C., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3492 - 3502 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Electronic Design Automation (EDA) comprises a series of computationally difficult optimization problems that require substantial specialized knowledge as well as a considerable amount of trial-and-error efforts. However, open challenges including long simulation runtime and lack of generalization continue to restrict the applications of existing EDA tools. Recently, learning-based algorithms especially reinforcement learning (RL) have been successfully applied to handle various combinatorial optimization problems by automatically acquiring knowledge from the past experience. In this paper, we formulate the floorplanning problem, the first stage of the physical design flow, as a Markov Decision Process (MDP). An end-toend learning-based floorplanning framework GoodFloorplan is proposed to explore the design space, which combines graph convolutional network (GCN) and RL. Experimental results demonstrate that, compared with state-of-the-art heuristic-based floorplanners, the proposed GoodFloorplan can provide better area and wirelength.

DOI： 10.1109/TCAD.2021.3131550

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Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure 査読有り国際誌

Xu Q., Ni T., Geng H., Chen S., Yu B., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3182 - 3187 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this paper, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration with the delay constraint (RFSC) is equivalent to the length-bounded multi-commodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. Experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead.

DOI： 10.1109/TCAD.2021.3133484

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A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch 査読有り国際誌

Yan A., Qian K., Cui J., Cui N., Ni T., Huang Z., Wen X.

2021 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As transistor feature sizes continue to scale down, the susceptibility of integrated circuits to harsh-radiation induced multiple-node-upsets (MNUs),such as double-node upsets (DNUs) and triple-node upsets (TNUs), is increasing. This paper presents an MNU self-recoverable hardened latch (namely SCDMSH) based on sextuple cross-coupled dual-interlocked-storage-cells (DICEs). The latch consists of eight transmission gates and six interlocked DICE cells. Due to the interlocking mechanism constructed from single-node-upset-self-recoverable DICE cells, the latch can self-recover from any possible single node upset (SNU), DNU and TNU. Simulation results validate the SNU, DNU and TNU self-recoverability of the proposed latch. Simulation results also demonstrate that the SCDMSH latch can approximately save 49% silicon area at the cost of moderate delay and power, compared with the state-of-the-art TNU self-recoverable reference latch (TNURL) of the same-type.

DOI： 10.1109/NANOARCH53687.2021.9642250

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A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets 査読有り国際誌

Yan A., Cao A., Qian K., Ding L., He Z., Fan Z., Wen X.

Proceedings - 2021 8th International Conference on Dependable Systems and Their Applications, DSA 2021 734 - 736 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a flip-flop (FF) that can tolerate double-node-upsets (DNUs). If the FF suffers from a DNU, it can still have a correct value on its output node. Simulation results demonstrate the FF's DNU tolerance, and also demonstrate that the proposed FF can save 92% delay, 55% power, and 28% area on average, compared to typical DNU hardened FFs, respectively.

DOI： 10.1109/DSA52907.2021.00108

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Novel Speed-and-Power-Optimized SRAM Cell Designs with Enhanced Self-Recoverability from Single- And Double-Node Upsets 査読有り国際誌

Yan A., Chen Y., Hu Y., Zhou J., Ni T., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 12 ) 4684 - 4695 2020年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

The continuous advancement of CMOS technologies makes SRAMs more and more sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-node upsets (DNUs). First, the S4P8N cell that has more redundant nodes and more access transistors is proposed. The cell has the following advantages: (1) it can self-recover from all possible SNUs; (2) it can self-recover from a part of DNUs; (3) it has small overhead in terms of power dissipation. Then, to reduce read and write access time, the S8P4N cell that uses a special feedback mechanism among its internal nodes is proposed. The cell has similar soft error tolerability as the S4P8N cell. Simulation results validate the high robustness of the proposed SRAM cells. These results also show that the write access time, read access time, and power dissipation of the S8P4N cell are reduced approximately by 29%, 20%, and 21% on average, at the cost of moderate silicon area, when compared with the state-of-the-art radiation-hardened SRAM cells.

DOI： 10.1109/TCSI.2020.3018328

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A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets 査読有り

Yan A., Chen Y., Zhou J., Cui J., Ni T., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2020-November 2020年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can provide self-recoverability from any single-node upsets (SNUs) and partial double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of six access transistors. Simulation results show that the SCCS18T cell can save approximately 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with typical hardened SRAM cells.

DOI： 10.1109/ATS49688.2020.9301569

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Logic Fault Diagnosis of Hidden Delay Defects 査読有り

Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

Proceedings - International Test Conference 2020-November 2020年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

DOI： 10.1109/ITC44778.2020.9325234

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Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC 査読有り国際誌

Ni T., Chang H., Song T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 67 ( 11 ) 2657 - 2661 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In this brief, a non-invasive online solution for 2.5D IC based on distributed pulse shrinking is proposed to test the faults of interconnects. Furthermore, a regression model based on artificial neural network (ANN) is proposed in order to judge whether the interconnects are faulty and quantify the degree of the faults in real time by online monitoring the delay of interconnects. Experiments on defect detection are presented through HSPICE simulation with realistic models for 45nm CMOS technology. The results show that the proposed method has features including: high resolution, low area overhead, high robustness, and be able to predict the class and the fault size.

DOI： 10.1109/TCSII.2019.2962824

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Design of double-upset recoverable and transient-pulse filterable latches for low-power and low-orbit aerospace applications 査読有り

Yan A., Chen Y., Xu Z., Chen Z., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 5 ) 3931 - 3940 2020年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a singleevent Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhancedversion of theDURTPF latch, namelyDURTPF-EV.TheDURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost ofmoderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.

DOI： 10.1109/TAES.2020.2982341

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Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors 査読有り

Dou Z., Yan A., Zhou J., Hu Y., Chen Y., Ni T., Cui J., Girard P., Wen X.

Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 35 - 40 2020年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

DOI： 10.1109/ITC-Asia51099.2020.00018

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A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications 査読有り

Yan A., Xu Z., Yang K., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 4 ) 2666 - 2676 2020年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node upsets (TNUs) are becoming more and more an issue in storage cells used for applications constrained by their environment, such as aerospace applications confronted to radiations. This article presents a novel triple-modular redundancy without voter based high-impedance state (HIS) insensitive and MNU-tolerant latch design, namely TMHIMNT, to ensure both high reliability and low cost. The TMHIMNT latch mainly comprises triple clock-gating (CG) based dual-interlocked-storage-cells (DICEs) and four inverters. Through three internal inverters, the values stored in DICEs converge to a common node feeding an output-level inverter, enabling the TMHIMNT latch to tolerate any possible MNU. Simulation results demonstrate the MNU tolerance of the proposed TMHIMNT latch. Due to the disuse of C-elements, the proposed TMHIMNT latch is insensitive to the HIS, making the latch more reliable for aerospace applications. Moreover, compared with the state-of-the-art TNU hardened latch, due to the use of a high-speed path, CG technologies, and fewer transistors, the proposed TMHIMNT latch can achieve 98% delay, 17% power, and 29% area reductions, respectively.

DOI： 10.1109/TAES.2019.2951186

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HITTSFL: Design of a cost-effective HIS-Insensitive TNU-Tolerant and SET-Filterable latch for safety-critical applications 査読有り

Yan A., Feng X., Zhao X., Zhou H., Cui J., Ying Z., Girard P., Wen X.

Proceedings - Design Automation Conference 2020-July 2020年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a cost-effective, high-impedance-state (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storage-cells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-the-art TNU hardened latch (TNUHL) that cannot filter SETs.

DOI： 10.1109/DAC18072.2020.9218704

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Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment 査読有り

Yan A., Hu Y., Cui J., Chen Z., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computers 69 ( 6 ) 789 - 799 2020年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

DOI： 10.1109/TC.2020.2966200

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Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments 査読有り

Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 2 ) 1163 - 1171 2020年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

In harsh radiation environments, nanoscale CMOS latches have become more and more vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm CMOS technology. The proposed latch is mainly constructed from seven mutually feeding-back soft-error-interceptive modules (SIMs), any of which consists of two three-input C-elements and one two-input C-element. Due to the mutual feedback mechanism of SIMs and the dual-level soft-error interception of each SIM, the latch can self-recover from any possible TNU. Simulation results demonstrate the TNU self-recoverability from any key TNU for the proposed latch using redundant silicon area. Furthermore, using a high-speed path, the proposed latch saves about 95.45% transmission delay and 86.97% delay-power-area product, compared with the state-of-the-art TNU-tolerant latch that cannot provide complete TNU self-recoverability at all.

DOI： 10.1109/TAES.2019.2925448

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Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs 査読有り国際誌

Yan A., Ling Y., Cui J., Chen Z., Huang Z., Song J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 3 ) 879 - 890 2020年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

DOI： 10.1109/TCSI.2019.2959007

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Dual-interlocked-storage-cell-based double-node-upset self-recoverable flip-flop design for safety-critical applications 査読有り

Yan A., Xu Z., Cui J., Ying Z., Huang Z., Liang H., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2020-October 2020年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a novel dual-interlocked storage-cell (DICE)-based double-node-upset (DNU) self-recoverable, namely DURI-FF, in the nano-scale CMOS technology. The master latch of the DURI-FF cell consists of three transmission gates (TGs) and three interlocked DICEs with three common nodes. The common nodes are connected to TGs for value initialization. The slave latch of the DURI-FF cell comprises six TGs, six inverters and three interlocked DICEs. The outputs of the inverters respectively feed the internal nodes of the slave latch. The interlocked DICEs make the master latch and the slave latch DNU self-recoverable. Simulation results validate the DNU self-recoverability of the proposed DURI-FF cell. Moreover, compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85102840573&origin=inward

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