研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 141 - 160 件目／全件表示 >>

GPU-Accelerated Small Delay Fault Simulation 査読有り国際誌

E. Schneider, S. Holst, M.-A. Kochte, X. Wen, H.-J. Wunderlich

Design and Test in Europe 1174 - 1179 2015年03月

Towards Memory-Aware VLSI Simulation Algorithms for Heterogeneous Architectures 査読有り国際誌

S. Holst, J. Miyazaki, X. Wen

International Symposium on Applied Engineering and Sciences 2014年12月

Soft-Error Tolerant TCAMs for High-Reliability Packet Classification 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE Asia Pacific Conference on Circuits and Systems 471 - 474 2014年11月

Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り国際誌

E. Schneider, S. Holst, X. Wen, H. Wunderlich

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD 17 - 23 2014年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA San Jose 2014年11月02日 - 2014年11月06日

© 2014 IEEE.Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate timesimulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.

DOI： 10.1109/ICCAD.2014.7001324

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84936860899&origin=inward

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り国際誌

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEICE Transactions on Information and Systems E97 ( 10 ) 2706 - 2718 2014年10月

低キャプチャ電力スキャンテスト生成のためのX埋め込み手法

李富強, 温暁青, 宮瀬紘平, ホルストシュテファン, 梶原誠司

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 ( 一般社団法人電子情報通信学会 ) 114 ( 99 ) 15 - 20 2014年06月

記述言語：英語掲載種別：研究論文（研究会，シンポジウム資料等）

低キャプチャ電力のスキャンテストパターンを生成するため,セルの実効電圧降下(IR-Drop)との関わりの強いローカル信号値遷移量(LSA:Local Switching Activity)を抑えるX埋め込み手法を提案する.この手法では,レイアウトレベルの回路を単位区域に分割した上,各単位区域の遷移量を示すLSAによってテストキューブ中のXビットの優先順位を決めて,伝搬しやすい値を最適論理値として順次Xビットに割り当てる.実験結果によって,提案手法がLSAを効果的に低減できることが示された.

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/110009925706

Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り国際誌

E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

ACM Design Automation Conference Poster 2014年06月

Low-power testing for 2D/3D devices and systems 査読有り国際誌

Lin X., Wen X., Xiang D.

Design of 3D Integrated Circuits and Systems 235 - 277 2014年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2015 by Taylor & Francis Group, LLC. Power dissipation has become a primary concern in large-scale integration (LSI) design [1]. Over the years, LSI designers have been tirelessly developing hardware and software techniques for effectively reducing functional power [2]. Functional constraints are often exploited at various levels to remove wasteful operations so that functional power is reduced. For example, a circuit designed for cell phone applications contains many functional blocks that do not need to be activated simultaneously, e.g., a block for audio and a block for phone calls. Dynamically disabling unnecessary circuit blocks significantly reduces functional power.

DOI： 10.1201/9781315215709

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85054660389&origin=inward

ATPG Enhancement Technology 査読有り国際誌

N.A. Zakaria, M.Z Khalid, X. Wen

IEEE Workshop on RTL and High Level Testing Paper IV.5.S 2013年11月

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り国際誌

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE Asian Test Symposium 19 - 24 2013年11月

Search Space Reduction for Low-Power Test Generation 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE Asian Test Symposium 171 - 176 2013年11月

Test Pattern Modification for Average IR-drop Reduction 査読有り国際誌

J. Li, W-S. Ding, H-Y. Hsieh, X. Wen

IEEE International Test Conference Poster 2013年09月

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing 査読有り国際誌

K. Miyase, R. Sakai, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

IEICE Transaction on Information and Systems E96-D ( 9 ) 2003 - 2011 2013年09月

SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop Paper 4.4 2013年07月

Controllability Analysis of Local Switching Activity for Layout Design 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

Workshop on Design and Test Methodologies for Emerging Technologies Paper 2 2013年05月

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE Design & Test of Computers 30 ( 4 ) 60 - 70 2013年04月

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression 査読有り国際誌

K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, L.-T. Wang

26th International Conference on VLSI Design 279 - 284 2013年01月

Fault Detection with Optimum March Test Algorithm 査読有り国際誌

N. Zakaria, W. Hassan, I. Halin, R. Sidek, X. Wen

Journal of Theoretical and Applied Information Technology 47 ( 1 ) 18 - 27 2013年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a research work aimed to detect previously-undetected faults, either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both in March Algorithm such as MATS++(6N), March C-(10N), March SR(14N), and March CL(12N). The main focus of this research is to improve fault coverage on Single Cell Faults as well as Static Double Cell Faults detection, using specified test algorithm. Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds) and Deceptive Read Destructive Faults (CFdrds) are types of faults mainly used in this research. The experiment result published in [1] shows BIST (Built-In-Self-Test) implementation with the new algorithm. It provides the same test length but with bigger area overhead, we therefore proposed a new 14N March Test Algorithm with fault coverage of more than 95% using solid 0s and 1s Data Background (DB). This paper reveals the design methodology to generate DB covers all memories function by applying non-transition data, transition data, and single read and double read data. The automation hardware was designed to give the flexibility to the user to generate other new March Algorithm prior to the selected algorithm and analyzed the performance in terms of fault detection and power consumption. © 2005 - 2013 JATIT & LLS. All rights reserved.

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84872392175&origin=inward

Estimation of the Amount of Don't-Care Bits in Test Vectors 査読有り国際誌

K. Miyase, S. Kajihara, X. Wen

IEEE Workshop on RTL and High Level Testing 2012年11月

A Transition Isolation Scan Cell Design for Low Shift and Capture Power 査読有り国際誌

Y.-T. Lin, J.-L Huang, X. Wen

IEEE Asian Test Symposium 107 - 112 2012年11月

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論文 - 温　暁青