研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 261 - 280 件目／全件表示 >>

Is Test Power Reduction Through X-Filling Good Enough? 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Test Conference 805 - 805 Poster 2010年11月

On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test 査読有り国際誌

S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, X. Wen

10th International Symposium on Communications and Information Technologies 723 - 726 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Tokyo 2010年10月26日 - 2010年10月29日

This paper proposes a test compaction method for full scan circuits based on multiple capture clock cycles. The multiple cycle test applies more than one capture clock signals for a circuit after scan shift operation, while the capture clock cycle of the conventional scan test is one. Because every captured value at scan flip-flops is used for fault detection, the opportunity of fault detection for each fault increases. As a result, the number of test vectors would be decreased compared with the single cycle mode. Such a test compaction method would be useful in field test that requires less test data so as to store them on-chip. Experimental results show that the proposed method is effective for test compaction. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665084

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=78651251137&origin=inward

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains 査読有り国際誌

S. Wu,L.-T. Wang,L. Yu,H. Furukawa,X. Wen,W.-B. Jone,N. A. Touba,F. Zhao,J. Liu,H.-J. Chao,F. Li,Z. Jiang

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 358 - 366 2010年10月

Case Studies on Transition Fault Test Generation for At-Speed Scan Testing 査読有り国際誌

N. A. Zakariz, E. V. Bautista, S. M. Jusoh, W. F. Lee, X. Wen

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 180 - 188 2010年10月

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes 査読有り国際誌

F. Wu,L. Dilillo,A. Bosio,P. Girard,S. Pravossoudovitch,A. Virazel,M. Tehranipoor,X. Wen,N. Ahmed

ASP Journal of Lower Power Electronics 6 ( 2 ) 359 - 374 2010年08月

On Delay Test Quality for Test Cubes 査読有り国際誌

S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen

IPSJ Transactions on System LSI Design Methodology 3 283 - 291 2010年08月

A Study of Capture-Safe Test Generation Flow for At-Speed Testing 査読有り国際誌

K. Miyase, X. Wen, S. Kajihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja

IEICE Transactions on Information and Systems E93-A ( 7 ) 1309 - 1318 2010年07月

On Estimation of NBTI-Induced Delay Degradation 査読有り国際誌

M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura

IEEE European Test Symposium 107 - 111 2010年05月

Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, X. Wen

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 376 - 381 2010年04月

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme 査読有り国際誌

K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L. Wang, M. Tehranipoor

IEICE Transactions on Information and Systems E93-D ( 1 ) 2 - 9 2010年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock- Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design. Copyright © 2010 The Institute of Electronics.

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=77950234242&origin=inward

CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing 招待有り査読有り国際誌

X. Wen, K. Enokimoto, K. Miyase, S. Kajihara, M. Aso, H. Furukawa

Symposium II (International Semiconductor Technology Conference & China Semiconductor Technology International Conference) 197 - 202 2010年03月

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

L.-T. Wang,X. Wen,S. Wu,H. Furukawa,H.-J. Chao,B. Sheu,J. Guo,and W.-B. Jone

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29 ( 2 ) 299 - 312 2010年02月

A Path Selection Method for Delay Test Targeting Transistor Aging 査読有り国際誌

M. Noda,S. Kajihara,Y. Sato,K. Miyase,X. Wen,and Y. Miura

IEEE International Workshop on Reliability Aware System Design and Test 57 - 61 2010年01月

X-Identification According to Required Distribution for Industrial Circuits 査読有り国際誌

I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

IEEE Workshop on RTL and High Level Testing 76 - 81 2009年11月

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing 査読有り国際誌

K. Enokimoto,X. Wen,Y. Yamato,K. Miyase,H. Sone,S. Kajihara,M. Aso,and H. Furukawa

IEEE Asian Test Symposium 99 - 104 2009年11月

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing 査読有り国際誌

Y. Yamato,X. Wen,K. Miyase,H. Furukawa,and S. Kajihara

IEEE 15th Pacific Rim International Symposium on Dependable Computing 81 - 86 2009年11月

Optimizing the Percentage of X-Bits to Reduce Switching Activity 査読有り国際誌

I. Beppu,K. Miyase,Y. Yamato,X. Wen,and S. Kajihara

IEEE Workshop on Defect and Date Driven Testing 4 Pages 2009年11月

A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment 査読有り国際誌

K. Miyase,K. Noda,H. Ito,K. Hatayama,T. Aikyo,Y. Yamato,X. Wen,and S. Kajihara

IEEE/ACM International Conference on Computer Aided Design 97 - 104 2009年11月

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment 査読有り国際誌

M.-F. Wu,J.-L. Huang,X. Wen,K. Miyase

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28 ( 11 ) 1767 - 1776 2009年11月

シグナルインテグリティ考慮型LSIテストを目指して招待有り査読有り

温　暁青

信頼性学会誌 31 ( 7 ) 498 - 505 2009年10月

　前のページ - 次のページ　

<温 暁青>

論文 - 温 暁青

<温　暁青>

論文 - 温　暁青