研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 21 - 40 件目／全件表示 >>

Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications 査読有り国際誌

Yan A., He Y., Huang Z., Yan W., Cui J., Wang X., Ni T., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents radiation-hardened flip-flop (FF) designs capable of tolerating soft errors, e.g., single-node upsets (SNUs), double-node upsets (DNUs) and multiple-node upsets (MNUs). First, a 2-input FF and a 3-input FF are proposed as the baseline FFs that not only respectively tolerate SNUs and DNUs but also exhibit cost efficiency in terms of delay, power, and area. Through adding two stages of C-elements, a 4-input FF and a 5-input FF are proposed as the baseline FFs as well. Utilizing the structural characteristics of these FFs, an N-1 input FF and an N input FF are proposed as the extended FFs capable of tolerating more node upsets. Moreover, a highly efficient algorithm for verifying MNU-tolerance of these FFs is proposed. Algorithm and HSPICE-tool-based verification results both demonstrate the MNU-tolerance for the proposed FFs with more inputs.

DOI： 10.1109/TCAD.2024.3426271

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Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices 査読有り国際誌

Yan A., Lin Z., Liu G., Zhang Q., Huang Z., Cui J., Wen X., Girard P.

Proceedings - IEEE International Symposium on Circuits and Systems 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Nonvolatile memories are widely used in emerging energy-harvesting Internet-of-Things (IoT) applications, and nonvolatile memories constructed from FeFET devices hold great promise. This paper presents a nonvolatile and single-event-upset (SEU)-recoverable latch based on FeFET and CMOS for energyharvesting devices. The latch uses n-type FeFET devices to provide nonvolatility without any additional control signals. Moreover, since the soft error problem has become increasingly severe, radiation hardening by design gains a great attention as a promising approach to mitigate the reliability issue. The latch uses feedback interlocked loops with n-type FeFETs and C-elements, enabling it to provide nonvolatility and SEU-recovery simultaneously. Simulation results with Candence Virtuoso verifies that the proposed latch design has correct functioning with excellent performance compared to the state-of-the-art designs.

DOI： 10.1109/ISCAS58744.2024.10558033

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Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware 査読有り国際誌

Ni T., Wen X., Amrouch H., Zhuo C., Song P.

ACM Transactions on Design Automation of Electronic Systems 29 ( 1 ) 2023年12月

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness 査読有り国際誌

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wang S., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 70 ( 12 ) 5074 - 5085 2023年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the input changes too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses. We study the output of the XOR gate when facing different inputs. By modeling the time of a fibonacci ring oscillator (FIRO) as an example, we find that the loss of short pulses in an inverter chain is the reason for making the FIRO enter into periodic oscillation. This phenomenon suppresses the accumulation of jitter and occurs periodically in existing structures. Our proposed structure uses independent sub-rings to accumulate jitter, allowing the main-ring to quickly generate short pulses to provide analog randomness. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA. The experimental results show that it has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.

DOI： 10.1109/TCSI.2023.3287162

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RMC-NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel 査読有り国際誌

Xu D., Ouyang Y., Zhou W., Huang Z., Liang H., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 ( 12 ) 2061 - 2074 2023年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

As chip fabrication has advanced to the nano level, the increased link density has heightened the risk of failures. The potential performance drawbacks resulting from these link failures have become a critical challenge in the design of reliable network-on-chip (NoC) systems. Fault-tolerant routing algorithms have proven to be effective strategies for handling this issue by diverting packets away from failed links to prevent congestion. However, these algorithms often result in excessive packet diversion, especially in the presence of a higher failure rate, which can significantly constrain the network's behavior. This article introduces a novel NoC design with reconfigurable multifunctional channels (RMC-NoC). This design dynamically adapts the channel functions in response to network conditions to ensure that packets from failed links follow their original paths. In addition, it presents a channel buffer bubble flow control mechanism that can resolve congestion by redistributing congested traffic within the channel buffer. The evaluation results demonstrate that our approach ensures superior network communication even in the presence of permanent link failures, with minimal area overhead and power consumption. Moreover, our system exhibits lower latency and higher throughput compared to state-of-the-art fault-tolerant methods across various link failure rates. Notably, even at a severe failure rate of 30%, RMC-NoC exhibits only a 16.3% increase in latency compared to an ideal failure-free environment (Baseline) while still maintaining system communication capabilities to a considerable extent.

DOI： 10.1109/TVLSI.2023.3321598

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An AI-Driven VM Threat Prediction Model for Multi-Risks Analysis-Based Cloud Cybersecurity 査読有り国際誌

Saxena D., Gupta I., Gupta R., Singh A.K., Wen X.

IEEE Transactions on Systems, Man, and Cybernetics: Systems 53 ( 11 ) 6815 - 6827 2023年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Cloud virtualization technology, ingrained with physical resource sharing, prompts cybersecurity threats on users' virtual machines (VMs) due to the presence of inevitable vulnerabilities on the offsite servers. Contrary to the existing works which concentrated on reducing resource sharing and encryption/decryption of data before transfer for improving cybersecurity which raises computational cost overhead, the proposed model operates diversely for efficiently serving the same purpose. This article proposes a novel multiple risks analysis-based VM threat prediction model (MR-TPM) to secure computational data and minimize adversary breaches by proactively estimating the VMs threats. It considers multiple cybersecurity risk factors associated with the configuration and management of VMs, along with analysis of users' behavior. All these threat factors are quantified for the generation of respective risk score values and fed as input into a machine learning-based classifier to estimate the probability of threat for each VM. The performance of MR-TPM is evaluated using benchmark Google Cluster and OpenNebula VM threat traces. The experimental results demonstrate that the proposed model efficiently computes the cybersecurity risks and learns the VM threat patterns from historical and live data samples. The deployment of MR-TPM with existing VM allocation policies reduces cybersecurity threats up to 88.9%.

DOI： 10.1109/TSMC.2023.3288081

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Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications 査読有り国際誌

Yan A., Cao A., Huang Z., Cui J., Ni T., Girard P., Wen X., Zhang J.

IEEE Transactions on Emerging Topics in Computing 11 ( 4 ) 1070 - 1081 2023年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

The continuous advancement of complementary metal-oxide-semiconductor technologies makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as double-node upsets (DNUs), are typical soft errors. This article proposes two radiation-hardened FF designs, namely DNU-tolerant FF (DUT-FF) and DNU-recoverable FF (DUR-FF). First, the DUT-FF which mainly consists of four dual-interlocked-storage-cells (DICEs) and three 2-input C-elements, is proposed. Then, to provide complete self-recovery from DNUs, the DUR-FF which mainly uses six interlocked DICEs is proposed. They have the following advantages: 1) They can completely protect against SNUs as well as DNUs; 2) the DUT-FF is cost-effective but the DUR-FF can provide complete self-recovery from any DNU. Simulations show the complete SNU/DNU tolerance of DUT-FF and the complete SNU/DNU self-recovery of DUR-FF but at the cost of indispensable area overhead when compared to the SNU hardened FFs. Besides, compared to the FFs of the same-type, the proposed FFs achieve a low delay making them suitable for high-performance applications.

DOI： 10.1109/TETC.2023.3317070

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GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting<sup>∗</sup> 査読有り国際誌

Shi S., Holst S., Wen X.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E106.D ( 10 ) 1694 - 1704 2023年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC’99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

DOI： 10.1587/transinf.2023EDP7011

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An equivalent processing method for integrated circuit electrical parameter data using BP neural networks 査読有り国際誌

Zhan W., Zhang L., Feng X., Pan P., Cai X., Wen X.

Microelectronics Journal 139 2023年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

In response to the current problem of significant differences between old and new equipment in testing electrical parameter data, as well as the lack of a unified parameter measurement standard in the IC testing industry, we propose an equivalent processing method for electrical parameter data using BP neural networks. Firstly, the method involves mapping the electrical parameter data measured by both the old and new equipment and subsequently trimming the test data. Then, the BP neural network is applied to the equivalent processing of the dataset, aiming to unify the test limits and electrical parameter data. This approach facilitates the extrapolation of new data from old equipment data, enabling a seamless data transfer and the harmonization of industry standards. This method effectively reduces the testing difficulty and misjudgment rate, thereby improving the testing efficiency for semiconductor manufacturers. The experimental results demonstrate that the proposed algorithm can accurately infer the new equipment's test data from the old equipment's data, ensuring data smooth transition. Furthermore, the modification of electrical parameter data does not affect the yield.

DOI： 10.1016/j.mejo.2023.105912

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Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications 査読有り国際誌

Yan A., Xiang J., Chang Y., Huang Z., Cui J., Girard P., Wen X.

Microelectronics Journal 139 2023年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper first presents a double-node upset (DNU) protected and sextuple cross-coupled static-random-access memory (SRAM) cell, i.e., SCCS-18T, for aerospace applications. The cell can recover from each possible single-node upsets (SNUs) as well as partial DNUs due to its formed large feedback loop that can retain values and intercept errors. To improve DNU self-recoverability, an enhanced version of the SCCS-18T cell, namely SCCS-18T-EV, is proposed. Due to the new formed structure, the SCCS-18T-EV can recover from more DNUs. Since parallel access transistors are used, the proposed cells have optimized read/write performance. Simulation results demonstrate the node-upset tolerance as well as the optimized operation performance of the proposed SCCS-18T and SCCS-18T-EV cells compared to existing SRAM cells.

DOI： 10.1016/j.mejo.2023.105908

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Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata 査読有り国際誌

Yan A., Li X., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland) 12 ( 14 ) 2023年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

DOI： 10.3390/electronics12143189

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A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications 査読有り国際誌

Yan A., Wei S., Zhang J., Cui J., Song J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 167 - 171 2023年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose a double-node-upset recoverable latch that can completely recover from all possible double-node-upsets (DNUs) with low area and low delay. The latch consists of seven 2-input C-elements (CEs) implemented in 22nm complementary metal oxide semiconductor (CMOS) technology, making it area-efficient. The proposed latch employs the clock gating methodology and a high-speed transmission path, enabling it to perform with lower overhead in terms of transmission delay and power dissipation. Simulation results demonstrate that the proposed latch can provide complete DNU recovery. Compared with typical double-node-upset-recoverable latches, the proposed latch can save 89.74% of Area-Delay-Power Product (ADPP) on average.

DOI： 10.1145/3583781.3590281

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Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications 査読有り国際誌

Yan A., Chang Y., Xiang J., Luo H., Cui J., Huang Z., Ni T., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 293 - 298 2023年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose two Highly Reliable and High-Speed SRAM cells, namely HRHS18T and HRHS18T_EV. The proposed cells can be applied to safety-critical applications due to their excellent self-recoverability from node-upsets. Meanwhile, the proposed cells have smaller read/write delay than other state-of-the-art hardened SRAMs. Simulation and quantitative calculation results show that, the proposed HRHS18T cell can save 65.05% read time and 38.12% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs. The results also show that the HRHS18T_EV cell can save 65.05% read time and 73.28% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs.

DOI： 10.1145/3583781.3590261

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Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array 査読有り国際誌

Chen N., Cheng F., Han C., Jiang J., Wen X.

Tsinghua Science and Technology 28 ( 2 ) 330 - 343 2023年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

To solve the problem of grid coarse-grained reconfigurable array task mapping under multiple constraints, we propose a Loop Subgraph-Level Greedy Mapping (LSLGM) algorithm using parallelism and processing element fragmentation. Under the constraint of a reconfigurable array, the LSLGM algorithm schedules node from a ready queue to the current reconfigurable cell array block. After mapping a node, its successor's indegree value will be dynamically updated. If its successor's indegree is zero, it will be directly scheduled to the ready queue; otherwise, the predecessor must be dynamically checked. If the predecessor cannot be mapped, it will be scheduled to a blocking queue. To dynamically adjust the ready node scheduling order, the scheduling function is constructed by exploiting factors, such as node number, node level, and node dependency. Compared with the loop subgraph-level mapping algorithm, experimental results show that the total cycles of the LSLGM algorithm decreases by an average of 33.0% (PEA4×4) and 33.9% (PEA7×7). Compared with the epimorphism map algorithm, the total cycles of the LSLGM algorithm decrease by an average of 38.1% (PEA4×4) and 39.0% (PEA7×7). The feasibility of LSLGM is verified.

DOI： 10.26599/TST.2022.9010001

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A High-Performance and P-Type FeFET-Based Non-Volatile Latch 査読有り国際誌

Yan A., Chen Y., Huang Z., Cui J., Wen X.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Non-volatile memory has a significant future in the Internet of Things and computation-in-memory applications. Among them, non-volatile memories using emerging FeFET devices have garnered significant attention. This paper proposes a novel P-type FeFET -based non-volatile latch. This design takes advantage of the unique characteristics of a P-type FeFET device to achieve non-volatility with no additional control signals. The Cadence simulation tool Virtuoso verifies that our proposed design has correct functioning with excellent power, area, and delay performance compared to state-of-the-art designs.

DOI： 10.1109/ATS59501.2023.10318017

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SASL-JTAG: A Light-Weight Dependable JTAG 査読有り国際誌

Wang S., Wei S., Ma J., Kai H., Higami Y., Takahashi H., Shimizu A., Wen X., Ni T.

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper addresses the performance imbalance issue of IoT systems and proposes a lightweight JTAG authentication scheme for enhancing the dependability of IoT devices. We propose a one-time authentication protocol, called SAS-L(Simple And Secure Light authentication), to improve the dependability of the JTAG, referred to as SASL-JTAG. The architecture of the SASLJTAG authentication is designed and implemented on an FPGA to verify its functionality and evaluate hardware overhead. SASL-JTAG offers a cost-effective and scalable solution for securing JTAG systems in IoT devices while ensuring high reliability.

DOI： 10.1109/DFT59622.2023.10313532

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Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling 査読有り国際誌

Shi S., Holst S., Wen X.

Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 501 - 507 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scan shift causes a lot of switching activity in the combinational logic that in turn can lead to high IR-drop. Excessive IR-drop may corrupt test vectors or responses during shifting, leading to test-induced yield-loss. Power-aware X-filling is a widely used method to reduce the overall switching activity during shifting without modifying the scan infrastructure. While such untargeted approaches help reduce the average IR-drop during shifting, some hot-spots of worst-case IR-drop still remain. Through an innovative in-depth IR-drop analysis of high-risk shift cycles, we discovered that these hot-spots are caused by a few High-Impact scan-cell Transitions (HITs). In this paper, we propose to reduce the peak IR-drop during scan shift by using a novel X-filling strategy that (1) identifies HITs through GPU-accelerated IR-drop estimation, and (2) adjusts the X-filling of test vectors to mitigate the remaining worst-case IR-drop hotspots. The results on ITC'99 benchmark circuits demonstrate a 26% peak IR-drop reduction on average without impact on fault coverage or test vector count.

DOI： 10.1109/MCSoC60832.2023.00080

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Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning 査読有り国際誌

Nie M., Jiang W., Yang W., Wang S., Wen X., Ni T.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Defect diagnosis and localization in wafer maps are crucial tasks in semiconductor manufacturing. Existing deep learning methods often require pixel-level annotations, making them impractical for large-scale deployment. In this paper, we propose a novel weakly supervised learning approach to achieving high-precision defect identification and effective localization with only image-level labels. By leveraging the information of defect types and locations, we introduce a weighted fusion of activation maps, called Class Activation Map (CAM), to highlight classspecific regions. We further enhance defect localization accuracy and completeness by employing optimized region growing operations to eliminate noise in defect regions. Moreover, we present an optimized inference method that provides meaningful visual explanations for defect recognition. Experimental results on real-world wafer map images demonstrate the effectiveness of our approach in accurately segmenting defect patterns with no pixel-level annotations. By training the model solely on wafer map image classification labels, our proposed model significantly improves defect recognition, facilitating efficient defect analysis in semiconductor manufacturing. The proposed weakly supervised learning approach offers a practical solution for defect diagnosis and localization, with the potential of widespread adoption in the semiconductor industry.

DOI： 10.1109/ATS59501.2023.10317989

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Design of Low-Cost Approximate CMOS Full Adders 査読有り国際誌

Yan A., Wei S., Li Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2023-May 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Many applications have an inherent tolerance for insignificant inaccuracies. Full adders are key arithmetic functions for many error-tolerant applications. Approximate full adders are considered an efficient technique to trade off energy relative to performance and accuracy. In this paper, we propose four approximate full adders with low overhead. The proposed and the existing approximate full adders are classified into two groups according to their error distances. Simulation results show that, compared with the existing approximate full adders, in the first group, the proposed ones can reduce power-area-delay product (PADP) by 61.83%, power by 54.15%, area by 44.67%, and delay by 22.78% on average; in the second group, the proposed ones can reduce PADP by 97.01%, power by 93.43%, area by 24.98%, and delay by 36.14% on average.

DOI： 10.1109/ISCAS46773.2023.10181531

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85167718965&origin=inward

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness 査読有り国際誌

Yan A., Zhou C., Wei S., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As CMOS processes continue to shrink, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiation. To tolerate MNU, a novel quadruple-node-upset (QNU) self-recoverable latch is proposed in this paper. The proposed latch is mainly constructed from six blocks of three-level C-elements (TLCEs) and six inverters. With the mutual feedback of the various TLCEs, the proposed latch can recover from any QNU. Furthermore, due to the clock gating methodology and a high-speed transmission path, the proposed latch has lower overhead in terms of power dissipation and transmission delay. Simulation results show that the proposed latch achieves high reliability with moderate overhead compared to typical existing latches.

DOI： 10.1109/ITC-Asia58802.2023.10301187

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