研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 21 - 40 件目／全件表示 >>

Incremental learning strategies for improved detection of unknown defects in wafer maps with limited samples 査読有り国際誌

Ni T., Jiang W., Liang H., Wen X., Nie M.

Computers in Industry 175 2026年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

Accurate detection of a wide range of defect patterns on wafers is crucial for enhancing chip yield and ensuring the reliability of semiconductor manufacturing systems. As this process becomes increasingly complex, new types of defects — referred to as unknown defects — emerge on wafers. Traditional pattern recognition methods struggle in this setting because limited samples are insufficient to effectively train deep learning models. Moreover, these models are prone to catastrophic forgetting when incrementally trained on new defect classes. To address these challenges, this paper proposes a method termed Few-Shot Class Contrastive Incremental Learning (FCCIL) for unknown wafer map defect detection. FCCIL integrates a contrastive learning network for distinguishing novel defect types and an incremental learning model for dynamic knowledge updating—both designed to mitigate catastrophic forgetting, thereby enabling the detection of unknown defects in wafer maps with limited data. Experimental results demonstrate a 4% improvement in forgetting resistance over state-of-the-art approaches, confirming the effectiveness of FCCIL in real-world semiconductor manufacturing scenarios.

DOI： 10.1016/j.compind.2025.104432

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Design and verification of a robust near-memory computing architecture for image fusion tasks 査読有り国際誌

Yan A. (Heifei University of Technology), Bao H. (Heifei University of Technology), Cui J. (Heifei University of Technology), Waris H., Li J. (Heifei University of Technology), Wen X.

Microelectronics Journal 168 2026年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the development of data-intensive applications, traditional von-Neumann architectures face the “storage wall” bottleneck, limiting the performance and energy efficiency of computing systems. Near-memory computing (NMC) mitigates this problem by integrating compute units near memory, enabling data to be processed in-situ. In this study, a novel near-memory computing architecture is designed and applied to the image fusion tasks with an approximate full adder. By integrating basic compute units near the storage module, local data-weighted processing reduces the performance-aware overhead of data migration. Experimental results show that, the designed approximate full adder reduces power consumption, delay and power-area-delay product (PADP) by an average of 4.3 %, 95.29 % and 94.49 %, respectively. Compared with the traditional von-Neumann architecture, the performance of the designed near-memory computing architecture is improved by 40 %. This solution realizes the energy efficiency optimization while maintaining the integrity of image fusion functionality, validating the feasibility of near-memory computing in lightweight image processing tasks.

DOI： 10.1016/j.mejo.2025.107006

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A Highly Robust and Low-Cost Multiple Node Upset Resilient Fast Latch for Radiation Applications 査読有り国際誌

Bai N., Wang F., Xu Y., Wang S., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 62 4411 - 4421 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the size of semiconductor processes continues to shrink and deep space exploration continues to advance, the design of multiple-node-upset (MNU)-resilient latches has become indispensable for radiation hardening by design (RHBD). The C-element (CE) and the clock-gated C-element (CG-CE) are the basic elements for most conventional MNU-resilient latches. However, most MNU-resilient latches improve the antiradiation ability with the redundant nodes or redundant CE and CG-CE, causing a large area overhead. Some other MNU-resilient latches have less area overhead but have less antiradiation ability. To overcome this problem, this article proposes a corresponding MNU resilient latch design named HLDRF. The proposed design consists of a generation module and a feedback module. The generation module transfers the generation nodes’ voltage to the feedback module, whereas the feedback module feeds the feedback nodes’ voltage back to the generation nodes through the pull-up/pull-down paths of the CE. This bidirectional interaction forms a closed-loop feedback circuit, ensuring a strong antiradiation ability. The proposed latch can fix errors quickly through feedback loops and without causing the propagation of faulty logic. The proposed latch achieves an optimal balance between area overhead and radiation hardness, offering superior comprehensive performance for deep space exploration. Furthermore, the proposed latch exhibits a lower sensitivity to process, supply voltage, and temperature variations compared to similar latches.

DOI： 10.1109/TAES.2026.3651658

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ACDRL: Aging-Mitigated C-Elements Based Double-Node-Upset-Recoverable Latch for Long-Term Reliability Enhancement 査読有り国際誌

Dong C. (Heifei University of Technology), Yan A. (Heifei University of Technology), Guo X. (Heifei University of Technology), Pei Z. (Heifei University of Technology), Wang Q. (Heifei University of Technology), Huang Z. (Heifei University of Technology), Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 62 6645 - 6652 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Soft errors and aging are two major factors impacting the long-term reliability of integrated circuits, especially for aerospace applications. Double-node upset (DNU) and bias-temperature instability (BTI) are typical soft errors and aging, respectively. First, this article presents a C-elements (CEs) based DNU-recoverable latch, namely the basic latch, without aging mitigation to ensure low overhead. Second, in order to alleviate BTI-induced aging, the BTI-mitigated CEs are proposed so as to construct the aging-mitigated CEs based DNU-recoverable latch, namely ACDRL, for long-term reliability enhancement. By optimizing the key CEs internal structure, the stress time of transistors in feedback loops can be effectively reduced to mitigate the impact of BTI on the latch. Pertinent simulation results demonstrate that the proposed latches have DNU recoverability; the soft error rate increase due to BTI is reduced by roughly 35% for ACDRL compared with the basic latch; the delay of ACDRL is almost not affected, and the area and power increase of ACDRL are limited compared with the BTI-unmitigated latches.

DOI： 10.1109/TAES.2026.3665491

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Algorithm-Aided Design and Verification for Multiple-Node-Upset-Recovery Latches 査読有り国際誌

Pei Z., Li J., Waris H., Younis M.S., Yan A., Deng J., Gui Y., Wen X.

Proceedings IEEE International Symposium on Circuits and Systems 4063 - 4067 2026年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In advanced CMOS technologies, integrated circuits are becoming increasingly sensitive to soft errors in radiation environments. The design process of existing latches heavily relies on electronic design automation (EDA) tools with comprehensive error-injection-based robustness verification. In this paper, algorithm-aided design and verification for robust latches are proposed and then, three algorithm-aided latches (i.e., SURLAD, DURLAD, and TURLAD) respectively providing SNU-, DNU-, and TNU-recovery are proposed. These latches are recoverable from single-node-upsets (SNUs) and multiple-node upsets (MNUs), respectively. Verification results demonstrate the robustness and advantages in terms of delay and power overhead of the proposed latches compared with state-of-the-art latches.

DOI： 10.1109/ISCAS66217.2026.11562619

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Automated Co-Optimization Framework of Feature Selection and Ensemble Learning for Wafer Yield Prediction 査読有り国際誌

Ni T., Wu H., Cheng M., Bian J., Wang S., Wen X., Nie M.

IEEE Transactions on Automation Science and Engineering 23 11245 - 11257 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Efficient and automated wafer yield prediction is central to cost control and process optimization in intelligent semiconductor manufacturing. As the initial testing stage in wafer inspection, Wafer Acceptance Testing (WAT) data contain critical process-related information. However, its high dimensionality, redundancy, and nonlinear inter-dependencies pose significant challenges to conventional yield prediction models, such as high computational overhead and limited generalization capability. Moreover, existing approaches often lack an automated framework capable of jointly addressing feature redundancy and model complexity. This paper proposes a collaborative and automated prediction framework that integrates feature selection and machine learning. First, an enhanced Binary Zebra Population Optimization Algorithm (BZPOA) is introduced, which incorporates redesigned exploration and development mechanisms to automatically identify key feature subsets from high-dimensional parameters, substantially reducing data redundancy and computational dimensionality. Second, a Bayesian hyperparameter-optimized XGBoost model is constructed, utilizing the Tree-structured Parzen Estimator (TPE) to achieve deep co-optimization of model parameters and feature space, thereby overcoming the inefficiency and overfitting issues commonly associated with manual parameter tuning. Experiments on a real-world dataset demonstrate that the proposed framework achieves average Recall, Precision, and F1-scores of 0.872, 0.917, and 0.902, respectively. Compared with the full-feature baseline, the BZPOA-selected feature subset improves predictive performance by 5%-10%, attains an AUC of 0.904, and significantly reduces per-wafer prediction time. Cross-factory transfer experiments further confirm the robustness of the proposed system. Note to Practitioners - In semiconductor manufacturing, wafer yield prediction is a critical link for ensuring production capacity and reducing costs. Traditional methods face challenges such as high-dimensional test data redundancy and complex model tuning, resulting in low prediction efficiency and weak generalization ability. This paper proposes a collaborative automation framework that achieves end-to-end optimization from raw data to yield prediction by integrating feature selection and machine learning. This method is applicable to early yield monitoring during the wafer testing stage and can be integrated into existing automated testing systems, facilitating real-time quality feedback and process adjustments.

DOI： 10.1109/TASE.2026.3700731

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FN2LD: FeFET-based nonvolatile and node-upset-recovery latch designs with cost optimization 査読有り国際誌

Yan A. (Heifei University of Technology), Jiang W. (Heifei University of Technology), Wang H. (Heifei University of Technology), Kang B. (Heifei University of Technology), Huang Z. (Heifei University of Technology), Ni T., Wen X., Girard P.

Microelectronics Journal 167 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Nonvolatile memory based on FeFETs demonstrates outstanding energy management capabilities, making it highly promising for energy-harvesting and battery-powered Internet of Things applications. Concurrently, the reduction in transistor dimensions and the increased integration of semiconductor circuits are intensifying the requirements for circuit robustness with protection against soft errors. In this paper, an innovative nonvolatile and single-node-upset-recovery latch, namely FN<sup>2</sup>LD-1, which does not require any additional control signals, is proposed. In addition, to further address the double-node-upset (DNU) threat in radiative environments, this paper also presents for the first time a FeFET-based nonvolatile and DNU-tolerant latch, namely FN<sup>2</sup>LD-2. Simulation results based on Cadence Virtuoso validate that the proposed latches provide nonvolatility and node-upset-recovery with low overhead. Compared with alternative nonvolatile latches, FN<sup>2</sup>LD-1 reduces delay by 67.54 % and delay-power-area product by 25.47 % on average, and FN<sup>2</sup>LD-2 reduces delay by 82.87 % and delay-power-area by 9.88 % on average, respectively.

DOI： 10.1016/j.mejo.2025.106975

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Locating Hotspots based on Switching Probability Calculation and Functional Analysis with Partial Truth Table 査読有り国際誌

OGATA Yuusei, YAMASHITA Tomoya, MIYASE Kohei, LU Shyue-Kung, WEN Xiaoqing

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人電子情報通信学会 ) advpub ( 0 ) 1638 - 1648 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

<p>When IR-drop in LSI testing becomes excessive in a certain area of LSI, it causes excessive delay, resulting in test malfunction (over-testing). This is because power consumption in the test mode is generally much higher than in the normal mode. Excessive IR-drop does not occur in the entire area of a circuit, but in certain areas where a large number of switching activities occur (such areas are called hotspots in this work). In order to avoid test malfunction, it is important to develop a method to reduce or control IR-drop in the hotspots. Locating hotspots is a necessary technique to reduce or control IR-drop effectively and efficiently. In this work, we propose a method to locate hotspots caused in the test mode by switching probability calculation and functional analysis with partial truth table. Experimental results for IWLS2005 OpenCores circuits demonstrate the proposed method can support to locate hotspots.</p>

DOI： 10.1587/transfun.2025eap1221

その他リンク： https://www.jstage.jst.go.jp/article/transfun/advpub/0/advpub_2025EAP1221/_pdf

Low-Delay, High-Robustness DNU Self-Healing Latch Based on the C-Element Feedback Loop 査読有り国際誌

Bai N., Xu P., Xu Y., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 62 5974 - 5985 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the impact of various radiations in the space environment on the reliability of latch circuits increases, this article proposes a low-delay double node upset (DNU) self-healing latch (LDDSL). The LDDSL latch is implemented based on a C-element feedback loop, enabling all internal node pairs to undergo DNU self-healing. The incorporation of high-speed channels between inputs and outputs significantly reduces delay time. The LDDSL latch achieves the lowest delay compared to existing latches with DNU-hardening, in terms of 15.59% less power consumption, a reduced 42.61% delay, and a remarkable 38.11% reduction in PDAP. Furthermore, the LDDSL latch demonstrates lower or comparable sensitivity to process, voltage, and temperature variations when compared to the reference latch designs.

DOI： 10.1109/TAES.2026.3660817

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105029957023&origin=inward

RMC PUF: A Highly Reliable PUF Architecture Based on Recursive Markov Chain Obfuscation 査読有り国際誌

Huang Z., Yang Z., Sun X., Lu Y., Bian J., Ouyang Y., Ni T., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 34 ( 8 ) 2558 - 2570 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Physical unclonable functions (PUFs) are critical hardware security primitives that extract entropy from intrinsic manufacturing process variations (MPVs) to generate unique cryptographic responses. They have demonstrated extensive application prospects in lightweight encryption and authentication for Internet of Things (IoT) devices. However, the classic arbiter PUF (APUF) is inherently vulnerable to machine learning (ML) modeling attacks due to the linear mathematical model of its delay circuits. To address this challenge, this article proposes a novel postprocessing obfuscation architecture named recursive Markov chain PUF (RMC PUF). The proposed architecture couples an APUF core with Markov obfuscation modules. By exploiting the intermediate stage responses of the APUF as an entropy source, the system constructs a 1-D recursive stochastic state transition mechanism. This approach recursively transforms and obfuscates the raw entropy based on Markov Chain theory, achieving a PUF system with stability and robust resistance against ML attacks. Through this efficient recursive obfuscation strategy, the design achieves precise utilization of the APUF’s intrinsic entropy. The work is validated through both numerical simulation and FPGA prototyping. Experimental results show that the prototype maintains a high reliability of 98.9%–99.9% within a voltage range of 0.8–1.2 V, and a reliability of 96.1%–99.7% within a temperature range from −10 <sup>◦</sup>C to 80 <sup>◦</sup>C. Comparative analysis indicates that the proposed RMC PUF significantly outperforms existing structures in security, limiting the prediction accuracy of four ML attack models [logistic regression (LR), artificial neural networks (ANNs), deep neural networks (DNNs), and covariance matrix adaptive evolutionary strategy (CMA-ES)] to no more than 54.72%.

DOI： 10.1109/TVLSI.2026.3693479

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A Challenge-Response Remapping Reliability Enhancement Method for APUF Based on Adjacent Challenge-Bit Flipping 査読有り国際誌

Lin Y., Gao B., Bian J., Liang H., Huang Z., Wen X.

IEEE Internet of Things Journal 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the rapid development of the Internet of Things (IoT), security issues in resource-constrained devices have become increasingly critical. Physical Unclonable Function (PUF) exploits unavoidable process variations introduced during IC manufacturing to generate unique responses and has been widely used for device authentication and cryptographic key generation. Among various PUF architectures, the Arbiter PUF (APUF) can generate a large number of challenge-response pairs (CRPs) with low hardware overhead. However, its reliability is highly sensitive to environmental variations and device aging, which may degrade the security of authentication protocols. In this paper, a challenge-response remapping reliability enhancement method for APUF based on adjacent challenge-bit flipping is proposed. First, a machine learning (ML) algorithm is employed to construct a software model of the APUF. A delay difference threshold is then introduced to identify challenges whose accumulated propagation delay differences fall below the threshold. Subsequently, specific adjacent bits in these challenges are flipped to transform them into highly reliable challenges. The proposed method is evaluated through Python-based simulations and FPGA-based hardware measurements. Experimental results show that the simulated reliability of the APUF can be improved to 100% under three environmental noise conditions. Moreover, within a temperature range from −20°C to 80°C, the measured reliability of the APUF can also reach 100% without reducing the number of available CRPs. Therefore, the proposed method significantly improves the reliability of APUFs without introducing additional hardware overhead or reducing the number of available CRPs, providing an effective solution for high-reliability authentication in IoT devices.

DOI： 10.1109/JIOT.2026.3731598

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A method for integrated circuit trimming focused on separation of trim codes 査読有り国際誌

Zhan W., Zhou Y., Zheng J., Wen X.

Microelectronics Reliability 174 2025年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In advanced processes, the addition of trimming circuits can effectively improve the yield of high-end chips. However, the mapping relationship between trimming parameters and trim codes in traditional methods is often segmented and discontinuous. This paper proposes a method that separates the trim codes into computational trim codes and applied trim codes. By reconstructing the mapping relationships between trimming parameters and computational trim codes, as well as between computational trim codes and applied trim codes, the proposed method achieves a linear mapping relationship between trimming parameters and computational trim codes, and a logical relationship between computational trim codes and applied trim codes. This novel method effectively reduces the number of trimming iterations and trimming time, thereby improving trimming efficiency. Two different hardware and software-based implementations have been designed to validate its feasibility. Experiments using two optimization algorithms demonstrate that trimming time can be reduced by an average of 44.97% and 40.00%, respectively, fully validating the effectiveness of the proposed method.

DOI： 10.1016/j.microrel.2025.115889

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105014926320&origin=inward

A lightweight general PUF framework for resisting machine learning attacks 査読有り国際誌

Ni T., Li F., Huang Z., Yan A., Wang S., Wen X., Nie M., Bian J.

Integration 104 2025年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

Physical Unclonable Function (PUF) is an attractive and low-cost security primitive that requires no storage and is resistant to reverse engineering. However, classical PUFs are highly vulnerable to machine learning attacks, and most attempts to resist these attacks consume excessive resources. To address this challenge, a lightweight general PUF framework is proposed in this paper. Firstly, the framework adopts segmentation processing to introduce structural nonlinearities for the purpose of self-protection. Secondly, the pre-segment response, pre-segment challenges and post-segment challenges undergo XOR processing to introduce challenges obfuscation, which greatly enhances the machine learning resistance of the PUF. In addition, for configurable RO PUF, a novel MUX-based RO (called MRO) is proposed in this paper, which can save resources by 50 %. Implementing a two-segment MRO-MRO instance based on the proposed PUF framework results in reliability, uniformity, and uniqueness that are close to the ideal values. Comprehensive experiments demonstrate that the proposed PUF has the advantages of scalable framework, low resource overhead, and strong resistance to machine learning attacks.

DOI： 10.1016/j.vlsi.2025.102459

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SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices 査読有り国際誌

OKAMOTO Hisashi, WEI Shaoqi, WANG Senling, KAI Hiroshi, TAKAHASHI Hiroshi, HIGAMI Yoshinobu, SHIMIZU Akihiro, NI Tianming, WEN Xiaoqing

Journal of Communications ( Engineering and Technology Publishing ) 20 ( 2 ) 214 - 220 2025年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

Joint Test Action Group (JTAG) interface is widely used in integrated circuits for functional testing and in-system debugging, ensuring high reliability throughout the silicon life cycle. However, it has also been identified as a potential vulnerability to the cyberattacks. Traditional security countermeasures such as adding authentication mechanism to restrict access to authorized users, often rely on uniform authentication credentials. This approach poses challenges for edge devices with varying computational capacities. Moreover, strengthening authentication security can lead to compatibility issues with embedded hardware on client devices, limiting scalability. To address these challenges, we propose Simple and Secure password authentication protocol, Light processing version based Joint Test Action Group plus Version (SASL-JTAG+), an enhanced JTAG authentication mechanism utilizing the Simple and Secure Password Authentication Protocol, Light Processing Version (SAS-L) protocol that enables one-time password authentication with adjustable bit lengths, tailored to the computational capacities of authenticators and target devices. The new approach provides robust security for devices with performance and cost constraints, offering flexible authentication data within a unified system. As a result, SASL-JTAG+ provides a scalable, long-term solution for securing IoT systems accommodating both legacy and modern devices while adapting to evolving technological demands.

その他リンク： https://ehime-u.repo.nii.ac.jp/records/2003018

An enhanced interlocked feedback structure-based dual-node upset resilient latch 査読有り国際誌

Bai N., Liu Z., Wen X., Xu Y., Wang Y., Chen J., Zhu W.

Microelectronics Journal 157 2025年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the integrated circuit technology continues to scale down, the design of Double Node Upset (DNU) resilient latches has become a critical challenge in radiation-hardened design. Traditional designs of resilient latches are primarily based on the Dual Interlocked Storage Cell (DICE) and novel feedback mechanisms. However, these conventional approaches often suffer from significant limitations, such as instability or errors in logic states due to charge sharing during latching, or trade-offs among power consumption, delay, and area. To overcome these challenges, this paper proposes a DNU-resilient latch based on an enhanced interlocked feedback structure. The proposed ISR latch leverages its interlocked feedback mechanism to achieve self-recovery for the maximum number of double-node upset pairs. Simulation results based on the SMIC 28 nm process model demonstrate that the proposed latch can achieve self-recovery under any double-node disturbance. Compared to existing advanced DNU-resilient latches, the proposed design shows superior performance and power efficiency, achieving an average reduction of 81.67% in PDAP.

DOI： 10.1016/j.mejo.2025.106555

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A Method for Grading Failure Rates Within the Dynamic Effective Space of Integrated Circuits After Testing 査読有り国際誌

Zhan W., Zhou Y., Zheng J., Cai X., Zhang Q., Wen X.

Applied Sciences Switzerland 15 ( 4 ) 2025年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

Integrated circuits that pass testing still have quality differences, thus making grading necessary. Traditional grading methods rely on static testing and electrical measurements, which are challenging to achieve precise grading, time-consuming, and costly. A new grading method based on the failure rate within a dynamically effective space is proposed. This method dynamically adjusts the evaluation space and uses an exponential decay function to calculate the influence weight of each neighboring chip on the evaluated chip, thereby computing the weighted failure rate of the evaluated chip and quantitatively grading the chips after wafer testing based on the scores. Experiments show that this method not only accurately captures quality differences and ensures grading accuracy but also significantly improves grading efficiency.

DOI： 10.3390/app15042009

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TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications 査読有り国際誌

Yan A. (合肥工業大学), Zhang J., Xu X., Li H., Bai N., Huang Z., Wang X., Wen X., Girard P.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 10 ) 2783 - 2794 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In nanoscale CMOS technology, harsh radiations in the environment can now easily cause soft errors, e.g., single-event transients (SETs) and triple node upsets (TNUs), severely affecting the reliability of space applications. In this article, TNUs tolerant and SET-pulses filtered latch (TUTPFL) with low power is proposed, which comprises from four input-stage C-elements (CEs), four inverters, and three output-stage CEs. The CEs’ delay differential enables the TUTPFL latch to effectively filter SET-pulse, while the CEs’ multilevel error-interception property enables the TUTPFL latch to tolerate any possible TNU. The results of HSPICE-based simulations and FPGA-based emulations demonstrate the TNU tolerance and SET filterability of the TUTPFL latch. Meanwhile, compared to the alternative radiation-hardened latches, the TUTPFL latch reduces power dissipation by roughly 20.43% on average.

DOI： 10.1109/TVLSI.2025.3571607

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105007297855&origin=inward

RHT_NoC: A Reconfigurable Hybrid Topology Architecture for Chiplet-Based Multicore System 査読有り国際誌

Xu D., Zhou W., Huang Z., Liang H. (合肥工業大学), Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 8 ) 2104 - 2117 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Chiplet-based system-on-chip (SoC) architectures, leveraging 2.5-D/3-D integration technologies, provide scalable solutions for a wide range of applications. Achieving high performance and cost-effectiveness in these systems relies heavily on optimizing die-to-die interconnect topologies and designs, which are essential for seamless interchiplet communication. This article introduces a reconfigurable hybrid topology (RHT) architecture designed for chiplet-based multicore systems. RHT achieves high performance and energy efficiency by dynamically reconfiguring the network topology to traffic variations, adaptively selecting transport subnets, and optimizing link bandwidth allocation, thereby minimizing congestion and maximizing packet throughput. Furthermore, RHT leverages global traffic information to dynamically combine Torus loops, maximizing opportunities for rapid packet transmission delivery while guaranteeing minimal hop counts. Moreover, RHT accelerates packet transmission via bufferless combined loops, extending the continuous sleeping periods of routers, improves power gating efficiency, and significantly reduces static power consumption. Simulation results indicate that the Mesh-DyRing achieves over a 40% reduction in network latency and more than a 20% decrease in power consumption overhead compared to the baseline design. When compared to WiNoC, an advanced hybrid wired-wireless topology design, the Mesh-DyRing-PG configuration reduces power consumption by 56.2% while maintaining equivalent average network latency.

DOI： 10.1109/TVLSI.2025.3572112

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105007631291&origin=inward

SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices 査読有り国際誌

Okamoto H., Wei S., Wang S., Kai H., Takahashi H., Higami Y., Shimizu A., Ni T., Wen X.

Journal of Communications 20 ( 2 ) 214 - 220 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Joint Test Action Group (JTAG) interface is widely used in integrated circuits for functional testing and in-system debugging, ensuring high reliability throughout the silicon life cycle. However, it has also been identified as a potential vulnerability to the cyberattacks. Traditional security countermeasures such as adding authentication mechanism to restrict access to authorized users, often rely on uniform authentication credentials. This approach poses challenges for edge devices with varying computational capacities. Moreover, strengthening authentication security can lead to compatibility issues with embedded hardware on client devices, limiting scalability. To address these challenges, we propose Simple and Secure password authentication protocol, Light processing version based Joint Test Action Group plus Version (SASL-JTAG+), an enhanced JTAG authentication mechanism utilizing the Simple and Secure Password Authentication Protocol, Light Processing Version (SAS-L) protocol that enables one-time password authentication with adjustable bit lengths, tailored to the computational capacities of authenticators and target devices. The new approach provides robust security for devices with performance and cost constraints, offering flexible authentication data within a unified system. As a result, SASL-JTAG+ provides a scalable, long-term solution for securing IoT systems accommodating both legacy and modern devices while adapting to evolving technological demands.

DOI： 10.12720/jcm.20.2.214-220

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105004754770&origin=inward

Segmentation-Enhanced Overlapped Defect Identification for Multipatterns Wafer Maps 査読有り国際誌

Ni T., Jiang W., Liang H. (合肥工業大学), Wen X., Nie M.

IEEE Transactions on Instrumentation and Measurement 74 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Due to the high complexity of the semiconductor manufacturing process, failures frequently occur. Moreover, there is a rising likelihood of multipattern defects appearing and overlapping on the wafer maps (WMs). Previous studies on defect patterns mainly focus on the classification of wafer defects, and these methods cannot provide effective defect location information for overlapped defect types. To solve this problem, a segmentation-enhanced overlapped defect identification (SEODI) framework is proposed in this article. This framework adeptly extracts and learns features from overlapped wafer defects and detects defects on WMs. Specifically, the wafer defects are categorized into two types—non-overlapped and overlapped and the model is subsequently trained accordingly. The trained model exhibits the capability to detect the non-overlapped defects, identify the overlapped defects, and send them into the U-net network for segmentation. After segmentation, the data is fed back into the detection model for further training. Additionally, we propose a data augmentation method to improve the efficiency of overlapped defect recognition. This method effectively addresses the challenge of detecting the multipattern defects in the semiconductor industry. Experimental findings, utilizing the universal defect dataset MixedWM38, demonstrate that the proposed method achieves an accuracy of 89.3% for overlapped type recognition, coupled with an impressive 89% mean average precision (mAP) for defect localization.

DOI： 10.1109/TIM.2025.3565049

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105005117747&origin=inward

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