研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 61 - 80 件目／全件表示 >>

Reconfigurable Fault-Tolerant Link With Bandwidth Expansion for 2.5-D Chiplet-Based Systems 査読有り国際誌

Zhou W., Xu D., Xu S., Luo L., Chen F., Ni T., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 11 ) 3043 - 3056 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

The 2.5-D chiplet-based systems offer a promising path toward higher performance and integration density, but the reliability of interchiplet links, particularly vertical links (VLs), poses a significant challenge. This article proposes reconfigurable bidirectional link (ReBL), a novel architecture providing robust fault tolerance and enhanced bandwidth for these critical interconnects. ReBL features three key innovations: 1) a robust fault-tolerant mechanism leveraging ReBLs that dynamically adapts to and mitigates permanent link failures; 2) a dynamic bandwidth expansion technique that significantly enhances the system efficiency by utilizing idle links to optimize resource allocation and throughput; and 3) a virtual channel (VC) allocation strategy that guarantees deadlock-free operations through strategic channel partitioning and assignment. Evaluations using synthetic traffic and PARSEC benchmarks demonstrate ReBL’s significant advantages under high fault rates. Compared with the state-of-the-art reliable and deadlock-free routing (ReD) approach, ReBL achieves an average reduction of 21.3% in packet latency and 4.9% in application execution time across the evaluated benchmarks. These benefits are achieved with only a 6.06% area overhead over baseline.

DOI： 10.1109/TVLSI.2025.3592915

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A Low-Cost Input-split Inverter-based Triple-Node-Upset Recoverable Latch Design 査読有り国際誌

Bai N., Xu P., Xu Y., Yan A., Wen X., Wang S., Xia Y.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 45 ( 4 ) 1963 - 1974 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the integration level of integrated circuits continues to increase and the feature size of nanoscale chips continues to shrink, the possibility of triple-node-upsets (TNUs) occurring in circuits increases significantly. This paper proposes a latch, namely CLTNUSL, which offers stable resilience against TNUs in radiative environments while achieving a good balance between reliability and overhead. Unlike the conventional latches consisting of multi-input C-elements, the proposed CLTNUSL latch mainly consists of 16 interlocked dual-input inverters. Due to the small number of transistors, CLTNUSL achieves low area overhead. Due to the use of high-speed paths and clock gating techniques, CLTNUSL achieves low latency and low power consumption. Simulation results demonstrate CLTNUSL's full recovery from TNU in all scenarios. Compared with the conventional TNU-hardened latch, CLTNUSL achieves minimal latency, power consumption, area overhead, and the delay-power-area product (DPAP). CLTNUSL reduces delay by 13.22%, power by 52.74%, area by 40.90%, and DPAP by 71.44% on average, compared with state-of-the-art latches. Process-Voltage-Temperature (PVT) and Monte Carlo simulation results show that the CLTNUSL latch is less sensitive to temperature, voltage and process variations compared with conventional TNU self-recovery latches.

DOI： 10.1109/TCAD.2025.3605516

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An Accelerated Newton-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization 査読有り国際誌

Zhou C., Cao Y., Yang F., Wen X., Shi Q., Rong R., Yang A.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 45 ( 3 ) 1535 - 1548 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

The advancement of technology nodes has intensified the focus on mixed-cell-height circuit design, posing challenges to traditional legalization techniques. In this paper, we propose a novel and efficient accelerated Newton-based matrix splitting (ANMS) iteration method to address the mixed-cell-height circuit legalization problem. Our approach reformulates this problem into a generalized absolute value equation and leverages matrix splitting and the latest estimate vector to enhance computational efficiency. We also introduce a relaxation variant within the ANMS framework, namely, the accelerated Newton-based successive overrelaxation (ANSOR) method, which is particularly effective in scenarios requiring high computational performance and precise parameter tuning. The proposed method achieves linear computational complexity. Furthermore, we perform an in-depth analysis of the sufficient convergence conditions for the ANMS method and optimize cells that have excessive displacement. Experimental results show that the proposed ANMS method achieves a speedup of 1.09× - 4.94× compared to state-of-the-art methods, while maintaining the quality of solution. This makes it highly suitable for addressing complex placement design challenges.

DOI： 10.1109/TCAD.2025.3593205

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NVLIM: MTJ and CMOS-Based Nonvolatile Latch Design With Protection Against Triple-Node-Upsets for Robust Computing 査読有り国際誌

Yan A., Zhang Y., Wang L., Huang Z., Zhang Q., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 34 ( 1 ) 268 - 279 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Soft errors and power dissipation emerge as critical challenges in developing high-reliability and cost-sensitive embedded systems. To address these issues, the magnetic tunnel junction (MTJ) is considered a promising solution due to its nonvolatility and its compatibility with traditional CMOS manufacturing processes. In this work, we propose a novel nonvolatile (NV) latch consisting of inverters and MTJs, namely, NVLIM, which provides nonvolatility and robust partial tolerance against triple-node-upsets (TNUs) at low cost. NVLIM integrates a TNU-tolerant block based on CMOS with a backup-restore block using MTJs. Simulation results incorporating process, voltage, and temperature (PVT) variations, bias temperature instability (BTI) impact, and Monte Carlo simulations demonstrate the balanced performance in terms of nonvolatility, robust partial TNU tolerance, and comprehensive overhead of the proposed latch.

DOI： 10.1109/TVLSI.2025.3614568

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QtNURAV: A Robust Latch Design with Quintuple Node Upset Recovery and Algorithm based Verifications for Aerospace Applications 査読有り国際誌

Yan A., Li J., Bao H., Ni T., Huang Z., Liang B., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 6 ) 18543 - 18554 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the continuous scaling of transistor feature sizes to the deep nano-scale, modern circuits have become increasingly sensitive to radiation-induced soft errors, such as multiple node upset (MNU). Especially, due to charge-sharing, the striking of one high-energy radiative particle can simultaneously impact multiple adjacent nodes of a highly integrated circuit causing MNU, e.g., quintuple node upset (QtNU) and even more node upsets. Existing MNU-hardened latch designs cannot provide QtNU recovery, and their robustness verification heavily depends on electronic-design-automation tools. In this paper, we present a robust latch, namely QtNURAV, to protect against QtNU for aerospace applications, along with an algorithm-based QtNU recovery verification method. The latch mainly employs four parallel dual-interlocked cells (DICEs) that feed each other through eight 3-input inverters to robustly retain values. The proposed algorithm simplifies the fault-tolerance verification process, demonstrating the QtNU recovery of QtNURAV. Simulation results based on HSPICE show that the QtNURAV latch can self-recover from any possible QtNU and has low delay and power consumption. Compared to existing Quadruple Node Upset hardened latches, the proposed QtNURAV latch provides QtNU recovery and effectively reduces delay, power and delay-power-area comprehensive product by 33.3%, 30.1%, and 53.3% on average, respectively.

DOI： 10.1109/TAES.2025.3612904

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A Parallel Feedback Obfuscation Strong PUF against Machine-Learning Modeling Attacks and Lightweight Authentication Protocol 査読有り国際誌

Huang Z., Lin Y., Wang Z., Lu Y., Liang H., Bian J., Ouyang Y., Ni T., Wen X.

IEEE Transactions on Dependable and Secure Computing 23 ( 2 ) 3051 - 3067 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Arbiter physical unclonable function (APUF) is a hardware security primitive that generates security keys by utilizing unavoidable process variations during chip manufacturing. However, the structure based on linear additive function makes it vulnerable to machine learning (ML) attacks. This paper proposes a parallel feedback obfuscation PUF (PFO PUF) design, which uses intermediate arbitration signals of the lower-layer APUF to generate the hidden challenge of the upper-layer APUF, enhancing the overall nonlinearity of the structure. The obfuscation module makes weight judgment for intermediate arbitration signals of upper-layer and lower-layer APUFs, which obfuscates the real response of PUF. We further design a variant of PFO PUF called reconfigured challenge obfuscation PFO PUF (RPFO PUF) and propose its lightweight device authentication protocol. RPFO PUF enhances the resistance of the original PFO PUF against reverse engineering (RE) and improves its Strict Avalanche Criterion (SAC) characteristic by reordering the challenges and incorporating weak PUF responses. The proposed PFO PUF and RPFO PUF were comprehensively evaluated via Python-based simulations and FPGA measurements. In Python simulations, both designs show strong resistance to state-of-the-art ML attacks, with logistic regression (LR), support vector machine (SVM), and covariance matrix adaptation evolution strategies (CMA-ES) yielding near 50% prediction accuracies under various PUF configurations. Although deep neural network (DNN) achieves up to 69.52% prediction accuracy on the PFO PUF, it drops to ∼50% on the RPFO PUF. FPGA results further confirm this, with the (32, 11)-RPFO PUF achieving a maximum prediction accuracy of only 51.47% across all four ML attacks. Moreover, both designs incur low hardware overheads, requiring just 743 and 2145 gate equivalents (GEs), respectively.

DOI： 10.1109/TDSC.2025.3632835

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Radiation-Hardened SRAM Designs for Self-Recovery From All Single-and Double-Node Upsets 査読有り国際誌

Yan A., Li J., Li K., Wang W., Huang Z., Ni T., Wang Q., Girard P., Wen X.

IEEE Transactions on Device and Materials Reliability 26 ( 1 ) 167 - 177 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the progress of semiconductor technology, transistor dimensions are continuously shrinking, and thus the sensitivity of static random-access memories (SRAMs) to radiation induced soft errors is increasingly severe. Single-node upsets (SNUs) as well as double-node upsets (DNUs) caused by high-energy radiative particles are typical soft errors. In order to solve this problem, this paper presents two radiation-hardened robust SRAM cells, i.e., RH33T and RH29T, based on multi-input inverters. They primarily use nine multi-input inverters to form the cross-coupled feedback mechanism for enabling the cells to recover quickly when impacted by SNUs or DNUs. HSPICE-based simulation results confirm that the RH29T and RH33T cells can fully tolerate SNUs and DNUs with good reliability and have moderate read/write access speeds and power overhead. In addition, Virtuoso-based simulation results show that the RH29T and RH33T have a moderate tolerance for static noise margin (SNM).

DOI： 10.1109/TDMR.2025.3641827

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LLM-Design Platform for Thermal-Failure-Aware 3D Chiplet Layout via Iterative Parameter Analysis 査読有り国際誌

Song T., Wang S., Wen X.

Proceedings 2025 IEEE 34th Asian Test Symposium Ats 2025 55 - 60 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Although advanced 3D chiplet packaging helps extend Moore's-Law gains through vertical stacking of heterogeneous dies, it simultaneously introduces unprecedented thermal challenges. Shrinking 3D interconnects and rising current densities trap heat at through-silicon vias (TSVs) and micro-bumps, causing steep temperature gradients and thermo-mechanical stress that directly trigger early failures. Existing methods interact with finite-element analysis (FEA) tools mainly through manual, experience-based parameter tuning, inevitably making hot-spot detection time-consuming and error-prone. This paper establishes a text-interactive, thermal-failure-aware design framework for 3D chiplets that couples large language model (LLM)-accelerated thermal analysis with FEA simulation. A Python-driven Automatic Code Generation Model (ACGM) is invoked to automate geometry drawing, meshing, and boundary-condition assignment, enabling rapid analysis and prediction of hot-spot locations within densely stacked chiplets and TSVs. The proposed ACGM eliminates domain-expert dependence by abstracting cumbersome FEA parameter setting into natural-language commands, thereby lowering the entry barrier and cutting operation time. Deployment of the proposed ACGM streamlines intricate FEA operations and Python scripting into concise natural-language commands, enabling accurate layout-parameter tuning and shortened design cy-cles-establishing an AI-centric design-verification paradigm for advanced 3D chiplets.

DOI： 10.1109/ATS66998.2025.00018

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Radiation-Resistant ZnO Thin-Film Transistor Voltage Reference 査読有り国際誌

Bai N., Ge G., Li H., Wu Y., Yan A., Wen X.

Proceedings 2025 IEEE 34th Asian Test Symposium Ats 2025 103 - 108 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a radiation-tolerant voltage reference circuit based on atomic layer-deposited zinc oxide thinfilm transistors (ZnO TFTs), where both active and floating gate layers utilize ZnO films. Employing a dual-exponential current source method, we accurately simulate single-event transient currents induced by high-energy particles. Measurement results demonstrate that the proposed circuit achieves 5 μs recovery time without radiation hardening, reducible to 1μs with hardening techniques. The circuit generates a 3.1 V reference voltage operating from 6 V to 10 V supply, with 18.78 mV/V line sensitivity and 0.72 μW static power consumption. Temperature stability is achieved through a complementary temperature coefficient. From 0°C to 80°C, the temperature coefficient of VREF is 79.56 ppm/°C, and the PSRR reaches -36.5 dB.

DOI： 10.1109/ATS66998.2025.00026

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Software-Defined Secure Island for Testing Chiplet Systems 査読有り国際誌

Okamoto H., Wang S., Kai H., Yotsuyanagi H., Higami Y., Ni T., Song T., Takahashi H., Wen X.

Proceedings 2025 IEEE 34th Asian Test Symposium Ats 2025 61 - 66 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Chiplet systems that stack heterogeneous dies via 2.5D/3D integration use JTAG-based test access ports (TAPs) to validate inter-die links and enable in-field diagnosis. However, these TAPs create a shared attack surface: penetrating a single die can potentially expose control of the entire stack. Current countermeasures involve embedding a complete cryptographic engine in each chiplet, which increases the area and locks the protocol at tape-out, leaving it susceptible to future unknown attacks. This paper proposes a Software-Defined Secure Island (SDSI) architecture that decouples security policies from hardwired logic while satisfying non-functional requirements. Each chiplet instantiates an ultra-lightweight Secure Island Controller (SIC) macro that performs only two XORs and two additions per handshake. Meanwhile, a centralized secure island runs heavyweight cryptography in firmware using the multi-round SASL-JTAG+ protocol. SDSI enables scalable, adaptable test access protection by decoupling security from hardware. An FPGA implementation shows that the SIC macro occupies 11% of the area of an AES- 128 core and 37% of a SHA256 core, yet it supports 256 - to 512-bit keys with negligible growth. A security analysis demonstrates immunity to replay attacks because the authentication data is refreshed with each session. All future upgrades, such as longer keys, stronger hashes, and additional rounds, are delivered via firmware, providing scalable, field-upgradable protection for heterogeneous chiplet systems.

DOI： 10.1109/ATS66998.2025.00019

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A Robust Newton Iteration Method for Mixed-Cell-Height Circuit Legalization under Technology and Region Constraints 査読有り国際誌

Zhou C., Cao Y., Shi Q., Wang L., Wen X.

ACM Transactions on Design Automation of Electronic Systems 29 ( 6 ) 2024年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

The evolution of advanced technology nodes has prompted a shift toward mixed-cell-height circuit design, while the introduction of technology and fence region constraints further increases the complexity of placement. In this article, we innovatively transform the mixed-cell-height circuit legalization problem into a generalized absolute value equation (GAVE) and propose a novel and effective robust Newton (RN) iteration method to address the challenge of the legalization problem.<sup>1</sup> First, the window-based cell insertion technique is applied to obtain the initial cell row allocation and cell order, and the cells are allocated to the matching region based on the R-tree structure. Then, the legalization problem of cells within the region is transformed into a GAVE, and an RN iteration method is proposed to solve the GAVE. Finally, the maximum displacement cells and technology violation cells are optimized based on a greedy method. Experimental results confirm the efficiency and robustness of the proposed method compared with the state-of-the-art methods.

DOI： 10.1145/3689436

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MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method 査読有り国際誌

Yan A. (合肥工業大学), Li Z., Gao Z., Zhang J., Huang Z., Ni T., Cui J., Wang X., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43 ( 7 ) 2205 - 2214 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability of latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. In this article, we propose a novel latch, namely, MURLAV, protected against quadruple node-upsets (QNUs) induced in harsh radiation environments, as well as an algorithmic error-recovery verification method. The latch provides complete recovery from all QNUs with a formed redundant structure. The algorithm can simplify the verification process and demonstrate the QNU recovery for the proposed MURLAV latch. Simulation results demonstrate that the proposed latch can recover from any QNU and that it has lower area and delay overhead. Compared with existing latches of the same type, the proposed MURLAV latch achieves an overhead reduction of 34% in silicon area and 15% in delay on average at the cost of moderate power consumption.

DOI： 10.1109/TCAD.2024.3357593

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A new die-level flexible design-for-test architecture for 3D stacked ICs 査読有り国際誌

Zhang Q., Zhan W., Wen X.

Integration 97 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

DOI： 10.1016/j.vlsi.2024.102190

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Efficient design approaches to CMOS full adder circuits 査読有り国際誌

Yan A., Bao H., Jiang W., Cui J., Huang Z., Wen X.

Microelectronics Journal 149 2024年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %.

DOI： 10.1016/j.mejo.2024.106235

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IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications 査読有り国際誌

Yan A., Dong C., Guo X., Song J., Cui J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 19 - 24 2024年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Modern powerful CMOS chips are usually highly integrated and implemented with aggressively shrunk technology nodes. In radiation environment, under charge-sharing mechanism, one particle striking can simultaneously impact multiple nodes causing double-node-upsets (DNUs) and triple-node-upsets (TNUs). In this paper, we propose an Interlocked Dual-circle Latch Design, namely IDLD, with low cost and TNU recovery for aerospace applications. IDLD consists of four transmission gates and twelve 2-input C-elements (CEs) implemented in 22nm CMOS process. Simulation results demonstrate the complete TNU recovery as well as cost-effectiveness for the proposed IDLD latch.

DOI： 10.1145/3649476.3658761

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A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors 査読有り国際誌

Xu H., Li J., Ma R., Liang H. (合肥工業大学), Liu C., Wang S., Wen X.

IEEE Transactions on Device and Materials Reliability 24 ( 2 ) 302 - 312 2024年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations.

DOI： 10.1109/TDMR.2024.3386954

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FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell 査読有り国際誌

Yan A., Chen Y., Gao Z., Ni T., Huang Z., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 71 ( 4 ) 2299 - 2303 2024年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

The Von-Neumann memory wall bottleneck that keeps expanding is mainly caused by the frequent data transfer between the main memory and the processor. The processing in-memory (PiM) capabilities of emerging nonvolatile devices have the potential to partially alleviate the memory wall problem. In this brief, we use the ferroelectric field-effect transistor (FeFET), one of the emerging nonvolatile devices, to design a multifunctional processing in-memory cell, namely FeMPIM. It can perform multiple logic operations in computing mode as well as content searching in ternary content-addressable memory (TCAM) mode. Simulation results demonstrate the multifunctional capability of the proposed FeMPIM as well as its moderate overhead when compared with the complementary metal-oxide-semiconductor (CMOS) based and the existing FeFET-based devices.

DOI： 10.1109/TCSII.2023.3331267

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SwinT-ILT: Swin Transformer embedding end-To-end mask optimization model 査読有り国際誌

Xu H., Qi P., Tang F., Ma R., Liang H., Huang Z., Wen X.

Journal of Micro/Nanopatterning, Materials and Metrology 23 ( 1 ) 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Background: Resolution enhancement techniques (RETs) are widely used to improve the quality of masks in lithography flow. Optical proximity correction (OPC), such as inverse lithography technology (ILT), improves mask printability, but conventional ILT suffers from computational overhead. Advanced learning-based methods accelerate the optimization process, but the quality of its mask could be more satisfactory to academia and industry. Aim: To improve the quality of masks while accelerating the optimization process, we propose SwinT-ILT, an end-To-end ILT optimization framework embedded in the Swin Transformer. Approach: The framework consists of a feature extraction module and a feature construction module. Leveraging the Swin Transformer, the feature extraction module extracts deep features, and the feature construction module reconstruct masks based on in-depth features. To enhance the resolution of feature maps without introducing noise, we incorporate a pixel shuffle layer into the feature construction module. Furthermore, we set a specific training objective that introduces the domain knowledge of the imaging system, thereby accelerating the convergence. Results: Quantitative results show that our SwinT-ILT achieves exceptional mask printability with relative mask manufacturability in only 0.5 s turnaround time. Conclusions: Our work contributes to the industry by effectively reducing semiconductor manufacturing cycles and enhancing manufacturing quality.

DOI： 10.1117/1.JMM.23.1.013201

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Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS 査読有り国際誌

Yan A., Wang L., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32 ( 1 ) 116 - 127 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) are widely used to address these concerns. MTJs are nonvolatile (NV) and compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant and NV latch, i.e., M-TPDICE-V2, providing high reliability. In addition, we further propose an advanced latch, namely, M-8C, that is able to completely recover from single-node upsets (SNUs) and DNUs. M-8C uses a DNU recovery module and a backup and restore module based on a pair of MTJs. Furthermore, we propose a universal backup and restore module suitable for any latch providing nonvolatility. We simulate the proposed latches using the Synopsys HSPICE tool with a 45-nm CMOS process model. Simulation results confirm the superior capabilities of our proposed M-TPDICE-V2 and M-8C latches. M-TPDICE-V2 exhibits strong SNU and DNU tolerance and nonvolatility, while the M-8C latch provides complete DNU recovery capabilities.

DOI： 10.1109/TVLSI.2023.3323562

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85174840567&origin=inward

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs 査読有り国際誌

Wang S., Wei S., Okamoto H., Nishikawa T., Kai H., Higami Y., Yotsuyanagi H., Ma R., Ni T., Takahashi H., Wen X.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel Test Point Insertion (TPI) strategy to enhance the testability for multi-cycle Built-In Self-Test (BIST) for logic circuits. The approach leverages Multivariate Temporal-Spatial Graph Convolutional Neural Networks (MTS-GCN) and Reinforcement Learning to identify optimal Test Points (TPs). The proposed TPI method treats the testability information of a logic circuit as time-series data and employs Multivariate Time-Series Graph Neural Networks (MTGNN) to capture the relationship between the circuit's structural (spatial information) attributes and the temporal variability of signal line testability across capture cycles. A subsequent Multi-Layer Perceptron (MLP) computes the metric for each signal line to pinpoint potential TPs based on the extracted temporal-spatial features. Experimental evaluation based on benchmark circuits confirms the efficacy of the proposed model, which is trained with Deep Q-Networks (DQN), in improving the fault detection for multi-cycle logic BIST.

DOI： 10.1109/ITC-Asia62534.2024.10661324

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85204766334&origin=inward

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