研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 61 - 80 件目／全件表示 >>

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits 査読有り国際誌

Utsunomiya T., Hoshino R., Miyase K., Lu S.K., Wen X., Kajihara S.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 43 - 48 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

High power consumption in LSI testing may cause excessive IR-drop. When IR-drop becomes excessive, it causes excessive delay, resulting in test malfunction (over-testing). Excessive IR-drop does not occur in the entire area of a circuit, but in certain areas where a large number of switching activities occur (such areas are called hotspots in this work). In order to avoid test malfunction, it is important to develop a method to reduce or control IR-drop in the hotspots. Locating hotspots is a necessary technique to reduce or control IR-drop effectively and efficiently. In this work, we propose a method to locate hotspots in a logic circuit by switching probability calculation. Experimental results for IWLS2005 OpenCores circuits demonstrate the proposed method can support to locate hotspots.

DOI： 10.1109/ITCAsia55616.2022.00018

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Power-Aware Testing in the Era of IoT 査読有り国際誌

Wen X.

Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022 2022年01月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

IoT devices are increasingly employed in various applications. Due to their intrinsic power supply limitation, IoT devices are usually designed with extremely low functional power dissipation. However, the testing of IoT devices has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper highlights the impact of excessive scan test power and points out the importance of power-aware testing for IoT devices.

DOI： 10.1109/ICSICT55466.2022.9963241

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Power and Energy Safe Real-Time Multi-Core Task Scheduling 査読有り国際誌

Baita K., Chakrabarti A., Chatterjee B., Holst S., Wen X.

Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 16 - 21 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scheduling tasks in multi-core real-time systems (e.g. low power devices/appliances) while keeping energy in mind is a difficult design challenge. Extensive work has been done to overcome this issue, in which task instances (jobs) have varying levels of operation power. Different combinations of system energy (SE) and subsequent minimal SE have been attained based on the power levels. However, both system power (SP) and system energy (SE) are expensive to operate. As a result, task scheduling for multi-core systems based on balancing both the SP and the SE (referred to as feasible SP and feasible SE, respectively) to achieve the lowest system cost is an issue that has not been adequately addressed in the literature. The states or zones of feasible SP (FSP) and feasible SE (FSE) are thought to be possible zones/states of the system where the system's power configuration provides lowered SE with increased job accommodation, lowering the system's cost. We offer a unique scheduling approach in which we identify numerous FSP and FSE zones (feasible zones/states) to fit all jobs to cores while minimising system cost (including optimum cost) and meeting deadlines. By giving weights to the FSP and FSE, we present a mechanism for ranking the many viable system states. The model is tested using produced task sets (low power task sets), and the results reveal that our approach effectively finds feasible zones, including the best one.

DOI： 10.1109/VLSID2022.2022.00016

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A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC 査読有り国際誌

Ni T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40 ( 9 ) 1952 - 1956 2021年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%-99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%-86.85% (46.01%-55.96%), 66.89%-73.25% (29.41%-38.49%), 68.02%-74.20% (41.40%-52.20%), 60.60%-68.18% (18.09%-33.18%), and 75.86%-80.52% (3.05%-20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay.

DOI： 10.1109/TCAD.2020.3025169

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Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications 査読有り国際誌

Yan A., Cao A., Xu Z., Cui J., Ni T., Girard P., Wen X.

Journal of Electronic Testing: Theory and Applications (JETTA) 37 ( 4 ) 489 - 502 2021年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

DOI： 10.1007/s10836-021-05962-0

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A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments 査読有り

Yan A., Cao A., Fan Z., Xu Z., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 301 - 306 2021年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state (HIS) insensitive latch design, namely QRHIL, for highly robust computing in harsh radiation environments. The latch mainly comprises a 5×5 looped C-element matrix to store values and provide complete 4NU recovery. Owing to the multiple-level error-interception of the 5×5 C-element matrix, the latch can recover from all possible 4NUs; thus, the latch is insensitive to HIS. Simulation results demonstrate the 4NU-recovery of the proposed latch. The results also show that the latch can approximately save 46% D-Q delay and 46% CLK-Q delay owing to the use of a high-speed D-Q path and clock-gating, compared with the state-of-the-art 3NU-recoverable latch (TNURL) that is not 4NU-recoverable.

DOI： 10.1145/3453688.3461493

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Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications 査読有り

Yan A., He Z., Zhou J., Cui J., Ni T., Huang Z., Wen X., Girard P.

Microelectronics Journal 111 2021年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

DOI： 10.1016/j.mejo.2021.105034

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A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology 査読有り

Ni T., Yang Z., Chang H., Zhang X., Lu L., Yan A., Huang Z., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 2 ) 724 - 734 2021年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

Through-silicon-vias (TSVs) are prone to defects during the manufacturing process, which pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is too great to be ignored, and in order to not use any redundant TSVs, a chain-type time division multiplexing access (TDMA)-based fault tolerance technique is proposed. However, a double-TSV structure is used per group, resulting in a significant TSV hardware overhead under a given large-scaled circuit design. Furthermore, it is impossible for the chain-TDMA scheme to plan the rerouting path for the right-hand-most TSV per group, resulting in a decrease in the repair rate per TSV group as well as in the whole TSV yield. In the proposed technique, we bundle six TSVs per group in a honeycomb pattern and the TSVs on the edges are connected to each other, enhancing the repair rate per group as well as the whole TSV yield. Subsequently, an architecture based on the proposed technique is designed, evaluated, and validated on logic-on-logic 3D IWLS'05 benchmark circuits using 45 nm TSMC technology. The proposed technique is found to reduce the area overhead by 87.95-90.42 percent, compared to the chain-TDMA scheme, which results in a yield of 96.90-99.09 percent.

DOI： 10.1109/TETC.2020.2969237

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Reliability-Driven Neuromorphic Computing Systems Design 査読有り

Xu Q., Wang J., Geng H., Chen S., Wen X.

Proceedings -Design, Automation and Test in Europe, DATE 2021-February 1586 - 1591 2021年02月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have provided a promising solution to the acceleration of neural networks. However, stuck-at faults (SAFs) in the memristor devices significantly degrade the computing accuracy of NCS. Besides, memristors suffer from process variations, causing the deviation of actual programming resistance from its target resistance. In this paper, we propose a novel reliability-driven design framework for a memristive crossbar-based NCS in combination with general and chip-specific design optimizations. First, we design a general reliability-aware training scheme to enhance the robustness of NCS to SAFs and device variations; a dropout-inspired approach is developed to alleviate the impact of SAFs; a new weighted error function, including cross-entropy error (CEE), the l2-norm of weights, and the sum of squares of first-order derivatives of CEE with respect to weights, is proposed to obtain a smooth error curve, where the effects of variations are suppressed. Second, given the neural network model generated by the reliability-aware training scheme, we exploit chip-specific mapping and retraining to further reduce the computation accuracy loss incurred by SAFs. Experimental results clearly demonstrate that the proposed method can boost the computation accuracy of NCS and improve the NCS robustness.

DOI： 10.23919/DATE51398.2021.9473929

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TPDICE and SIM based 4-node-upset completely hardened latch design for highly robust computing in harsh radiation 査読有り

Yan A., Ding L., Shan C., Cai H., Chen X., Wei Z., Huang Z., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2021-May 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Technology scaling and charge-sharing make nano-scale CMOS latches become severely vulnerable to multiple-node upsets (MNUs). This paper proposes a triple-path dual-interlocked-storage-cell (TPDICE) and soft-error interceptive module (SIM) based 4-Node-Upset (4NU) completely hardened latch, namely 4NUHL latch, that can completely tolerate soft errors, such as 4NUs. The latch mainly consists of 2 TPDICEs and a 3-level SIM which comprises six 2-input C-elements. Owing to the single-node-upset self-recoverability and multiple storage nodes of TPDICEs and the soft-error interception capability of the SIM, the latch can provide complete 4NU tolerance. Simulation results demonstrate that the proposed 4NUHL latch is completely 4NU hardened. Furthermore, we use a high-speed path, clock-gating, and a few transistors to reduce overhead of the proposed latch. We compared the proposed latch with state-of-the-art hardened latches in terms of reliability and overhead to demonstrate the advantages of the proposed latch.

DOI： 10.1109/ISCAS51556.2021.9401453

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On the efficacy of scan chain grouping for mitigating IR-drop-induced test data corruption 査読有り

Zhang Y., Holst S., Wen X., Miyase K., Kajihara S., Qian J.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E104D ( 6 ) 816 - 827 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Loading test vectors and unloading test responses in shift mode during scan testing cause many scan flip-flops to switch simultaneously. The resulting shift switching activity around scan flip-flops can cause excessive local IR-drop that can change the states of some scan flip-flops, leading to test data corruption. A common approach solving this problem is partial-shift, in which multiple scan chains are formed and only one group of the scan chains is shifted at a time. However, previous methods based on this approach use random grouping, which may reduce global shift switching activity, but may not be optimized to reduce local shift switching activity, resulting in remaining high risk of test data corruption even when partial-shift is applied. This paper proposes novel algorithms (one optimal and one heuristic) to group scan chains, focusing on reducing local shift switching activity around scan flip-flops, thus reducing the risk of test data corruption. Experimental results on all large ITC'99 benchmark circuits demonstrate the effectiveness of the proposed optimal and heuristic algorithms as well as the scalability of the heuristic algorithm.

DOI： 10.1587/transinf.2020EDP7042

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Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS 査読有り

Yan A., Lai C., Zhang Y., Cui J., Huang Z., Song J., Guo J., Wen X.

IEEE Transactions on Emerging Topics in Computing 9 ( 1 ) 520 - 533 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39 percent and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

DOI： 10.1109/TETC.2018.2871861

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Cellular Structure Based Fault-Tolerance TSV Configuration in 3D-IC 査読有り

Xu Q., Sun W., Chen S., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 5 ) 1196 - 1208 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement. But the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this paper, we propose an effective TSV repair strategy for the cellular TSV redundancy architecture, with taking account of the delay overhead. First, we prove that the cellular structure-based fault-tolerance TSV configuration with the delay constraint (CSFTC) is equivalent to the length-bounded multi-commodity flow (LBMCF) problem. Next, an integer linear programming formulation is presented to solve the LBMCF problem. Finally, to speed-up the fault-tolerance structure configuration process, an efficient Lagrangian relaxation based heuristic method is further proposed. Experimental results demonstrate that, compared with the state-of-the-art fault-tolerance structures, the proposed method can provide high yield and low delay overhead.

DOI： 10.1109/TCAD.2021.3084920

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GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning 査読有り国際誌

Xu Q., Geng H., Chen S., Yuan B., Zhuo C., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3492 - 3502 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Electronic Design Automation (EDA) comprises a series of computationally difficult optimization problems that require substantial specialized knowledge as well as a considerable amount of trial-and-error efforts. However, open challenges including long simulation runtime and lack of generalization continue to restrict the applications of existing EDA tools. Recently, learning-based algorithms especially reinforcement learning (RL) have been successfully applied to handle various combinatorial optimization problems by automatically acquiring knowledge from the past experience. In this paper, we formulate the floorplanning problem, the first stage of the physical design flow, as a Markov Decision Process (MDP). An end-toend learning-based floorplanning framework GoodFloorplan is proposed to explore the design space, which combines graph convolutional network (GCN) and RL. Experimental results demonstrate that, compared with state-of-the-art heuristic-based floorplanners, the proposed GoodFloorplan can provide better area and wirelength.

DOI： 10.1109/TCAD.2021.3131550

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Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure 査読有り国際誌

Xu Q., Ni T., Geng H., Chen S., Yu B., Kang Y., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 ( 10 ) 3182 - 3187 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this paper, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration with the delay constraint (RFSC) is equivalent to the length-bounded multi-commodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. Experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead.

DOI： 10.1109/TCAD.2021.3133484

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A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch 査読有り国際誌

Yan A., Qian K., Cui J., Cui N., Ni T., Huang Z., Wen X.

2021 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As transistor feature sizes continue to scale down, the susceptibility of integrated circuits to harsh-radiation induced multiple-node-upsets (MNUs),such as double-node upsets (DNUs) and triple-node upsets (TNUs), is increasing. This paper presents an MNU self-recoverable hardened latch (namely SCDMSH) based on sextuple cross-coupled dual-interlocked-storage-cells (DICEs). The latch consists of eight transmission gates and six interlocked DICE cells. Due to the interlocking mechanism constructed from single-node-upset-self-recoverable DICE cells, the latch can self-recover from any possible single node upset (SNU), DNU and TNU. Simulation results validate the SNU, DNU and TNU self-recoverability of the proposed latch. Simulation results also demonstrate that the SCDMSH latch can approximately save 49% silicon area at the cost of moderate delay and power, compared with the state-of-the-art TNU self-recoverable reference latch (TNURL) of the same-type.

DOI： 10.1109/NANOARCH53687.2021.9642250

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A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets 査読有り国際誌

Yan A., Cao A., Qian K., Ding L., He Z., Fan Z., Wen X.

Proceedings - 2021 8th International Conference on Dependable Systems and Their Applications, DSA 2021 734 - 736 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a flip-flop (FF) that can tolerate double-node-upsets (DNUs). If the FF suffers from a DNU, it can still have a correct value on its output node. Simulation results demonstrate the FF's DNU tolerance, and also demonstrate that the proposed FF can save 92% delay, 55% power, and 28% area on average, compared to typical DNU hardened FFs, respectively.

DOI： 10.1109/DSA52907.2021.00108

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LSI Testing: A Core Technology to a Successful LSI Industry 招待有り査読有り国際誌

Wen X.

Proceedings of International Conference on ASIC 2021年01月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Despite its ever-growing importance in all innovation fields, such as automotive and IoT applications, the LSI industry is fragile due to its a weak technology-business chain. In addition, its products, namely LSI chips, are vulnerable to six risks (defective chip escape, radiation, aging, malicious attack, counterfeiting). LSI testing is the technology that is indispensable to mitigate these risks. This paper highlights the intent of LSI testing as well as its impact on the LSI industry.

DOI： 10.1109/ASICON52560.2021.9620418

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Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing 査読有り国際誌

Yan A., Zhai Z., Wang L., Zhang J., Cui N., Ni T., Wen X.

Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 2021年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of design and manufacturing technologies of nano-scale CMOS circuits, latches are becoming increasingly sensitive to multiple-node-upsets caused by harsh radiation effects. In this paper, a Parallel Dual-interlocked-storage-cells (DICEs) and Dual-level C-elements (CEs) based 3-node-upset (3NU)-Tolerant Latch, namely PDDCTL, design for highly robust computing, is proposed. The latch comprises five transmission gates, two DICEs and three CEs. Due to the use of two single-node-upset self-recoverable DICEs and three error-interceptive CEs, the latch can provide complete 3NU-tolerance with low cost. Simulation results not only confirm the 3NU-tolerance of the proposed latch but also demonstrate that the delay-power-area product of the PDDCTL latch is reduced by 68.82% on average compared with the state-of-the-art 3NU hardened latch designs.

DOI： 10.1109/ITC-Asia53059.2021.9808602

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Novel Speed-and-Power-Optimized SRAM Cell Designs with Enhanced Self-Recoverability from Single- And Double-Node Upsets 査読有り

Yan A., Chen Y., Hu Y., Zhou J., Ni T., Cui J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 12 ) 4684 - 4695 2020年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

The continuous advancement of CMOS technologies makes SRAMs more and more sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-node upsets (DNUs). First, the S4P8N cell that has more redundant nodes and more access transistors is proposed. The cell has the following advantages: (1) it can self-recover from all possible SNUs; (2) it can self-recover from a part of DNUs; (3) it has small overhead in terms of power dissipation. Then, to reduce read and write access time, the S8P4N cell that uses a special feedback mechanism among its internal nodes is proposed. The cell has similar soft error tolerability as the S4P8N cell. Simulation results validate the high robustness of the proposed SRAM cells. These results also show that the write access time, read access time, and power dissipation of the S8P4N cell are reduced approximately by 29%, 20%, and 21% on average, at the cost of moderate silicon area, when compared with the state-of-the-art radiation-hardened SRAM cells.

DOI： 10.1109/TCSI.2020.3018328

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85097329770&origin=inward

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