研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 41 - 60 件目／全件表示 >>

Test and Diagnosis Strategies for Interchiplet Interconnects 査読有り国際誌

Liu X., Yang D., Zhang L., Ji S., Yan D., Wang Z., Guo Y., Wen X., Cai Z.

IEEE Transactions on Instrumentation and Measurement 74 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

The irregular through-silicon via (TSV) layout complicates the crosstalk's effect, making parallel testing more difficult. For efficient testing and diagnosis of irregular TSV layouts in postbonding, a novel test grouping algorithm based on neural networks is proposed. The influence range of crosstalk faults and the hardware overhead are both considered in the algorithm, maximizing the number of TSVs that can be tested simultaneously, thereby shortening both the test and diagnosis time. Based on the grouping results, an efficient built-in self-test (BIST) architecture with low hardware overhead for testing and diagnosing TSVs is proposed. Die wrapper register (DWR) cells of the IEEE Std 1838 are enhanced and diagnosis is embedded into the test process by improving test patterns and using an on-chip feature compression circuit. This approach supports testing, locating, and identifying stuck-at, bridge, delay, and crosstalk faults. Experimental results show that the test grouping algorithm reduces the average number of groups by 0.371, with more significant reductions observed in large-scale and highly complex settings. The proposed architecture achieves shorter test and diagnosis time to 7G+GN with lower hardware overhead, where G and N are the number of groups and TSVs, respectively.

DOI： 10.1109/TIM.2025.3548248

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Triple-Node-Upset Recovery High-Impedance-State Insensitive and Single-Event-Transient Filtering Latch for Aerospace Applications 査読有り国際誌

Yan A. (合肥工業大学), Lin Z., Xu Y., Bai N., Cui J., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 4 ) 10847 - 10854 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a 4×4-device-Matrix-based Cost-optimized Triple-node-upset (TNU)-recovery High-impedance-state (HIS)-insensitive and Single-event-transient (SET)-filtering Latch, namely MCTHSL, designed for aerospace applications. The MCTHSL latch comprises a 4×4-device matrix to completely provide TNU recovery and thus it is HIS-insensitive. The input of a Schmitt Trigger (ST) is split to create an input-split ST, namely ISST, to simultaneously provide the functions of a C-element (CE), a SET-filtering device and a delay element. The matrix comprises 15 mutually interlocking 2-input CEs as well as an ISST to store values, recover from TNUs and filter SETs with HIS-insensitivity and cost-optimization. Simulation results demonstrate the above-mentioned features as well as moderate sensitivity to the impacts of process, voltage and temperature (PVT) variations of our proposed MCTHSL latch in comparison with existing latches with TNU-recovery. The features are achieved at the cost of moderate overhead in terms of area, delay, and power.

DOI： 10.1109/TAES.2025.3546581

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Reconfigurable Radiation-Hardened SRAM Cell Design for Different Radiation Environments 査読有り国際誌

Bai N., Wang F., Xu Y., Wang S., Wen X.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 44 ( 9 ) 3581 - 3591 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a novel and effective 14T (14-transistors) reconfigurable radiation-hardened static-random access-memory (SRAM) cell design under the SMIC 65nm process, featuring a unique memory reconfigurability architecture with two operation modes, namely the high reliability (HR) mode and the triple-time memory (TTM) mode for meeting different radiation environmental requirements. The proposed HR mode provides strong protection of the memory arrays in harsh radiation environments. Compared with the traditional triple modular redundancy (TMR) structure, the proposed HR mode reduces area overhead by 30%, delay by 37%, and power consumption by 16%. The TTM mode uses the EN (enable) circuit to expand the capacity threefold in less harsh radiation environments, avoiding the area wastage caused by the traditional TMR structure. By implementing the two innovative operation modes, the proposed design overcomes the limitations of the traditional TMR structure, reducing area overhead while retaining the radiation hardening capability. In addition, this paper presents a mode-switching mechanism composed of a detection circuit and an EN circuit. The detection circuit can detect errors in the reconfigurable architecture. With the proposed mode-switching mechanism, two operation modes can switch in response to different radiation environments. Besides, to ensure the normal operations of the TTM mode in radiation environments, the proposed 14T cell serves as a bitcell in the memory reconfigurable architecture. Compared with typical existing designs, such as radiation-hardened based design (RHBD), writability enhanced (WE-Quatro), and dual interlocked storage cell (DICE) cells, the proposed 14T cell design has better delay, critical charge, and HSNM.

DOI： 10.1109/TCAD.2025.3541010

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NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead 査読有り国際誌

Yan A. (合肥工業大学), Jiang W., Bao H., Huang Z., Ni T., Wen X., Girard P.

Proceedings Design Automation and Test in Europe Date 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a FeFET-based non-volatile and single-event upset (SEU) recoverable latch, namely NVSRLO, which does not require any extra control signals. Simulation results show that the proposed latch provides non-volatility and SEU-recovery with optimized overhead. Compared with existing non-volatile latches, NVSRLO significantly reduces delay, power, and delay-power-area product at the cost of area.

DOI： 10.23919/DATE64628.2025.10993239

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A Low Cost Triple-Node-Upset Self-Recoverable Latch Design for Nanoscale CMOS 査読有り国際誌

Bai N., Zhang P., Xu Y., Guo Y., Li H., Wang Y., Wen X.

IEEE Transactions on Device and Materials Reliability 25 ( 2 ) 296 - 307 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Due to the constant reduction of semiconductor feature sizes, the charge sharing effect is getting worse. The occurrence probability of triple-node upset (TNU), which has a significant impact on the circuit’s reliability, is rising in nanoscale digital circuits. This paper proposes a low overhead and TNU self-recovery latch (TNU-SR) based on the 28 nm CMOS technology to efficiently tolerate TNU and reduce the power dissipation and latency of the latch. The latch design proposed in this article adopts stacked transistors to reduce sensitive nodes and area overhead. The TNU-SR latch uses clock gating and high-speed transfer path technology, resulting in low power dissipation and low delay. For simulation results, compared with existing latches, it can be known that the TNU-SR latch performs well in terms of delay, power consumption, and area, so it is a good choice for radiation-hardened design for space applications. In addition, compared with the latest TNU self-recovery latch (HLTNURL), the TNU-SR latch proposed in this paper reduces the Power-Area-Delay Product (PADP) metric by 111.13%.

DOI： 10.1109/TDMR.2025.3561519

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A Low-Cost QuadrupleNode-Upset Tolerant Latch Design and Recovery Rate Optimization Algorithm 査読有り国際誌

Huang Z., Jiang X., Zhang Y., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 5 ) 13858 - 13870 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the continuous shrinking of nanoscale CMOS technology, the critical charge of circuit nodes has significantly decreased, rendering the nodes highly susceptible to soft errors. In this paper, a high-performance single-node-upset recovery memory cell (HSRM) is proposed. Based on four HSAMs, a latch namely QUAD-HSRM is introduced, which can completely tolerate quadruple-nodeupset (QNU). Additionally, a circuit matrix-based verification algorithm is proposed, which is not limited to C-element, and can automatically detect the multi-node-upset recovery rate and blocking rate of latches. Based on this algorithm, an optimization algorithm for automatically improving the recovery rate of latches was proposed, and using this algorithm, the QUAD-HSRM was optimized to obtain the QUAD-HSRM-PRO. Compared to the QUAD-HSRM, the QNU recovery rate of the QUAD-HSRM-PRO has increased from 54.94% to 95.76%. Compared to other QNU hardened latches (LC-QNUTL, QRHIL, LDAVPM, MURLAV), the QUAD-HSRM-PRO shows an average power reduction of 45.02%, an average PDP reduction of 33.07%, an average setup time reduction of 8.00%, an average Q<inf>cirt</inf> increase of 80.56%.

DOI： 10.1109/TAES.2025.3581546

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A Response-Nonlinearized DEMUX-TDC PUF for Resistance Against Modeling Attacks and Secure Authentication Protocols 査読有り国際誌

Ni T., Wu H., Nie M., Yan A. (合肥工業大学), Wang S., Wen X., Bian J.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 10 ) 2606 - 2619 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As a critical hardware security primitive for the authentication within the Internet of Things (IoT), the physical unclonable function (PUF) represents an innovative security design paradigm for integrated circuits. However, the linear challenge-response mapping of the arbiter PUF (APUF) and variants render these structures more susceptible to modeling attacks due to their delayed linear structure. In this article, we propose a nonlinearized demultiplexer time-to-digital converter (DEMUX-TDC) PUF. This PUF uses a quantized delay difference technique to alter the traditional response generation mechanism, demonstrating robust resistance against modeling attacks. First, the proposed PUF employs a segmented APUF variant structure configured in both front and back segmented modes to generate a source of delay difference entropy. Additionally, the scheme incorporates a multilayer differential tapped TDC circuit to quantize the delay differences into digital codes, followed by a linear feedback shift register (LFSR) to obfuscate the final output response. We further propose a highly secure mutual authentication protocol based on reconfigurable PUF, by leveraging the characteristics of front and back segments of the PUF’s challenge. Evaluation of the proposed scheme on the implementation of Xilinx Virtex-7 and Spartan-6 field-programmable gate array (FPGA) demonstrates that the uniqueness and uniformity can reach ideal value, in the condition of prediction accuracy across six modeling attacks remaining around 50%.

DOI： 10.1109/TVLSI.2025.3575056

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BF PUF: A Modeling Attack-Resistant Strong PUF Based on Bent Functions 査読有り国際誌

Huang Z. (合肥工業大学), Zeng F., Chi Y., Lin Y., Lu Y., Liang H., Bian J., Ouyang Y., Ni T., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 8 ) 2299 - 2311 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Strong physical unclonable functions (PUFs) are promising circuits for lightweight Internet of Things (IoT) authentication and security. However, existing strong PUFs exhibit very low cryptographic nonlinearity (NL), making them vulnerable to machine learning (ML) modeling and cryptanalytic attack. To address this issue, we propose the Bent function PUF (BF PUF) based on Maiorana-McFarland (M-M) constructed Bent functions, which obfuscates the responses of the strong PUF to enhance resistance against modeling attacks. The core idea is to employ the M-M construction method for Bent functions to ensure maximum cryptographic NL to resist modeling attacks. A Feistel network is configured using weak PUF responses as keys to achieve device-specific and unpredictable mappings of input challenges while meeting the requirements of the M-M Bent function construction. A Python-based model of the BF PUF was developed, and simulation results indicate that the cryptographic NL of the proposed BF PUF outperforms k-XOR arbiter PUFs (APUFs) (k =2 , 4, 6). The proposed BF PUF was also implemented and evaluated on the FPGA hardware platform. The experimental results show that under modeling attacks using four ML algorithms—logistic regression (LR), artificial neural networks (ANNs), deep neural networks (DNNs), and covariance matrix adaptation evolution strategies (CMA-ES)—the best prediction accuracy under these four modeling attack algorithms is 52.60%. The reliability under temperature fluctuations ranging from - 10°C to 80°C is between 84.20% and 99.78%.

DOI： 10.1109/TVLSI.2025.3569587

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Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications 査読有り国際誌

Yan A. (合肥工業大学), Zhou C., Ni T., Zhang J., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 3 ) 6202 - 6216 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the aggressive shrinking of transistor feature sizes, nanoscale complementary metal oxide semiconductor (CMOS) circuits are becoming more vulnerable to multinode upsets, e.g., triple-node upsets as well as quadruple-node upsets (QNUs), caused by the effects of harsh radiation. This article first presents a QNU completely tolerant latch based on the so-called triple-path dual-interlocked cell (TPDICE) and the soft-error-interception module, namely quadruple-node-upset hardened latch (QNUHL). We further propose an advanced latch, namely quadruple-node-upset recovery hardened latch (QNURHL), which mainly employs 24 interlocked C-elements, to provide complete QNU recovery. Simulations based on the HSPICE tool demonstrate the complete QNU tolerance as well as the reasonable overhead for the QNUHL latch and also show that the QNURHL latch is recoverable from any possible QNU and can roughly save silicon area by 11% and power dissipation by 16%, compared with the QNU hardened latch of the same type. Moreover, an algorithm-based method for the verification of error tolerance and recovery of latches is proposed. The proposed method can simplify the verifications to demonstrate the capability of node-upset tolerance and/or recovery for latches.

DOI： 10.1109/TAES.2024.3525448

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Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement 査読有り国際誌

Yan A., Hu C., Li J., Bai N., Huang Z., Ni T., Patrick G., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 6 ) 1765 - 1773 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the continuous advancement of CMOS technologies, soft errors, such as single-node upset (SNU) and double-node upset (DNU), caused by radiation in nanoscale integrated circuits, are becoming increasingly prominent. Meanwhile, transistor aging mitigation is indispensable for long-term robustness enhancement. First, to reduce the impact of radiation on circuits, we propose a novel DNU-recovery latch with low cost, namely, DURLC, only consisting of four dual-input C-elements (CEs) and four clock-gated input-split inverters for the storage of values. Second, we propose a DNU-recovery latch with moderate cost, namely, DURMC, based on seven CEs and four inverters, for convenience to optimize the latch to alleviate aging. The proposed DNU-recovery latch with mitigated aging is called DURMA. The latch employs a high-speed path to reduce delay without sacrificing performance when mitigating aging issues. Finally, we propose an algorithm-based verification method to validate the DNU recovery of the proposed latches. The simulation results show that, compared with the state-of-the-art robust latches, the proposed latches have the advantages of DNU recovery with moderate and even low cost, and meanwhile, aging is effectively mitigated for the DURMA latch.

DOI： 10.1109/TVLSI.2025.3554117

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Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS 査読有り国際誌

Yan A. (合肥工業大学), Xu Y., Zhang Y., Bai N., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 7 ) 2079 - 2083 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Spintronic devices, such as magnetic tunnel junctions (MTJs), are promising for space applications due to their radiation hardness and nonvolatility. However, as semiconductor technology advances, CMOS peripheral circuits are becoming vulnerable to double node upset (DNU) as well as triple node upset (TNU). This brief proposes two nonvolatile and robust latch designs primarily composed of MTJs and C-elements (CEs). Both designs offer nonvolatility and self-recovery from multiple-node upsets. Simulation results demonstrate that the proposed latches provide nonvolatility and complete protection against multiple-node upsets with balanced overhead.

DOI： 10.1109/TVLSI.2025.3562769

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Efficient Modulated State Space Model for Mixed-Type Wafer Defect Pattern Recognition 査読有り国際誌

Nie M., Zhu S., Yan A., Zhuo C., Wen X., Ni T.

Proceedings Design Automation and Test in Europe Date 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Accurate and efficient wafer defect detection is crucial in semiconductor manufacturing to maintain product quality and optimize yield. Traditional methods struggle with the complexity and diversity of modern wafer defect patterns. While deep learning approaches are effective, they are often resource-intensive, posing challenges for real-time deployment in industrial settings. To solve these problems, we propose an Efficient Modulated State Space Model (EM-SSM) for mixed-type wafer defect recognition, optimized with knowledge distillation to balance accuracy and efficiency. Our framework captures size-dependent relationships and improves defect-specific feature representation to recognize complex defects precisely. Specifically, we introduce an efficient directional modulation mechanism to refine spatial recognition of defect patterns. To further improve inference efficiency, we propose a deep-to-shallow distillation method that transfers knowledge from deeper networks to lighter networks, reducing inference time without compromising classification accuracy. Experimental results on the MixedWM38 wafer dataset with 38 defect types show that our model achieves 99.0% accuracy, outperforming traditional methods in both accuracy and efficiency. Our model offers a scalable solution for modern semiconductor defect detection.

DOI： 10.23919/DATE64628.2025.10992855

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Graph-Based Multitask Transfer Learning for Fault Detection and Diagnosis of Few-Shot Analog Circuits 査読有り国際誌

Gao Z., Yan A. (合肥工業大学), Huang Z., Cui J., Roh B.H., Liu G., Girard P., Wen X.

IEEE Internet of Things Journal 12 ( 12 ) 21264 - 21279 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Building an interpretable fault detection and diagnostic model based on few-shot circuit samples and prior information about circuit structures is of significant importance. To fill these gaps, we propose a graph-based multitask transfer learning (TL) method for fault detection and diagnosis of circuits under few-shot conditions. First, in order to model the interconnections of nodes in a circuit, the sample data is organized into a graph structure, and a semi-supervised graph-based structural feature fusion method is proposed. The proposed method can accept graph-structured data and process the data using feature fusion methods. Second, to improve the model performance under few-shot conditions, two TL mechanisms are proposed for the topological structure characteristics of analog circuits as well as circuit signal characteristics. Finally, through a parameter-shared strategy, we propose a task transfer-based fault diagnosis approach. Experimental results on three different circuits show that the proposed method has the best diagnostic accuracy compared to typical detection and diagnosis schemes.

DOI： 10.1109/JIOT.2025.3547957

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HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications 査読有り国際誌

Guo X., Zhang J., Meng X., Li Z., Wen X., Girard P., Liang B., Yan A. (合肥工業大学)

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 44 ( 6 ) 2367 - 2377 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the rapid advancement of semiconductor technologies, latches become increasingly sensitive to soft errors, especially triple node upsets (TNUs), in harsh radiation environments. In this article, we first propose a high-performance and area-efficient latch, namely, HALTRAV, featuring complete TNU-recovery. The storage portion of HALTRAV consists of 28 interlocked source-drain cross-coupled inverters (SCIs) for complete TNU-recovery with area efficiency and low delay. To mitigate the issue that node-upset-recovery verifications for existing latches highly relies on electronic design automation tools, we further propose an algorithm-based verification method that can automatically verify the node-upset-recovery of latches, which greatly simplifies the reliability-verification flow. Simulation results demonstrate the TNU-recovery of HALTRAV and also show that HALTRAV achieves 40.38%, 8.17%, and 31.89% reduction in delay, area, and delay-power–area product (DPAP) on average, respectively; however; it is at the cost of power as compared to typical latches that are TNU-recoverable. Comparison results also demonstrate the moderate sensitivity of HALTRAV to the impacts of the process, voltage, and temperature (PVT) variations.

DOI： 10.1109/TCAD.2024.3511335

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Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design 査読有り国際誌

Ma R., Holst S., Xu H., Wen X., Wang S., Li J., Yan A. (合肥工業大学)

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 2 ) 449 - 461 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Soft errors have been a severe threat to the reliability of modern integrated circuits (ICs), making hardened latch designs indispensable for masking soft errors with redundancy. However, the added redundancy also masks production defects as soft errors; this makes it hard to detect defects in hardened latches, thus significantly reducing their reliability. Our previous work proposed the scan-test-aware hardened latch (STAHL) design, the first for addressing the issue of low defect detectability of hardened latch designs. However, STAHL still suffers from two problems: 1) it is not self-resilient to soft errors and 2) a STAHL-based scan design requires one additional control signal. This article proposes a high defect detectable and single-event-upset (SEU)-resilient robust (HIDER) latch to address the issues of the low defect detectability of existing hardened latches and the STAHLs lack of SEU-resilient capability. Two scan designs [HIDER-based scan-cell-S (HIDER-SC-S) and HIDER-based scan-cell-F (HIDER-SC-F)], as well as two corresponding test procedures, are proposed to fully test HIDER latch with only one control signal. Simulation results show that the HIDER latch achieves the highest defect coverage (DC) in both single latch cell detection and scan tests among all existing hardened latch designs. In addition, the HIDER latch has much lower power and a smaller delay than STAHL.

DOI： 10.1109/TVLSI.2024.3467089

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Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Based on Cross-Interlocking 査読有り国際誌

Huang Z. (合肥工業大学), Ai L., Jiang X., Wang X., Lu Y., Pan J., Song T., Wen X., Yan A.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 44 ( 4 ) 1595 - 1608 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

As the CMOS technology continues to shrink, latches are becoming increasingly susceptible to multiple-node-upset caused by charge sharing in radiation environments. In this article, a low-cost quadruple-node-upset (QNU) self-recoverable latch based on cross-interlocking (Quad-CIRC) is proposed. By utilizing four cross-interlocking self-recoverable cells (CIRCs) for interlocking, complete QNU self-recovery is achieved with reduced sensitive nodes. Meanwhile, the majority of currently available QNU self-recoverable latches are primarily composed of C-elements-based redundancy, resulting in a significant increase in area overhead. However, Quad-CIRC effectively reduces area overhead while ensuring hardened capability through cross-interlocking of CIRCs. HSPICE-based simulations in 22 nm CMOS technology demonstrate that Quad-CIRC achieves a reduction of 69.08% on average of power consumption, an increase of 16.83% on average of delay, a reduction of 63.51% on average of power-delay-product (PDP), a reduction of 51.01% on average of area, a reduction of 83.44% on average of area-PDP (APDP), and an increase of 60.49% on average of critical charge, compared to five other QNU self-recoverable latches (QRHIL, MURLAV, LDAVPM, QR-R11-C2 , and low-delay QNU self-recoverable).

DOI： 10.1109/TCAD.2024.3471913

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TNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications 査読有り国際誌

Yan A., Pei Z., Guo X., Song J., Jiang C., Liang H., Wen X., Girard P.

Proceedings IEEE International Symposium on Circuits and Systems 2025年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As semiconductor technology advances, radiative-particle-induced soft errors and power consumption are becoming major concerns for digital circuits in aerospace applications. Radiation hardening by design and magnetic tunnel junctions (MTJs) are widely employed to address these concerns. In this paper, a novel latch, called TNURML, that can completely recover from triple-node upsets (TNUs), is proposed. The embedded MTJs provide non-volatility and are compatible with traditional CMOS processes. The TNURML employs a TNU-recovery module as well as a pair of MTJs for backup and recovery operations. Extensive simulations demonstrate the excellent TNU-recovery capability and non-volatility of the TNURML latch at the cost of slightly increased area overhead. The proposed TNURML latch reduces 43.63% of delay and 48.23% of power on average when compared to the state-of-the-art latches.

DOI： 10.1109/ISCAS56072.2025.11043354

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QNUCPN: A Low-Power Single-Event Quadruple-Node-Upset Recovery Latch 査読有り国際誌

Huang Z., Qiu L., Yang S., Wang X., Lu Y., Pan J., Cheng F., Wen X., Yan A.

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 45 ( 2 ) 855 - 866 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Integrated circuits are increasingly sensitive to radiation-induced multi-node upset in advanced CMOS technology. This paper proposes a novel low-power quadruple-node-upset recovery latch (QNU-CPN), which is based on the feedback interconnection of twenty-two input-split C-elements with P-input and N-input (CPNs) to achieve high reliability. Post-layout simulation results for 45nm CMOS by HSPICE technology show that the proposed QNU-CPN latch exhibits a reduction in power consumption by an average of 56.45%, a reduction in power-delay product (PDP) by an average of 56.92%, a reduction in area-power-delay product (APDP) by an average of 58.59%, and a reduction in setup time by an average of 11.11%, in comparison to four other existing quadruple-node upset recovery latch (LDAVPM, QRHIL, QRHIL-LC, MURLAV). Furthermore, this paper proposes the recovery rate calculation algorithm method that can calculate the recovery rate based on the configuration of multiple fault-tolerant components.

DOI： 10.1109/TCAD.2025.3590658

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105011074318&origin=inward

A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments 査読有り国際誌

Bai N., Xia Y., Xu Y., Wang Y., Wang S., Wen X.

IEEE Transactions on Very Large Scale Integration VLSI Systems 33 ( 9 ) 2580 - 2591 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the advancement of semiconductor technology, circuits have become increasingly susceptible to errors induced by radiation. Traditional approaches to enhancing the resilience of circuits against single-node upsets (SNUs) are insufficient to meet the robustness standards of modern designs. This article proposes a high-performance, low-power latch, named high-performance low-power double-node upset resilient latch (HLDRL), which is designed to exhibit exceptional resilience against double-node upsets (DNUs). Its design has six intricately interconnected C-elements (CEs) and two three-input CEs, for error interception, ensuring robust performance even in the case of DNUs. The Technology Computer Aided Design (TCAD) tool is used to validate the effectiveness of the HLDRL. Besides, comprehensive simulations are conducted utilizing the advanced SMIC 55-nm process technology. These simulation results show that our proposed HLDRL latch can autonomously recover from any DNU and thereby ensure the integrity of the system. Moreover, compared with existing DNU-resilient latches, the proposed HLDRL latch exhibits substantial improvements in terms of multiple metrics. On average, the proposed latch achieves an impressive 29.39% dynamic power saving, a remarkable 40.04% increase in speed, a notable 4.81% reduction in area, and a substantial 53.96% decrease in the power-delay–area product (PDAP). In the post-layout simulation, the proposed latch achieves a 30.39% dynamic power saving, a 36.47% increase in speed, and an impressive 52.38% decrease in PDAP. Furthermore, the proposed latch demonstrates enhanced resilience against variations in process, supply voltage, and temperature (PVT).

DOI： 10.1109/TVLSI.2025.3585169

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105012589138&origin=inward

Non-Volatile, Double and Triple Node Upsets Tolerant Latch Designs Based on FeFET and CMOS 査読有り国際誌

Yan A., Kang B., Jiang W., Ni T., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 61 ( 6 ) 16981 - 16992 2025年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Non-volatile memories (NVMs) are widely used in energy-harvesting Internet of Things (IoTs) systems, and ferroelectric field effect transistor (FeFET) devices present opportunities for NVM designs due to such important features as low power consumption, fast access speed and compatibility with the CMOS technology. However, rising soft error rates caused by radiation pose a severe reliability challenge, and state-of-the-art radiation hardening by design (RHBD) methods are urgently needed. This paper presents a non-volatile double-node-upset (DNU) tolerant latch (NVDTL) and its enhanced version, i.e., a non-volatile triple-node-upset (TNU) tolerant latch (NVTTL), which do not require auxiliary control signals to provide the non-volatility feature. The NVDTL utilizes two parallel single-node-upset (SNU) recovery units. Each unit integrates multiple 2-input C-elements and input-split inverters with embedded FeFETs to form interlocked feedback loops. Moreover, NVTTL enhances its robustness reliability through a two-stage error-blocking mechanism in the output module to provide TNU tolerance. Simulation results based on Cadence Virtuoso have validated the proposed latches' fault-tolerance and non-volatility and also show that the comprehensive delay-power-area product is reduced by approximately 77.21% for NVDTL and 61.67% for NVTTL, and the power-delay product is reduced by 23.45% and 11.15%, respectively, compared to the existing latches with the same level of radiation hardness.

DOI： 10.1109/TAES.2025.3599136

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105013263658&origin=inward

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