研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 41 - 60 件目／全件表示 >>

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications 査読有り国際誌

Yan A., Xiang J., Huang Z., Ni T., Cui J., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

For high-speed operations, low power consumption and small silicon area, transistors are being scaled aggressively. Meanwhile, circuit reliability is facing greater challenges in advanced technologies. In this paper, a highly reliable and low-power SRAM with double-node-upset (DNU) recovery, namely HRLP16T, is proposed for safety-critical fields. HRLP16T can recover from single-node-upset (SNU) at all the sensitive nodes, and it has eight node pairs recoverable from DNUs. Simulation results demonstrate its advantages in terms of delay and power consumption over typical existing SRAM cell designs.

DOI： 10.1109/ITC-Asia58802.2023.10301170

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BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell 査読有り国際誌

Holst S., Ma R., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2023-May 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Ensuring the correct operation of modern VLSI circuits within safety-critical systems is essential since modern technology nodes are more susceptible to Early-Life Failures (ELFs) and radiation-induced Soft-Errors (SEs). Tackling both of these challenges leads to contradicting design requirements: Effective in-field ELF detection requires online-monitoring or periodic built-in self-Testing with excellent cell-internal defect coverage. SE-hardened latch designs, however, are less testable because they are designed to mask cell-internal failures. We propose BiSTAHL, a new SE-hardened scan-cell design that is fully built-in self-Testable for both production defects and ELFs.

DOI： 10.1109/ETS56758.2023.10174154

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Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications 査読有り国際誌

Yan A., Li X., Gao Z., Huang Z., Ni T., Wen X.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of CMOS technologies, integrated circuits are becoming more prone to soft errors, e.g., triple-node upsets (TNUs). In this paper, to effectively tolerate TNUs, an input-split C-element-based DICEs (IC-DICEs) based TNU-recovery latch is proposed. The latch employs three interlocked IC-DICEs to allow recovering from any TNU. Simulations demonstrate the TNU recovery of the latch, and also demonstrate that the proposed latch can reduce delay by 87.21%, area by 27.04%, and delay-area-power product (DAPP) by 87.44% on average, compared to the alternative latches.

DOI： 10.1109/ATS59501.2023.10317977

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A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery 査読有り国際誌

Yan A., Li X., Ni T., Huang Z., Wen X.

Proceedings - 2023 10th International Conference on Dependable Systems and Their Applications, DSA 2023 474 - 476 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The aggressive shrinking of CMOS makes flip-flops (FFs) vulnerable to single-node upset (SNU) as well as double-node upset (DNU). SNU and DNU are typical soft errors. This paper presents a highly reliable and low delay FF providing complete DNU-recovery. Simulations show the complete DNU-recovery as well as low-delay for our proposed FF making the FF suitable for high-robustness and high-performance applications.

DOI： 10.1109/DSA59317.2023.00065

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A Low Overhead and Double-Node-Upset Self-Recoverable Latch 査読有り国際誌

Yan A., Xia F., Ni T., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of semiconductor technologies, integrated circuits, especially storage elements (e.g., latches) have become increasingly vulnerable to soft errors. In order to effectively tolerate double-node-upsets (DNUs) caused by radiation and reduce the power and area of latches, this paper proposes a DNU self-recoverable latch with low overhead in terms of power and area. The proposed latch mainly comprises seven 2-input C-elements and two inverters to achieve DNU self-recovery. Simulation results show that the proposed latch can recover from all possible DNUs and that it can reduce delay by 45.7%, power by 29.1%, area by 65.9%, and area-power-delay-product by 87.4%, on average, compared to typical existing DNU self-recoverable latches.

DOI： 10.1109/ITC-Asia58802.2023.10301166

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A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges 査読有り国際誌

Ni T., Li F., Peng Q., Wang S., Wen X.

Proceedings of the 2023 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Physically unclonable functions (PUFs) are an attractive and low-cost security primitive because it requires no storage and is easy to implement. PUFs arise from changes in the manufacturing process of the device and can generate secure and unique keys for secure storage, authentication, and data encryption. In addition, the keys generated by PUFs should be reliable, independent, and themselves resistant to attacks and reverse engineering. In this paper, a new PUF framework is proposed, which segments the whole structure, introduces the non-linearity of the structure, uses the previous challenges and the later challenges are XOR with the previous response, which introduces the obfuscation of the challenges to improve the resistance to machine learning attack. The framework can be used for any kind of strong PUF implementation. In this paper, the whole framework is implemented with RO ring PUF, the PUF shows excellent performance, and the RO ring is modified with four input multiplexer and only a pair of counters and a comparator for multiple rings, which significantly reduces the hardware resource consumption. The PUF has passed machine learning attacks with significant resistance to Logistic Regression(LR) and Covariance Matrix Adaptation Evolutionary Strategies(CMA-ES).

DOI： 10.1109/AsianHOST59942.2023.10409383

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A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design 査読有り国際誌

Yan A., Wei S., Chen Y., Fan Z., Huang Z., Cui J., Girard P., Wen X.

Micromachines 13 ( 11 ) 2022年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.

DOI： 10.3390/mi13111802

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A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications 査読有り国際誌

Yan A., Qian K., Song T., Huang Z., Ni T., Chen Y., Wen X.

Integration 86 22 - 29 2022年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a novel radiation hardened latch (namely DCTELC) that can completely tolerate single-node upsets and double-node upsets (DNUs) for high-performance applications. The latch mainly consists of a clock-gating based dual-interlocked-cell (DICE), a 2-input C-element, and a clock-gating based 2-input C-element. The latch introduces isolated nodes to tolerate DNUs and the isolated nodes have no time to float for high-performance applications. Simulation results demonstrate the complete DNU tolerance for the latch and an 86% power-area-delay product (PADP) saving on average compared with state-of-the-art DNU-tolerant latches. Moreover, compared with the existing latches of the same type, the power dissipation, silicon area, transmission delay, and PADP of the proposed latch are the smallest.

DOI： 10.1016/j.vlsi.2022.04.008

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A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology 査読有り国際誌

Yan A., Zhou Z., Wei S., Cui J., Zhou Y., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 255 - 260 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input C-elements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively.

DOI： 10.1145/3526241.3530321

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Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications 査読有り国際誌

Yan A., Chen Y., Song S., Zhai Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 333 - 338 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel sextuple cross-coupled dual-interlocked-storage-cell (DICE) based double-node-upset (DNU) recoverable and low-delay flip-flop (FF), namely SCDRL-FF, for aerospace applications. The SCDRL-FF mainly consists of sextuple cross-coupled DICEs controlled by clock-gating. The use of clock-gating based DICEs significantly reduces the CLK-Q transmission delay of the SCDRL-FF. Through the redundant and interlocked clock-gating based DICEs, the SCDRL-FF can provide complete DNU recoverability. Simulation results demonstrate the DNU recoverability of the SCDRL-FF and a 65% delay reduction on average compared with the state-of-the-art hardened FFs. The low delay overhead makes the proposed SCDRL-FF effectively applicable to high-performance applications and the DNU recoverability makes the proposed SCDRL-FF also suitable for aerospace applications.

DOI： 10.1145/3526241.3530355

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Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications 査読有り国際誌

Yan A., He Z., Xiang J., Cui J., Zhou Y., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 261 - 266 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Aggressive scaling of CMOS technologies requires to pay attention to the reliability issues of circuits. This paper presents two highly reliable RHBD 10T and 12T SRAM cells, which can protect against single-node upsets (SNUs) and double-node upsets (DNUs). The 10T cell mainly consists of two cross-coupled input-split inverters and the cell can robustly keep stored values through a feedback mechanism among its internal nodes. It also has a low cost in terms of area and power consumption, since it uses only a few transistors. Based on the 10T cell, a 12T cell is proposed that uses four parallel access transistors. The 12T cell has a reduced read/write access time with the same soft error tolerance when compared to the 10T cell. Simulation results demonstrate that the proposed cells can recover from SNUs and a part of DNUs. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed 10T cell can save 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

DOI： 10.1145/3526241.3530312

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A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center 査読有り国際誌

Saxena D., Gupta I., Kumar J., Singh A.K., Wen X.

IEEE Systems Journal 16 ( 2 ) 3163 - 3174 2022年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

To facilitate cost-effective and elastic computing benefits to the cloud users, the energy-efficient and secure allocation of virtual machines (VMs) plays a significant role at the data center. The inefficient VM placement (VMP) and sharing of common physical machines among multiple users leads to resource wastage, excessive power consumption, increased intercommunication cost, and security breaches. To address the aforementioned challenges, a novel secure and multiobjective VMP (SM-VMP) framework is proposed with an efficient VM migration. The proposed framework ensures an energy-efficient distribution of physical resources among VMs, which emphasizes secure and timely execution of user application by reducing intercommunication delay. The VMP is carried out by applying the proposed Whale Optimization Genetic Algorithm (WOGA), inspired by whale evolutionary optimization and nondominated sorting based genetic algorithms. The performance evaluation for static and dynamic VMP and comparison with recent state of the arts observed a notable reduction in shared servers, intercommunication cost, power consumption, and execution time up to 28.81%, 25.7%, 35.9%, and 82.21%, respectively with increased resource utilization up to 30.21%.

DOI： 10.1109/JSYST.2021.3092521

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Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications 査読有り国際誌

Yan A., Xiang J., Cao A., He Z., Cui J., Ni T., Huang Z., Wen X., Girard P.

IEEE Transactions on Device and Materials Reliability 22 ( 2 ) 282 - 295 2022年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead.

DOI： 10.1109/TDMR.2022.3175324

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Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications 査読有り国際誌

Yan A., Fan Z., Ding L., Cui J., Huang Z., Wang Q., Zheng H., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 58 ( 1 ) 517 - 529 2022年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this article also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2, 32.8, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called high-impedance state-insensitive, TNU-tolerant, and SET-filterable latch can reduce delay, power, and area by 78.9, 15.8, and 28.6%, respectively, compared with the state-of-the-art TNU hardened latch.

DOI： 10.1109/TAES.2021.3103586

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Broadcast-TDMA: A Cost-Effective Fault Tolerance Method for TSV Lifetime Reliability Enhancement 査読有り国際誌

Ni T., Bian J., Yang Z., Nie M., Yao L., Huang Z., Yan A., Wen X.

IEEE Design and Test 39 ( 5 ) 34 - 42 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Electromigration and time-dependent dielectric breakdown induced through-silicon-via (TSV) aging, along with TSV thermal issues including thermo-mechanical stress and thermal cycling, may result in failure and affect the lifetime reliability of TSV. This paper proposes a cost-effective fault tolerance method for TSV lifetime reliability enhancement. In a honeycomb TSV group formed by six TSVs without the utilization of redundant TSVs, any faulty TSV can be bypassed and broadcasted to any other TSVs in the same group. The cost-effectiveness of the proposed fault tolerance method has been evaluated based on the IWLS’05 3D benchmark circuits using 45nm open cell library. Experimental results show that the proposed method has the highest lifetime reliability compared with state-of-art router-based, ring-based, and chain-TDMA based solutions for lifetime reliability enhancement, and the lifetime reliability of the proposed scheme can still remain more than 90% even at 10 years. Furthermore, compared with the methods mentioned above, the proposed method can achieve 34.05%~58.56%, 29.46%~55.55%, 4.75%~39.84% reductions in hardware overhead, respectively. All these promising attributes can facilitate this proposed architecture’s adoption in 3D IC designs.

DOI： 10.1109/MDAT.2022.3189827

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A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications 査読有り国際誌

Yan A., Qian K., Cui J., Cui N., Huang Z., Wen X., Girard P.

Proceedings of the IEEE VLSI Test Symposium 2022-April 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In space, the impact of radiative particles, such as neutrons and heavy ions, can change the node states of a flip-flop, thus resulting in loss of data. In this paper, a Highly reliable and Low power Radiation-hardened-by-design (RHBD) Flip-Flop cell, namely HLRFF, completely hardened against double-node-upsets (DNUs), is proposed for aerospace applications. The HLRFF is a master-slave structure. The master latch is mainly constructed from two 2-input C-elements (CEs) and one 2-input clock-gating based CE, while the slave latch has an additional keeper at the output stage. The verification results demonstrate that the proposed HLRFF is completely DNU-tolerant. Furthermore, compared to the state-of-the-art radiation-hardened FF cells, the proposed HLRFF can reduce power consumption by approximately 69%. However, only the proposed HLRFF is not only completely DNU-tolerant but also insensitive to high-impedance-state.

DOI： 10.1109/VTS52500.2021.9794197

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Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments 査読有り国際誌

Yan A., Xu Z., Feng X., Cui J., Chen Z., Ni T., Huang Z., Girard P., Wen X.

IEEE Transactions on Emerging Topics in Computing 10 ( 1 ) 404 - 413 2022年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.

DOI： 10.1109/TETC.2020.3025584

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SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments 査読有り国際誌

Yan A., Li Z., Huang S., Zhai Z., Cheng X., Cui J., Ni T., Wen X., Girard P.

Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 1257 - 1262 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the CMOS technology is continuously scaling down, nano-scale integrated circuits are becoming susceptible to harsh-radiation induced soft errors, such as double-node upsets (DNUs) and triple-node upsets (TNUs). This paper presents a shuttle C-elements based low-cost and robust latch (namely SCLCRL) that can recover from any TNU in harsh radiation environments. The latch comprises seven primary storage nodes and seven secondary storage nodes. Each pair of primary nodes feeds a secondary node through one C-element (CE) and each pair of secondary nodes feeds a primary node through another CE, forming redundant feedback loops to robustly retain values. Simulation results validate all key TNUs' recoverability features of the proposed latch. Simulation results also demonstrate that the proposed SCLCRL latch can approximately save 29% silicon area and 47% D-Q delay on average at the cost of moderate power, compared with the state-of-the-art TNU-recoverable reference latches of the same-type.

DOI： 10.23919/DATE54114.2022.9774665

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Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS 査読有り国際誌

Yan A., Song S., Zhang J., Cui J., Huang Z., Ni T., Wen X., Girard P.

Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 73 - 78 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the aggressive reduction of CMOS transistor feature sizes, the soft error rate of nano-scale integrated circuits increases exponentially. In this paper, we propose a novel cost-optimized and robust latch, namely CRLHQ, hardened against quadruple-node-upsets (QNUs) for nanoscale CMOS technologies. The latch mainly comprises a 5×5 matrix based on interlocked source-drain cross-coupled inverters to robustly store logic values. Owing to the redundant constructed feedback loops, the latch can recover from all possible QNUs. Simulation results demonstrate all key QNUs' recovery of the proposed CRLHQ latch. Simulation results also show that the proposed latch can approximately reduce the D-Q delay by 44.3%, the silicon area by 7.3% and the delay-area-power product (DAPP) by 14.2%, compared with the state-of-the-art same-type reference latches that can recover from any QNU.

DOI： 10.1109/ITCAsia55616.2022.00023

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A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters 査読有り国際誌

Yan A., Song S., Chen Y., Cui J., Huang Z., Wen X.

Proceedings of the IEEE Conference on Nanotechnology 2022-July 215 - 218 2022年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel low-cost and robust latch, namely LRLPT, protected against triple-node upsets (TNUs) in nano-scale CMOS. The storage part of the latch comprises interlocked source-drain cross-coupled inverters forming redundant feedback loops to robustly store values. Simulation results demonstrate all key TNUs' recovery of the proposed latch. Simulation results also demonstrate that the proposed latch can save 69.67% delay, 37.51% silicon area and 71.77% delay-area-power product (DAPP) compared to the state-of-the-art TNU-recovery reference latch of the same-type.

DOI： 10.1109/NANO54668.2022.9928674

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85142937099&origin=inward

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