研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 201 - 220 件目／全件表示 >>

Power-Aware Testing For Low-Power VLSI Circuits 招待有り査読有り国際誌

X. Wen

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings 585 - 588 Paper S37-1 2016年10月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Hangzhou 2016年10月25日 - 2016年10月28日

© 2016 IEEE. Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely heat, false failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research topics in this field will also be discussed.

DOI： 10.1109/ICSICT.2016.7998986

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85028640934&origin=inward

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016-September 679 - 684 2016年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA Pittsburgh 2016年07月11日 - 2016年07月13日

© 2016 IEEE.Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys), called κ-TX. κ-TX corrects up to κ-bit flip errors and significantly enhances the tolerance of the TCAM against soft errors, where κ is the maximum number of bit flips in a word of a TCAM. κ-TX consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and an ECC-SRAM. First, κ-TX randomly selects a search key. After that, κ-TX detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and κ-TX refreshes the TCAM words by using a backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of κ-TX outperforms other schemes significantly. Moreover, the hardware overhead of k-TX is small due to the use of only a single TCAM. κ-TX can be easily implemented and is useful for fault-tolerant packet classifiers.

DOI： 10.1109/ISVLSI.2016.77

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84988953667&origin=inward

SAT-Based Post-Processing for Regional Capture Power Reduction in at-speed scan test generation 査読有り国際誌

S. Eggersgluss, K. Miyase, X. Wen

IEEE European Test Symposium 2016-July 2016年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Netherlands Amsterdam 2016年05月23日 - 2016年05月27日

© 2016 IEEE.With more and more sophisticated low-power design techniques being applied to modern LSI chips for aggressive functional power reduction, the risk of fault-free chips falsely failing production test grows due to excessively high test power compared with functional power. Existing low-power ATPG methods, however, suffer from severe test data inflation and often use unfocused global test power reduction. This paper proposes a novel optimization-SAT-based at-speed scan test generation method that is explicitly targeted at eliminating high-capture-power test vectors in a pre-generated compact test set. This method employs layout information in reducing capture switching activity in a focused regional manner. Experiments demonstrate that the proposed method can effectively eliminate a large number of high-capture-power test vectors with neither test data inflation nor fault coverage loss.

DOI： 10.1109/ETS.2016.7519327

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84991435135&origin=inward

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill 査読有り国際誌

D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35 ( 3 ) 499 - 512 2016年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE.At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.

DOI： 10.1109/TCAD.2015.2474365

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84963778122&origin=inward

Test Pattern Modification for Average IR-Drop Reduction 査読有り国際誌

W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen

IEEE Transactions on VLSI Systems 24 ( 1 ) 38 - 49 2016年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern. We propose a fast average IR drop estimation, which is very close to the time-averaged IR drop of time-consuming transient simulation (R2 =0.99). We calculate the contribution of every node to these nodes inside IR-drop hotspot so that we can effectively modify only a few don't care bits in the test patterns to reduce IR drop. The experimental results show that our technique successively reduces time-averaged IR drop by 10% with almost no fault coverage loss and no test pattern inflation.

DOI： 10.1109/TVLSI.2015.2391291

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84927779731&origin=inward

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch 査読有り国際誌

K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian

IEEE Asian Test Symposium 103 - 108 2015年11月

Power Supply Noise and Its Reduction in At-Speed Scan Testing 招待有り査読有り国際誌

X. Wen

IEEE International Conference on ASIC Paper B5-3 2015年11月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Chengdu 2015年11月03日 - 2015年11月06日

Scan testing tends to cause excessive switching activity in an LSI circuit, incurring significant power supply noise with severe impact on its timing. This may lead to over-test or under-test, resulting in test yield loss or low test quality. This paper describes the issue of power supply noise in at-speed scan testing, introduces typical techniques for its reduction, and discusses some important future research topics.

DOI： 10.1109/ASICON.2015.7516980

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84982256034&origin=inward

A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

24th International Workshop on Logic and Synthesis 2015年06月

Identification of High Power Consuming Areas with Gate Type and Logic Level Information 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE European Test Symposium Paper 9.1 2015年05月

A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE European Test Symposium Poster 2.4 2015年05月

GPU-Accelerated Small Delay Fault Simulation 査読有り国際誌

E. Schneider, S. Holst, M.-A. Kochte, X. Wen, H.-J. Wunderlich

Design and Test in Europe 1174 - 1179 2015年03月

Towards Memory-Aware VLSI Simulation Algorithms for Heterogeneous Architectures 査読有り国際誌

S. Holst, J. Miyazaki, X. Wen

International Symposium on Applied Engineering and Sciences 2014年12月

Soft-Error Tolerant TCAMs for High-Reliability Packet Classification 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase

IEEE Asia Pacific Conference on Circuits and Systems 471 - 474 2014年11月

Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り国際誌

E. Schneider, S. Holst, X. Wen, H. Wunderlich

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD 17 - 23 2014年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA San Jose 2014年11月02日 - 2014年11月06日

© 2014 IEEE.Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate timesimulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.

DOI： 10.1109/ICCAD.2014.7001324

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84936860899&origin=inward

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り国際誌

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEICE Transactions on Information and Systems E97 ( 10 ) 2706 - 2718 2014年10月

低キャプチャ電力スキャンテスト生成のためのX埋め込み手法

李富強, 温暁青, 宮瀬紘平, ホルストシュテファン, 梶原誠司

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 ( 一般社団法人電子情報通信学会 ) 114 ( 99 ) 15 - 20 2014年06月

記述言語：英語掲載種別：研究論文（研究会，シンポジウム資料等）

低キャプチャ電力のスキャンテストパターンを生成するため,セルの実効電圧降下(IR-Drop)との関わりの強いローカル信号値遷移量(LSA:Local Switching Activity)を抑えるX埋め込み手法を提案する.この手法では,レイアウトレベルの回路を単位区域に分割した上,各単位区域の遷移量を示すLSAによってテストキューブ中のXビットの優先順位を決めて,伝搬しやすい値を最適論理値として順次Xビットに割り当てる.実験結果によって,提案手法がLSAを効果的に低減できることが示された.

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/110009925706

Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits 査読有り国際誌

E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich

ACM Design Automation Conference Poster 2014年06月

Low-power testing for 2D/3D devices and systems 査読有り国際誌

Lin X., Wen X., Xiang D.

Design of 3D Integrated Circuits and Systems 235 - 277 2014年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2015 by Taylor & Francis Group, LLC. Power dissipation has become a primary concern in large-scale integration (LSI) design [1]. Over the years, LSI designers have been tirelessly developing hardware and software techniques for effectively reducing functional power [2]. Functional constraints are often exploited at various levels to remove wasteful operations so that functional power is reduced. For example, a circuit designed for cell phone applications contains many functional blocks that do not need to be activated simultaneously, e.g., a block for audio and a block for phone calls. Dynamically disabling unnecessary circuit blocks significantly reduces functional power.

DOI： 10.1201/9781315215709

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85054660389&origin=inward

ATPG Enhancement Technology 査読有り国際誌

N.A. Zakaria, M.Z Khalid, X. Wen

IEEE Workshop on RTL and High Level Testing Paper IV.5.S 2013年11月

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST 査読有り国際誌

A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE Asian Test Symposium 19 - 24 2013年11月

　前のページ - 次のページ　

<温 暁青>

論文 - 温 暁青

<温　暁青>

論文 - 温　暁青