研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 81 - 100 件目／全件表示 >>

SHRCO: Design of an SRAM with High Reliability and Cost Optimization for Safety-Critical Applications 査読有り国際誌

Chang Y., Liu G., Ullah I., Shan G., Wen X., Yan A.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel radiation-hardened high-reliability SRAM cell, namely SHRCO, with 12 transistors for robust value storage as well as 6 transistors for parallel access operations. Using separated and error-interceptive feedback paths, the proposed cell has a complete self-recoverability from single-node upset (SNUs) at all single nodes and an excellent self-recoverability from double-node upsets (DNUs) at a part of node pairs. In addition, the proposed cell has superior access operation speed due to the inclusion of extra parallel access transistors. Simulation results show that the proposed cell has the largest number of node pairs that can self-recover from DNUs. Moreover, compared to the existing radiation-hardened SRAM cells, the proposed cell saves 28% of read time and 3% of write time on average.

DOI： 10.1109/ITC-Asia62534.2024.10661340

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SRBML: A Single-Event-Upset Recoverable and BTI-Mitigated Latch Design for Long-Term Reliability Enhancement 査読有り国際誌

Xia F., Zhang J., Ali J., Zhang C., Wen X., Yan A.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Soft-errors and aging are considered as two primary factors affecting the long-term reliability of aerospace integrated circuits (ICs). As one of the key components in aerospace ICs, latches play a pivotal role to ensure desirable circuit functionality. This paper presents a single-event-upset recovery latch, namely SRBML, with bias-temperature-instability (BTI)-mitigation. By optimizing its internal structure, the latch can recover from single-event-upsets (SEUs) and reduce the stress time of transistors in feedback loops to simultaneously mitigate the impact of BTI on the latch. Simulation results demonstrate that the soft error rate increase due to BTI is reduced by roughly 34% for SRBML after BTI-mitigation. In addition, the delay of SRBML is not affected, and the area and power increase are limited compared to BTI-unmitigated latches.

DOI： 10.1109/ITC-Asia62534.2024.10661343

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PFO PUF: A Lightweight Parallel Feed Obfuscation PUF Resistant to Machine Learning Attacks 査読有り国際誌

Huang Z., Lin Y., Zeng F., Bian J., Yang Z., Liang H., Lu Y., Yao L., Wen X., Ni T.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Arbiter Physically Unclonable Functions (APUFs) are hardware security primitives that leverage manufacturing process variation to generate security keys. They can produce exponential challenge-response pairs (CRPs) with minimal hardware overhead. However, the symmetric nature of linear additive functions makes them vulnerable to modeling attacks rooted in machine learning. To address this issue, this paper introduces a novel design called Parallel Feed Obfuscation PUF (PFO PUF). In this approach, the intermediate decision signals from the lower APUF are used as a concealed challenge for the upper APUF, enhancing the overall nonlinearity of the dual-APUF. Additionally, obfuscation modules are employed to determine the weights of the intermediate decision signals from both the upper and lower APUFs, protecting the actual response. Experimental results demonstrate that the proposed PFO PUF effectively withstands four advanced machine learning attack algorithms, including Logistic Regression (LR), Support Vector Machine (SVM), Deep Feedforward Neural Network (DFNN), and Efficient CANDECOMP/PARAFAC Tensor Regression Network (ECPTRN). The prediction accuracy of these four algorithms is consistently below 66.30%. Compared with other enhanced structures based on APUF, PFO-PUF only uses 493 LUTs and has lower resource overhead.

DOI： 10.1109/ITC-Asia62534.2024.10661356

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CQCTL: A Cost-Optimized and Quadruple-Node-Upset Completely Tolerant Latch Design for Safety-Critical Applications 査読有り国際誌

Shen Z., Zhang Q., Roh B.H., Song J., Wen X.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid development of semiconductor technologies, latches are becoming increasingly sensitive to multiple node upsets, such as triple node upsets and quadruple node upsets (QNUs). Therefore, they should be considered for safety-critical applications. To effectively tolerate QNUs, this paper proposes a QNU-tolerant latch design with moderate overhead. The latch mainly comprises two parallel storage cells, and three 2-input C-elements. When any four internal nodes are flipped at the same time, the output value of the latch will not be affected. Simulation results not only confirm the QNU tolerance of the proposed latch but also demonstrate that the latch can reduce by 40.93% delay, 40.73% area, 13.11% power, and 71.19% delay-area-power product (DAPP) on average compared to the existing QNU-tolerant latches.

DOI： 10.1109/ITC-Asia62534.2024.10661360

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Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based Reconfigurable Processor (MRP) 査読有り国際誌

Sasagawa K., Wang S., Nishikawa T., Kai H., Higami Y., Takahashi H., Yotsuyanagi H., Ni T., Wen X.

2024 International Technical Conference on Circuits Systems Computers and Communications Itc Cscc 2024 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The Memory-based Reconfigurable Processor (MRP) is a memory-centric reconfigurable device that offers advantages in processing speed and cost compared to other reconfigurable devices like FPGAs, making it a promising alternative device for Artificial Intelligence applications such as neural networks (NNs). However, due to the unique structure of MRP, the method for implementing NNs on it has not yet been established. In our previous work [8], we have proposed a sparse neural network model named MNN (MRP Neural Networks), specifically designed to align with the unique connection structure of MRP for neural network integration. This paper extends our research by proposing a binarization method for MNN referred to as the BMNN using XNOR-Net to facilitate practical NNs application (handwriting digits recognition) on MRP. To enhance the performance of BMNN, a novel implementation strategy Deep-BMNN is also proposed aimed at increasing both the layer depth and the neuron count of BMNN by folding the logic routing on the MRP device. Experimental results using MNIST dataset for handwritten digits recognition demonstrate that our proposed binary NNs for MRP can achieve comparable accuracy to those of fully connected NNs employing real numbers.

DOI： 10.1109/ITC-CSCC62988.2024.10628398

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ICLTR: A Input-split Inverters and C-elements based Low-Cost Latch with Triple-Node-Upset Recovery 査読有り国際誌

Zhang J., Li Z., Shan G., Song J., Guo X., Wen X.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the semiconductor technology continues to advance, integrated circuits (ICs) are becoming increasingly sensitive to soft errors, e.g., double-node upsets (DNUs) and triplenode upsets (TNUs), induced by harsh radiation. In this paper, a low-cost latch design, namely ICLTR, using input-split inverters (ISIs) and C-elements to provide complete TNU recovery, is proposed. ICLTR consists of seven ISIs, seven 2-input C-elements and a clock-gated inverter, and all these elements are interlocked. Simulation results show the complete TNU recovery for ICLTR. The simulation results also show that ICLTR can save 59.5% of the transmission delay, 36.1% of the power consumption and 81.6% of the delay-area-power product (DAPP) on average when compared with the same type of TNU recovery latch designs.

DOI： 10.1109/ITC-Asia62534.2024.10661358

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Multiple-Error Interceptive Voter Designs for Safety-Critical Applications 査読有り国際誌

Li X., Song J., Zhang C., He Y., Wen X., Huang Z.

Proceedings Itc Asia 2024 8th IEEE International Test Conference in Asia 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes multiple-error interceptive voter designs for safety-critical applications. The proposed baseline voters comprise two-stage error-filters, in which the first stage includes two parallel C-elements (CEs) and the second stage includes one CE to filter soft errors. The voters have high-speed versions, any of which is embedded with a high-speed path from its original input to its output to reduce delay. Simulation results demonstrate the soft error tolerance of the proposed voters. Moreover, compared with the triple-modular-redundancy (TMR) voter that can only tolerate single soft errors, the proposed 3-input baseline and 4-input high-speed voters can tolerate double soft errors and can reduce the area-power-delay product by 77.03% and 95.05%, respectively, due to the use of a few transistors and a high-speed path. The voters are extended to intercept N-1 soft errors, N being the number of inputs of each voter. Note that the voters are also extended to make so that they can tolerate hard/permanent errors in addition to soft errors.

DOI： 10.1109/ITC-Asia62534.2024.10661339

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NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization 査読有り国際誌

Huang Z., Sun L., Wang X., Liang H., Lu Y., Yan A., Pan J., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 60 ( 4 ) 4590 - 4600 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Multi-node upset induced by radiation on integrated circuits has caused many circuit reliability issues. This paper proposes a single-event quadruple-node upset recovery latch (NEST), based on 4 circular feedback loops that are formed by 25 C-elements to realize high robustness. NEST achieves 29.02% reduction in power consumption compared to the LDAVPM latch and 51.44% reduction in setup time compared to the QRHIL latch. NEST also achieves a 99.29% quadruple-node upset recovery rate. Furthermore, a high-speed, high-precision optimization algorithm for multi-node upset recovery is also proposed and implemented. This algorithm achieves 99.84% reduction in simulation time for exhaustive fault injections having equivalent accuracy with HSPICE.

DOI： 10.1109/TAES.2024.3379962

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Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications 査読有り国際誌

Yan A., He Y., Huang Z., Yan W., Cui J., Wang X., Ni T., Girard P., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 44 ( 1 ) 390 - 394 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents radiation-hardened flip-flop (FF) designs capable of tolerating soft errors, e.g., single-node upsets (SNUs), double-node upsets (DNUs) and multiple-node upsets (MNUs). First, a 2-input FF and a 3-input FF are proposed as the baseline FFs that not only respectively tolerate SNUs and DNUs but also exhibit cost efficiency in terms of delay, power, and area. Through adding two stages of C-elements, a 4-input FF and a 5-input FF are proposed as the baseline FFs as well. Utilizing the structural characteristics of these FFs, an N-1 input FF and an N input FF are proposed as the extended FFs capable of tolerating more node upsets. Moreover, a highly efficient algorithm for verifying MNU-tolerance of these FFs is proposed. Algorithm and HSPICE-tool-based verification results both demonstrate the MNU-tolerance for the proposed FFs with more inputs.

DOI： 10.1109/TCAD.2024.3426271

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Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices 査読有り国際誌

Yan A., Lin Z., Liu G., Zhang Q., Huang Z., Cui J., Wen X., Girard P.

Proceedings - IEEE International Symposium on Circuits and Systems 2024年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Nonvolatile memories are widely used in emerging energy-harvesting Internet-of-Things (IoT) applications, and nonvolatile memories constructed from FeFET devices hold great promise. This paper presents a nonvolatile and single-event-upset (SEU)-recoverable latch based on FeFET and CMOS for energyharvesting devices. The latch uses n-type FeFET devices to provide nonvolatility without any additional control signals. Moreover, since the soft error problem has become increasingly severe, radiation hardening by design gains a great attention as a promising approach to mitigate the reliability issue. The latch uses feedback interlocked loops with n-type FeFETs and C-elements, enabling it to provide nonvolatility and SEU-recovery simultaneously. Simulation results with Candence Virtuoso verifies that the proposed latch design has correct functioning with excellent performance compared to the state-of-the-art designs.

DOI： 10.1109/ISCAS58744.2024.10558033

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Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware 査読有り国際誌

Ni T., Wen X., Amrouch H., Zhuo C., Song P.

ACM Transactions on Design Automation of Electronic Systems 29 ( 1 ) 2023年12月

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness 査読有り国際誌

Ni T., Peng Q., Bian J., Yao L., Huang Z., Yan A., Wang S., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 70 ( 12 ) 5074 - 5085 2023年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the input changes too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses. We study the output of the XOR gate when facing different inputs. By modeling the time of a fibonacci ring oscillator (FIRO) as an example, we find that the loss of short pulses in an inverter chain is the reason for making the FIRO enter into periodic oscillation. This phenomenon suppresses the accumulation of jitter and occurs periodically in existing structures. Our proposed structure uses independent sub-rings to accumulate jitter, allowing the main-ring to quickly generate short pulses to provide analog randomness. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA. The experimental results show that it has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.

DOI： 10.1109/TCSI.2023.3287162

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RMC-NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel 査読有り国際誌

Xu D., Ouyang Y., Zhou W., Huang Z., Liang H., Wen X.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 ( 12 ) 2061 - 2074 2023年12月

記述言語：英語掲載種別：研究論文（学術雑誌）

As chip fabrication has advanced to the nano level, the increased link density has heightened the risk of failures. The potential performance drawbacks resulting from these link failures have become a critical challenge in the design of reliable network-on-chip (NoC) systems. Fault-tolerant routing algorithms have proven to be effective strategies for handling this issue by diverting packets away from failed links to prevent congestion. However, these algorithms often result in excessive packet diversion, especially in the presence of a higher failure rate, which can significantly constrain the network's behavior. This article introduces a novel NoC design with reconfigurable multifunctional channels (RMC-NoC). This design dynamically adapts the channel functions in response to network conditions to ensure that packets from failed links follow their original paths. In addition, it presents a channel buffer bubble flow control mechanism that can resolve congestion by redistributing congested traffic within the channel buffer. The evaluation results demonstrate that our approach ensures superior network communication even in the presence of permanent link failures, with minimal area overhead and power consumption. Moreover, our system exhibits lower latency and higher throughput compared to state-of-the-art fault-tolerant methods across various link failure rates. Notably, even at a severe failure rate of 30%, RMC-NoC exhibits only a 16.3% increase in latency compared to an ideal failure-free environment (Baseline) while still maintaining system communication capabilities to a considerable extent.

DOI： 10.1109/TVLSI.2023.3321598

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An AI-Driven VM Threat Prediction Model for Multi-Risks Analysis-Based Cloud Cybersecurity 査読有り国際誌

Saxena D., Gupta I., Gupta R., Singh A.K., Wen X.

IEEE Transactions on Systems, Man, and Cybernetics: Systems 53 ( 11 ) 6815 - 6827 2023年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Cloud virtualization technology, ingrained with physical resource sharing, prompts cybersecurity threats on users' virtual machines (VMs) due to the presence of inevitable vulnerabilities on the offsite servers. Contrary to the existing works which concentrated on reducing resource sharing and encryption/decryption of data before transfer for improving cybersecurity which raises computational cost overhead, the proposed model operates diversely for efficiently serving the same purpose. This article proposes a novel multiple risks analysis-based VM threat prediction model (MR-TPM) to secure computational data and minimize adversary breaches by proactively estimating the VMs threats. It considers multiple cybersecurity risk factors associated with the configuration and management of VMs, along with analysis of users' behavior. All these threat factors are quantified for the generation of respective risk score values and fed as input into a machine learning-based classifier to estimate the probability of threat for each VM. The performance of MR-TPM is evaluated using benchmark Google Cluster and OpenNebula VM threat traces. The experimental results demonstrate that the proposed model efficiently computes the cybersecurity risks and learns the VM threat patterns from historical and live data samples. The deployment of MR-TPM with existing VM allocation policies reduces cybersecurity threats up to 88.9%.

DOI： 10.1109/TSMC.2023.3288081

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Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications 査読有り国際誌

Yan A., Cao A., Huang Z., Cui J., Ni T., Girard P., Wen X., Zhang J.

IEEE Transactions on Emerging Topics in Computing 11 ( 4 ) 1070 - 1081 2023年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

The continuous advancement of complementary metal-oxide-semiconductor technologies makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as double-node upsets (DNUs), are typical soft errors. This article proposes two radiation-hardened FF designs, namely DNU-tolerant FF (DUT-FF) and DNU-recoverable FF (DUR-FF). First, the DUT-FF which mainly consists of four dual-interlocked-storage-cells (DICEs) and three 2-input C-elements, is proposed. Then, to provide complete self-recovery from DNUs, the DUR-FF which mainly uses six interlocked DICEs is proposed. They have the following advantages: 1) They can completely protect against SNUs as well as DNUs; 2) the DUT-FF is cost-effective but the DUR-FF can provide complete self-recovery from any DNU. Simulations show the complete SNU/DNU tolerance of DUT-FF and the complete SNU/DNU self-recovery of DUR-FF but at the cost of indispensable area overhead when compared to the SNU hardened FFs. Besides, compared to the FFs of the same-type, the proposed FFs achieve a low delay making them suitable for high-performance applications.

DOI： 10.1109/TETC.2023.3317070

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GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting<sup>∗</sup> 査読有り国際誌

Shi S., Holst S., Wen X.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E106.D ( 10 ) 1694 - 1704 2023年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC’99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

DOI： 10.1587/transinf.2023EDP7011

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An equivalent processing method for integrated circuit electrical parameter data using BP neural networks 査読有り国際誌

Zhan W., Zhang L., Feng X., Pan P., Cai X., Wen X.

Microelectronics Journal 139 2023年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

In response to the current problem of significant differences between old and new equipment in testing electrical parameter data, as well as the lack of a unified parameter measurement standard in the IC testing industry, we propose an equivalent processing method for electrical parameter data using BP neural networks. Firstly, the method involves mapping the electrical parameter data measured by both the old and new equipment and subsequently trimming the test data. Then, the BP neural network is applied to the equivalent processing of the dataset, aiming to unify the test limits and electrical parameter data. This approach facilitates the extrapolation of new data from old equipment data, enabling a seamless data transfer and the harmonization of industry standards. This method effectively reduces the testing difficulty and misjudgment rate, thereby improving the testing efficiency for semiconductor manufacturers. The experimental results demonstrate that the proposed algorithm can accurately infer the new equipment's test data from the old equipment's data, ensuring data smooth transition. Furthermore, the modification of electrical parameter data does not affect the yield.

DOI： 10.1016/j.mejo.2023.105912

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Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications 査読有り国際誌

Yan A., Xiang J., Chang Y., Huang Z., Cui J., Girard P., Wen X.

Microelectronics Journal 139 2023年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper first presents a double-node upset (DNU) protected and sextuple cross-coupled static-random-access memory (SRAM) cell, i.e., SCCS-18T, for aerospace applications. The cell can recover from each possible single-node upsets (SNUs) as well as partial DNUs due to its formed large feedback loop that can retain values and intercept errors. To improve DNU self-recoverability, an enhanced version of the SCCS-18T cell, namely SCCS-18T-EV, is proposed. Due to the new formed structure, the SCCS-18T-EV can recover from more DNUs. Since parallel access transistors are used, the proposed cells have optimized read/write performance. Simulation results demonstrate the node-upset tolerance as well as the optimized operation performance of the proposed SCCS-18T and SCCS-18T-EV cells compared to existing SRAM cells.

DOI： 10.1016/j.mejo.2023.105908

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Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata 査読有り国際誌

Yan A., Li X., Liu R., Huang Z., Girard P., Wen X.

Electronics (Switzerland) 12 ( 14 ) 2023年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

DOI： 10.3390/electronics12143189

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A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications 査読有り国際誌

Yan A., Wei S., Zhang J., Cui J., Song J., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 167 - 171 2023年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose a double-node-upset recoverable latch that can completely recover from all possible double-node-upsets (DNUs) with low area and low delay. The latch consists of seven 2-input C-elements (CEs) implemented in 22nm complementary metal oxide semiconductor (CMOS) technology, making it area-efficient. The proposed latch employs the clock gating methodology and a high-speed transmission path, enabling it to perform with lower overhead in terms of transmission delay and power dissipation. Simulation results demonstrate that the proposed latch can provide complete DNU recovery. Compared with typical double-node-upset-recoverable latches, the proposed latch can save 89.74% of Area-Delay-Power Product (ADPP) on average.

DOI： 10.1145/3583781.3590281

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