研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 81 - 100 件目／全件表示 >>

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets 査読有り

Yan A., Chen Y., Zhou J., Cui J., Ni T., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2020-November 2020年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can provide self-recoverability from any single-node upsets (SNUs) and partial double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of six access transistors. Simulation results show that the SCCS18T cell can save approximately 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with typical hardened SRAM cells.

DOI： 10.1109/ATS49688.2020.9301569

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85099135793&origin=inward

Logic Fault Diagnosis of Hidden Delay Defects 査読有り

Holst S., Kampmann M., Sprenger A., Reimer J.D., Hellebrand S., Wunderlich H.J., Wen X.

Proceedings - International Test Conference 2020-November 2020年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-Than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

DOI： 10.1109/ITC44778.2020.9325234

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85100182545&origin=inward

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC 査読有り

Ni T., Chang H., Song T., Xu Q., Huang Z., Liang H., Yan A., Wen X.

IEEE Transactions on Circuits and Systems II: Express Briefs 67 ( 11 ) 2657 - 2661 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In this brief, a non-invasive online solution for 2.5D IC based on distributed pulse shrinking is proposed to test the faults of interconnects. Furthermore, a regression model based on artificial neural network (ANN) is proposed in order to judge whether the interconnects are faulty and quantify the degree of the faults in real time by online monitoring the delay of interconnects. Experiments on defect detection are presented through HSPICE simulation with realistic models for 45nm CMOS technology. The results show that the proposed method has features including: high resolution, low area overhead, high robustness, and be able to predict the class and the fault size.

DOI： 10.1109/TCSII.2019.2962824

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85087478428&origin=inward

Design of double-upset recoverable and transient-pulse filterable latches for low-power and low-orbit aerospace applications 査読有り

Yan A., Chen Y., Xu Z., Chen Z., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 5 ) 3931 - 3940 2020年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a singleevent Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhancedversion of theDURTPF latch, namelyDURTPF-EV.TheDURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost ofmoderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.

DOI： 10.1109/TAES.2020.2982341

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85105864697&origin=inward

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors 査読有り

Dou Z., Yan A., Zhou J., Hu Y., Chen Y., Ni T., Cui J., Girard P., Wen X.

Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 35 - 40 2020年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

DOI： 10.1109/ITC-Asia51099.2020.00018

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85096363091&origin=inward

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications 査読有り

Yan A., Xu Z., Yang K., Cui J., Huang Z., Girard P., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 4 ) 2666 - 2676 2020年08月

記述言語：英語掲載種別：研究論文（学術雑誌）

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node upsets (TNUs) are becoming more and more an issue in storage cells used for applications constrained by their environment, such as aerospace applications confronted to radiations. This article presents a novel triple-modular redundancy without voter based high-impedance state (HIS) insensitive and MNU-tolerant latch design, namely TMHIMNT, to ensure both high reliability and low cost. The TMHIMNT latch mainly comprises triple clock-gating (CG) based dual-interlocked-storage-cells (DICEs) and four inverters. Through three internal inverters, the values stored in DICEs converge to a common node feeding an output-level inverter, enabling the TMHIMNT latch to tolerate any possible MNU. Simulation results demonstrate the MNU tolerance of the proposed TMHIMNT latch. Due to the disuse of C-elements, the proposed TMHIMNT latch is insensitive to the HIS, making the latch more reliable for aerospace applications. Moreover, compared with the state-of-the-art TNU hardened latch, due to the use of a high-speed path, CG technologies, and fewer transistors, the proposed TMHIMNT latch can achieve 98% delay, 17% power, and 29% area reductions, respectively.

DOI： 10.1109/TAES.2019.2951186

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85089465000&origin=inward

HITTSFL: Design of a cost-effective HIS-Insensitive TNU-Tolerant and SET-Filterable latch for safety-critical applications 査読有り

Yan A., Feng X., Zhao X., Zhou H., Cui J., Ying Z., Girard P., Wen X.

Proceedings - Design Automation Conference 2020-July 2020年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a cost-effective, high-impedance-state (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storage-cells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-the-art TNU hardened latch (TNUHL) that cannot filter SETs.

DOI： 10.1109/DAC18072.2020.9218704

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85093914925&origin=inward

Information Assurance through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment 査読有り

Yan A., Hu Y., Cui J., Chen Z., Huang Z., Ni T., Girard P., Wen X.

IEEE Transactions on Computers 69 ( 6 ) 789 - 799 2020年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

DOI： 10.1109/TC.2020.2966200

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85084862252&origin=inward

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments 査読有り

Yan A., Feng X., Hu Y., Lai C., Cui J., Chen Z., Miyase K., Wen X.

IEEE Transactions on Aerospace and Electronic Systems 56 ( 2 ) 1163 - 1171 2020年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

In harsh radiation environments, nanoscale CMOS latches have become more and more vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm CMOS technology. The proposed latch is mainly constructed from seven mutually feeding-back soft-error-interceptive modules (SIMs), any of which consists of two three-input C-elements and one two-input C-element. Due to the mutual feedback mechanism of SIMs and the dual-level soft-error interception of each SIM, the latch can self-recover from any possible TNU. Simulation results demonstrate the TNU self-recoverability from any key TNU for the proposed latch using redundant silicon area. Furthermore, using a high-speed path, the proposed latch saves about 95.45% transmission delay and 86.97% delay-power-area product, compared with the state-of-the-art TNU-tolerant latch that cannot provide complete TNU self-recoverability at all.

DOI： 10.1109/TAES.2019.2925448

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85080857920&origin=inward

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs 査読有り

Yan A., Ling Y., Cui J., Chen Z., Huang Z., Song J., Girard P., Wen X.

IEEE Transactions on Circuits and Systems I: Regular Papers 67 ( 3 ) 879 - 890 2020年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

DOI： 10.1109/TCSI.2019.2959007

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85080857044&origin=inward

Dual-interlocked-storage-cell-based double-node-upset self-recoverable flip-flop design for safety-critical applications 査読有り

Yan A., Xu Z., Cui J., Ying Z., Huang Z., Liang H., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2020-October 2020年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a novel dual-interlocked storage-cell (DICE)-based double-node-upset (DNU) self-recoverable, namely DURI-FF, in the nano-scale CMOS technology. The master latch of the DURI-FF cell consists of three transmission gates (TGs) and three interlocked DICEs with three common nodes. The common nodes are connected to TGs for value initialization. The slave latch of the DURI-FF cell comprises six TGs, six inverters and three interlocked DICEs. The outputs of the inverters respectively feed the internal nodes of the slave latch. The interlocked DICEs make the master latch and the slave latch DNU self-recoverable. Simulation results validate the DNU self-recoverability of the proposed DURI-FF cell. Moreover, compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85102840573&origin=inward

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications 査読有り

Yan A., Wu Z., Zhou J., Hu Y., Chen Y., Ying Z., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2019-December 55 - 60 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The Aggressive technology scaling makes modern advanced SRAMs more and more sensitive to soft errors that include single-node upsets (SNUs) and double-node upsets (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs. The cell mainly consists of six cross-coupled input-split inverters, constructing a large error-interceptive feedback loop to robustly retain stored values. Since the cell has many redundant storage nodes, the cell achieves the following robustness: (1) the cell can self-recover from all possible SNU; (2) the cell can self-recover from partial DNUs; (3) the cell can avoid the occurrence of other DNUs due to node-separation. Simulation results validate the excellent robustness of the proposed cell. Moreover, compared with the state-of-the-art typical existing hardened cells, the proposed cell achieves an approximate 61% read access time as well as 12% write access time reduction at the costs of 47% power dissipation as well as 44% silicon area on average.

DOI： 10.1109/ATS47505.2019.00006

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85078343707&origin=inward

Targeted partial-shift for mitigating shift switching activity hot-spots during scan test 査読有り

Holst S., Shi S., Wen X.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2019-December 124 - 129 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

DOI： 10.1109/PRDC47002.2019.00042

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85078466669&origin=inward

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications 査読有り

Yan A., Wu Z., Lu L., Chen Z., Song J., Ying Z., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2019-December 43 - 48 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.

DOI： 10.1109/ATS47505.2019.000-2

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85078359545&origin=inward

Variation-aware small delay fault diagnosis on compressed test responses 査読有り

Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings - International Test Conference 2019-November 2019年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

DOI： 10.1109/ITC44170.2019.9000143

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85081599098&origin=inward

A fault-tolerant MPSoC for CubeSats 査読有り国際誌

Fuchs C., Chou P., Wen X., Murillo N., Furano G., Holst S., Tavoularis A., Lu S., Plaat A., Marinis K.

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 2019年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

DOI： 10.1109/DFT.2019.8875417

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85074436279&origin=inward

A static method for analyzing hotspot distribution on the LSI 査読有り

Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 73 - 78 2019年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Performance degradation caused by high IR-drop in normal functional mode of LSI can be avoided by improving the power supply network in the layout design phase. However, while IR-drop increases much more in test mode than in normal functional mode, excessive IR-drop in test mode is not appropriately considered in the layout design phase. Excessive IR-drop in test mode causes over-testing, which wrongly determines a fault free LSI in normal functional mode to be faulty. In this work, we propose a method for analyzing high IR-drop areas (hotspot distribution), which is necessary to effectively and efficiently reduce excessive IR-drop.

DOI： 10.1109/ITC-Asia.2019.00026

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85074388891&origin=inward

A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells 査読有り国際誌

Song Z., Yan A., Cui J., Chen Z., Li X., Wen X., Lai C., Huang Z., Liang H.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 139 - 144 2019年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81% for the proposed latch compared with the only existing SETU hardened latch.

DOI： 10.1109/ITC-Asia.2019.00037

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85074437547&origin=inward

Power-Aware Testing for Low-Power VLSI Circuits 招待有り査読有り国際誌

X. Wen

15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits Paper S12-1 2019年06月

Small Delay Fault Diagnosis with Compacted Responses 査読有り国際誌

S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich

Poster at ACM Design Automation Conf. 2019年06月

　前のページ - 次のページ　

1
2
3
4
5
6
7
8
9
10
11
12
13
14