研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 101 - 120 件目／全件表示 >>

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications 査読有り国際誌

Yan A., Hu Y., Song J., Wen X.

Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 1679 - 1684 2019年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 EDAA. This paper presents a single-event double-upset (SEDU) self-recoverable and single-event transient (SET) pulse filterable latch design for low power applications in 22nm CMOS technology. The latch mainly consists of eight mutually feeding back C-elements and a Schmitt trigger. Simulation results have demonstrated both the SEDU self-recoverability and SET pulse filterability for the latch using redundant silicon area. Using clock gating technology, the latch saves about 54.85% power dissipation on average compared with the up-to-date SEDU self-recoverable latch designs which are not SET pulse filterable at all.

DOI： 10.23919/DATE.2019.8714841

Scopus

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STAHL: A novel scan-test-aware hardened latch design 査読有り国際誌

Ma R., Holst S., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2019-May 2019年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulner-ability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode.

DOI： 10.1109/ETS.2019.8791544

Kyutacar

Scopus

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Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout 査読有り国際誌

Yan A., Wu Z., Guo J., Song J., Wen X.

IEEE Transactions on Reliability 68 ( 1 ) 354 - 363 2019年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2018 IEEE. This paper presents two novel memory cell designs that can completely tolerate double-node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant storage nodes, the cell achieves the following robustness: 1) In the case of 1 being stored, the cell can self-recover from any double-node upset (DNU) as well as any single node upset (SNU); 2) in the case of 0 being stored, the cell can self-recover from any double-adjacent-node upset (DANU), partial double-separated-node upset (DSNU) as well as any SNU. Any other DSNU can be tolerated by the cell due to the use of the layout approach. Second, a layout-independent cell is proposed that can self-recover from any DNU as well as any SNU. Simulation results validate the robustness of the proposed cell designs. Furthermore, compared with typical existing radiation hardened memory cells, the proposed layout-dependent cell saves 55.60% read access time and 33.76% write access time at the costs of 4.28% power dissipation and 39.01% silicon area on average, still low compared with layout-independent cell designs.

DOI： 10.1109/TR.2018.2876243

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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults 査読有り国際誌

Ni T., Yao Y., Chang H., Lu L., Liang H., Yan A., Huang Z., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 ( 10 ) 2938 - 2951 2019年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

IEEE Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the FTSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3D-ICs. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based RTSV architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this paper, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.

DOI： 10.1109/TCAD.2019.2946243

Scopus

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Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets 査読有り

Yan A., Zhou J., Hu Y., Cui J., Huang Z., Girard P., Wen X.

IEEE Access 7 176188 - 176196 2019年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

DOI： 10.1109/ACCESS.2019.2958109

Scopus

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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing 査読有り国際誌

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. High scan shift power often leads to excessive heat as well as shift timing failures. Partial shift (shifting a subset of scan chains at a time) is a widely adopted approach for avoiding excessive heat by reducing global switching activity, we show for the first time that it may actually cause excessive IR-drop on some clock buffers and worsen shift clock skews, thus increasing the risk of shift timing failures. This paper addresses this problem with an innovative method, namely Clock-Skew-Aware Scan Chain Grouping (CSA-SCG). CSA-SCG properly groups scan chains to be shifted simultaneously so as to reduce the imbalance of switching activity around the clock paths for neighboring scan flip-flops in scan chains. Experiments on large ITC'99 benchmark circuits demonstrate the effectiveness of CSA-SCG for reducing scan shift clock skews to lower the risk of shift timing failures in partial shift.

DOI： 10.1109/ATS.2018.00037

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Message from the Technical Program Co-Chairs 招待有り査読有り国際誌

Li H., Wen X., Huang Z.

Proceedings of the Asian Test Symposium 2018-October 2018年12月

Foreword 査読有り国際誌

Li X., Li H., Cheng K.T.T., Wen X.

Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018 2018年09月

The impact of production defects on the soft-error tolerance of hardened latches 査読有り国際誌

Holst S., Ma R., Wen X.

Proceedings of the European Test Workshop 2018-May 1 - 6 2018年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces the test coverage of cell-internal production defects. Moreover, the test escapes reduce the soft-error tolerance of the defective latches. This work introduces a new soft-error vulnerability metric called Post Test Vulnerability Factor that correctly measures the added vulnerability to transiant frults such as particle strikes caused by undiscovered production defects within hardened latches.

DOI： 10.1109/ETS.2018.8400694

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Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

Proceedings of the 27th International Workshop on Logic and Synthesis 124 - 131 2018年06月

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application 査読有り国際誌

A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

IEEE Transactions on Circuits and Systems II: Express Briefs 66 ( 2 ) 287 - 291 Early Access 2018年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.

DOI： 10.1109/TCSII.2018.2849028

Scopus

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A Method to Detect Bit Flips in a Soft-Error Resilient TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 ( 6 ) 1185 - 1196 2018年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE. Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors k. KX-TCAM corrects up to k -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers.

DOI： 10.1109/TCAD.2017.2748019

Scopus

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The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches 査読有り国際誌

S. Holst, R. Ma, X. Wen

Proceedings of IEEE European Test Symposium Paper 7A-1 2018年05月

Design Automation for Legacy Circuits 査読有り国際誌

I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies 174 - 179 2018年03月

Locating Hot Spot with Justification Techniques in a Layout Design 査読有り国際誌

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

Proceedings of IEEE Workshop on RTL and High Level Testing Paper S1.2 2017年11月

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption 査読有り国際誌

Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian

Proceedings of the Asian Test Symposium 140 - 145 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Taiwan Taipei 2017年11月27日 - 2017年11月30日

© 2017 IEEE. Loading and unloading test patterns during scan testing causes many scan flip-flops to trigger simultaneously. This instantaneous switching activity during shift in turn may cause excessive IR-drop that can disrupt the states of some scan flip-flops and corrupt test stimuli or responses. A common design technique to even out these instantaneous power surges is to design multiple scan chains and shift only a group of the scan chains at a same time. This paper introduces a novel algorithm to optimally group scan chains so as to minimize the probability of test data corruption caused by excessive instantaneous IR-drop on scan flip-flops. The experiments show optimal results on all large ITC'99 benchmark circuits.

DOI： 10.1109/ATS.2017.37

Kyutacar

Scopus

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Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors 査読有り国際誌

S. Holst, E. Schneider, H. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen

Proceedings - International Test Conference 2017-December 1 - 8 Paper 3.4 2017年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA Fort Warth 2017年10月29日 - 2017年11月03日

© 2017 IEEE. Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases of test data corruption are mitigated in a non-intrusive way by selective test data manipulation and masking of affected responses. Evaluation results show the computational feasibility of our method for large benchmark circuits, and demonstrate that a few targeted pattern changes provide large potential gains in shift safety and test time with negligible cost in fault coverage.

DOI： 10.1109/TEST.2017.8242055

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A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips 査読有り国際誌

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Transactions on Emerging Topics in Computing 8 ( 3 ) 591 - 601 Early Access 2017年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

DOI： 10.1109/TETC.2017.2767070

Kyutacar

Scopus

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Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs 査読有り国際誌

T. Ni, M. Nie, H. Liang, J. Bian, X. Xu, X. Fang, Z. Huang, X. Wen

IEICE Electronics Express 18 ( 14 ) Letter 20170590 2017年10月

GPU-Accelerated Simulation of Small Delay Faults 査読有り国際誌

E. Schneider, M. Kochte, S. Holst, X. Wen, H. Wunderlich

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 ( 5 ) 829 - 841 2017年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE.Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units (GPUs) with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.

DOI： 10.1109/TCAD.2016.2598560

Scopus

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論文 - 温　暁青