研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 101 - 120 件目／全件表示 >>

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications 査読有り国際誌

Yan A., Chang Y., Xiang J., Luo H., Cui J., Huang Z., Ni T., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 293 - 298 2023年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose two Highly Reliable and High-Speed SRAM cells, namely HRHS18T and HRHS18T_EV. The proposed cells can be applied to safety-critical applications due to their excellent self-recoverability from node-upsets. Meanwhile, the proposed cells have smaller read/write delay than other state-of-the-art hardened SRAMs. Simulation and quantitative calculation results show that, the proposed HRHS18T cell can save 65.05% read time and 38.12% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs. The results also show that the HRHS18T_EV cell can save 65.05% read time and 73.28% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs.

DOI： 10.1145/3583781.3590261

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Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array 査読有り国際誌

Chen N., Cheng F., Han C., Jiang J., Wen X.

Tsinghua Science and Technology 28 ( 2 ) 330 - 343 2023年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

To solve the problem of grid coarse-grained reconfigurable array task mapping under multiple constraints, we propose a Loop Subgraph-Level Greedy Mapping (LSLGM) algorithm using parallelism and processing element fragmentation. Under the constraint of a reconfigurable array, the LSLGM algorithm schedules node from a ready queue to the current reconfigurable cell array block. After mapping a node, its successor's indegree value will be dynamically updated. If its successor's indegree is zero, it will be directly scheduled to the ready queue; otherwise, the predecessor must be dynamically checked. If the predecessor cannot be mapped, it will be scheduled to a blocking queue. To dynamically adjust the ready node scheduling order, the scheduling function is constructed by exploiting factors, such as node number, node level, and node dependency. Compared with the loop subgraph-level mapping algorithm, experimental results show that the total cycles of the LSLGM algorithm decreases by an average of 33.0% (PEA4×4) and 33.9% (PEA7×7). Compared with the epimorphism map algorithm, the total cycles of the LSLGM algorithm decrease by an average of 38.1% (PEA4×4) and 39.0% (PEA7×7). The feasibility of LSLGM is verified.

DOI： 10.26599/TST.2022.9010001

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Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning 査読有り国際誌

Nie M., Jiang W., Yang W., Wang S., Wen X., Ni T.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Defect diagnosis and localization in wafer maps are crucial tasks in semiconductor manufacturing. Existing deep learning methods often require pixel-level annotations, making them impractical for large-scale deployment. In this paper, we propose a novel weakly supervised learning approach to achieving high-precision defect identification and effective localization with only image-level labels. By leveraging the information of defect types and locations, we introduce a weighted fusion of activation maps, called Class Activation Map (CAM), to highlight classspecific regions. We further enhance defect localization accuracy and completeness by employing optimized region growing operations to eliminate noise in defect regions. Moreover, we present an optimized inference method that provides meaningful visual explanations for defect recognition. Experimental results on real-world wafer map images demonstrate the effectiveness of our approach in accurately segmenting defect patterns with no pixel-level annotations. By training the model solely on wafer map image classification labels, our proposed model significantly improves defect recognition, facilitating efficient defect analysis in semiconductor manufacturing. The proposed weakly supervised learning approach offers a practical solution for defect diagnosis and localization, with the potential of widespread adoption in the semiconductor industry.

DOI： 10.1109/ATS59501.2023.10317989

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Design of Low-Cost Approximate CMOS Full Adders 査読有り国際誌

Yan A., Wei S., Li Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings - IEEE International Symposium on Circuits and Systems 2023-May 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Many applications have an inherent tolerance for insignificant inaccuracies. Full adders are key arithmetic functions for many error-tolerant applications. Approximate full adders are considered an efficient technique to trade off energy relative to performance and accuracy. In this paper, we propose four approximate full adders with low overhead. The proposed and the existing approximate full adders are classified into two groups according to their error distances. Simulation results show that, compared with the existing approximate full adders, in the first group, the proposed ones can reduce power-area-delay product (PADP) by 61.83%, power by 54.15%, area by 44.67%, and delay by 22.78% on average; in the second group, the proposed ones can reduce PADP by 97.01%, power by 93.43%, area by 24.98%, and delay by 36.14% on average.

DOI： 10.1109/ISCAS46773.2023.10181531

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Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness 査読有り国際誌

Yan A., Zhou C., Wei S., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As CMOS processes continue to shrink, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiation. To tolerate MNU, a novel quadruple-node-upset (QNU) self-recoverable latch is proposed in this paper. The proposed latch is mainly constructed from six blocks of three-level C-elements (TLCEs) and six inverters. With the mutual feedback of the various TLCEs, the proposed latch can recover from any QNU. Furthermore, due to the clock gating methodology and a high-speed transmission path, the proposed latch has lower overhead in terms of power dissipation and transmission delay. Simulation results show that the proposed latch achieves high reliability with moderate overhead compared to typical existing latches.

DOI： 10.1109/ITC-Asia58802.2023.10301187

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Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications 査読有り国際誌

Yan A., Xiang J., Huang Z., Ni T., Cui J., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

For high-speed operations, low power consumption and small silicon area, transistors are being scaled aggressively. Meanwhile, circuit reliability is facing greater challenges in advanced technologies. In this paper, a highly reliable and low-power SRAM with double-node-upset (DNU) recovery, namely HRLP16T, is proposed for safety-critical fields. HRLP16T can recover from single-node-upset (SNU) at all the sensitive nodes, and it has eight node pairs recoverable from DNUs. Simulation results demonstrate its advantages in terms of delay and power consumption over typical existing SRAM cell designs.

DOI： 10.1109/ITC-Asia58802.2023.10301170

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BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell 査読有り国際誌

Holst S., Ma R., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2023-May 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Ensuring the correct operation of modern VLSI circuits within safety-critical systems is essential since modern technology nodes are more susceptible to Early-Life Failures (ELFs) and radiation-induced Soft-Errors (SEs). Tackling both of these challenges leads to contradicting design requirements: Effective in-field ELF detection requires online-monitoring or periodic built-in self-Testing with excellent cell-internal defect coverage. SE-hardened latch designs, however, are less testable because they are designed to mask cell-internal failures. We propose BiSTAHL, a new SE-hardened scan-cell design that is fully built-in self-Testable for both production defects and ELFs.

DOI： 10.1109/ETS56758.2023.10174154

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Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications 査読有り国際誌

Yan A., Li X., Gao Z., Huang Z., Ni T., Wen X.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of CMOS technologies, integrated circuits are becoming more prone to soft errors, e.g., triple-node upsets (TNUs). In this paper, to effectively tolerate TNUs, an input-split C-element-based DICEs (IC-DICEs) based TNU-recovery latch is proposed. The latch employs three interlocked IC-DICEs to allow recovering from any TNU. Simulations demonstrate the TNU recovery of the latch, and also demonstrate that the proposed latch can reduce delay by 87.21%, area by 27.04%, and delay-area-power product (DAPP) by 87.44% on average, compared to the alternative latches.

DOI： 10.1109/ATS59501.2023.10317977

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A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery 査読有り国際誌

Yan A., Li X., Ni T., Huang Z., Wen X.

Proceedings - 2023 10th International Conference on Dependable Systems and Their Applications, DSA 2023 474 - 476 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The aggressive shrinking of CMOS makes flip-flops (FFs) vulnerable to single-node upset (SNU) as well as double-node upset (DNU). SNU and DNU are typical soft errors. This paper presents a highly reliable and low delay FF providing complete DNU-recovery. Simulations show the complete DNU-recovery as well as low-delay for our proposed FF making the FF suitable for high-robustness and high-performance applications.

DOI： 10.1109/DSA59317.2023.00065

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A Low Overhead and Double-Node-Upset Self-Recoverable Latch 査読有り国際誌

Yan A., Xia F., Ni T., Cui J., Huang Z., Girard P., Wen X.

Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the rapid advancement of semiconductor technologies, integrated circuits, especially storage elements (e.g., latches) have become increasingly vulnerable to soft errors. In order to effectively tolerate double-node-upsets (DNUs) caused by radiation and reduce the power and area of latches, this paper proposes a DNU self-recoverable latch with low overhead in terms of power and area. The proposed latch mainly comprises seven 2-input C-elements and two inverters to achieve DNU self-recovery. Simulation results show that the proposed latch can recover from all possible DNUs and that it can reduce delay by 45.7%, power by 29.1%, area by 65.9%, and area-power-delay-product by 87.4%, on average, compared to typical existing DNU self-recoverable latches.

DOI： 10.1109/ITC-Asia58802.2023.10301166

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A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges 査読有り国際誌

Ni T., Li F., Peng Q., Wang S., Wen X.

Proceedings of the 2023 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2023 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Physically unclonable functions (PUFs) are an attractive and low-cost security primitive because it requires no storage and is easy to implement. PUFs arise from changes in the manufacturing process of the device and can generate secure and unique keys for secure storage, authentication, and data encryption. In addition, the keys generated by PUFs should be reliable, independent, and themselves resistant to attacks and reverse engineering. In this paper, a new PUF framework is proposed, which segments the whole structure, introduces the non-linearity of the structure, uses the previous challenges and the later challenges are XOR with the previous response, which introduces the obfuscation of the challenges to improve the resistance to machine learning attack. The framework can be used for any kind of strong PUF implementation. In this paper, the whole framework is implemented with RO ring PUF, the PUF shows excellent performance, and the RO ring is modified with four input multiplexer and only a pair of counters and a comparator for multiple rings, which significantly reduces the hardware resource consumption. The PUF has passed machine learning attacks with significant resistance to Logistic Regression(LR) and Covariance Matrix Adaptation Evolutionary Strategies(CMA-ES).

DOI： 10.1109/AsianHOST59942.2023.10409383

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A High-Performance and P-Type FeFET-Based Non-Volatile Latch 査読有り国際誌

Yan A., Chen Y., Huang Z., Cui J., Wen X.

Proceedings of the Asian Test Symposium 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Non-volatile memory has a significant future in the Internet of Things and computation-in-memory applications. Among them, non-volatile memories using emerging FeFET devices have garnered significant attention. This paper proposes a novel P-type FeFET -based non-volatile latch. This design takes advantage of the unique characteristics of a P-type FeFET device to achieve non-volatility with no additional control signals. The Cadence simulation tool Virtuoso verifies that our proposed design has correct functioning with excellent power, area, and delay performance compared to state-of-the-art designs.

DOI： 10.1109/ATS59501.2023.10318017

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Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling 査読有り国際誌

Shi S., Holst S., Wen X.

Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 501 - 507 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Scan shift causes a lot of switching activity in the combinational logic that in turn can lead to high IR-drop. Excessive IR-drop may corrupt test vectors or responses during shifting, leading to test-induced yield-loss. Power-aware X-filling is a widely used method to reduce the overall switching activity during shifting without modifying the scan infrastructure. While such untargeted approaches help reduce the average IR-drop during shifting, some hot-spots of worst-case IR-drop still remain. Through an innovative in-depth IR-drop analysis of high-risk shift cycles, we discovered that these hot-spots are caused by a few High-Impact scan-cell Transitions (HITs). In this paper, we propose to reduce the peak IR-drop during scan shift by using a novel X-filling strategy that (1) identifies HITs through GPU-accelerated IR-drop estimation, and (2) adjusts the X-filling of test vectors to mitigate the remaining worst-case IR-drop hotspots. The results on ITC'99 benchmark circuits demonstrate a 26% peak IR-drop reduction on average without impact on fault coverage or test vector count.

DOI： 10.1109/MCSoC60832.2023.00080

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SASL-JTAG: A Light-Weight Dependable JTAG 査読有り国際誌

Wang S., Wei S., Ma J., Kai H., Higami Y., Takahashi H., Shimizu A., Wen X., Ni T.

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper addresses the performance imbalance issue of IoT systems and proposes a lightweight JTAG authentication scheme for enhancing the dependability of IoT devices. We propose a one-time authentication protocol, called SAS-L(Simple And Secure Light authentication), to improve the dependability of the JTAG, referred to as SASL-JTAG. The architecture of the SASLJTAG authentication is designed and implemented on an FPGA to verify its functionality and evaluate hardware overhead. SASL-JTAG offers a cost-effective and scalable solution for securing JTAG systems in IoT devices while ensuring high reliability.

DOI： 10.1109/DFT59622.2023.10313532

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A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design 査読有り国際誌

Yan A., Wei S., Chen Y., Fan Z., Huang Z., Cui J., Girard P., Wen X.

Micromachines 13 ( 11 ) 2022年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.

DOI： 10.3390/mi13111802

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85141815384&origin=inward

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications 査読有り国際誌

Yan A., Qian K., Song T., Huang Z., Ni T., Chen Y., Wen X.

Integration 86 22 - 29 2022年09月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a novel radiation hardened latch (namely DCTELC) that can completely tolerate single-node upsets and double-node upsets (DNUs) for high-performance applications. The latch mainly consists of a clock-gating based dual-interlocked-cell (DICE), a 2-input C-element, and a clock-gating based 2-input C-element. The latch introduces isolated nodes to tolerate DNUs and the isolated nodes have no time to float for high-performance applications. Simulation results demonstrate the complete DNU tolerance for the latch and an 86% power-area-delay product (PADP) saving on average compared with state-of-the-art DNU-tolerant latches. Moreover, compared with the existing latches of the same type, the power dissipation, silicon area, transmission delay, and PADP of the proposed latch are the smallest.

DOI： 10.1016/j.vlsi.2022.04.008

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85129713569&origin=inward

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology 査読有り国際誌

Yan A., Zhou Z., Wei S., Cui J., Zhou Y., Ni T., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 255 - 260 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input C-elements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively.

DOI： 10.1145/3526241.3530321

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85131668290&origin=inward

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications 査読有り国際誌

Yan A., He Z., Xiang J., Cui J., Zhou Y., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 261 - 266 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Aggressive scaling of CMOS technologies requires to pay attention to the reliability issues of circuits. This paper presents two highly reliable RHBD 10T and 12T SRAM cells, which can protect against single-node upsets (SNUs) and double-node upsets (DNUs). The 10T cell mainly consists of two cross-coupled input-split inverters and the cell can robustly keep stored values through a feedback mechanism among its internal nodes. It also has a low cost in terms of area and power consumption, since it uses only a few transistors. Based on the 10T cell, a 12T cell is proposed that uses four parallel access transistors. The 12T cell has a reduced read/write access time with the same soft error tolerance when compared to the 10T cell. Simulation results demonstrate that the proposed cells can recover from SNUs and a part of DNUs. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed 10T cell can save 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

DOI： 10.1145/3526241.3530312

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85131690517&origin=inward

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications 査読有り国際誌

Yan A., Chen Y., Song S., Zhai Z., Cui J., Huang Z., Girard P., Wen X.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 333 - 338 2022年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a novel sextuple cross-coupled dual-interlocked-storage-cell (DICE) based double-node-upset (DNU) recoverable and low-delay flip-flop (FF), namely SCDRL-FF, for aerospace applications. The SCDRL-FF mainly consists of sextuple cross-coupled DICEs controlled by clock-gating. The use of clock-gating based DICEs significantly reduces the CLK-Q transmission delay of the SCDRL-FF. Through the redundant and interlocked clock-gating based DICEs, the SCDRL-FF can provide complete DNU recoverability. Simulation results demonstrate the DNU recoverability of the SCDRL-FF and a 65% delay reduction on average compared with the state-of-the-art hardened FFs. The low delay overhead makes the proposed SCDRL-FF effectively applicable to high-performance applications and the DNU recoverability makes the proposed SCDRL-FF also suitable for aerospace applications.

DOI： 10.1145/3526241.3530355

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A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center 査読有り国際誌

Saxena D., Gupta I., Kumar J., Singh A.K., Wen X.

IEEE Systems Journal 16 ( 2 ) 3163 - 3174 2022年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

To facilitate cost-effective and elastic computing benefits to the cloud users, the energy-efficient and secure allocation of virtual machines (VMs) plays a significant role at the data center. The inefficient VM placement (VMP) and sharing of common physical machines among multiple users leads to resource wastage, excessive power consumption, increased intercommunication cost, and security breaches. To address the aforementioned challenges, a novel secure and multiobjective VMP (SM-VMP) framework is proposed with an efficient VM migration. The proposed framework ensures an energy-efficient distribution of physical resources among VMs, which emphasizes secure and timely execution of user application by reducing intercommunication delay. The VMP is carried out by applying the proposed Whale Optimization Genetic Algorithm (WOGA), inspired by whale evolutionary optimization and nondominated sorting based genetic algorithms. The performance evaluation for static and dynamic VMP and comparison with recent state of the arts observed a notable reduction in shared servers, intercommunication cost, power consumption, and execution time up to 28.81%, 25.7%, 35.9%, and 82.21%, respectively with increased resource utilization up to 30.21%.

DOI： 10.1109/JSYST.2021.3092521

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