研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 221 - 240 件目／全件表示 >>

Search Space Reduction for Low-Power Test Generation 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

IEEE Asian Test Symposium 171 - 176 2013年11月

Test Pattern Modification for Average IR-drop Reduction 査読有り国際誌

J. Li, W-S. Ding, H-Y. Hsieh, X. Wen

IEEE International Test Conference Poster 2013年09月

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing 査読有り国際誌

K. Miyase, R. Sakai, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

IEICE Transaction on Information and Systems E96-D ( 9 ) 2003 - 2011 2013年09月

SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop Paper 4.4 2013年07月

Controllability Analysis of Local Switching Activity for Layout Design 査読有り国際誌

K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara

Workshop on Design and Test Methodologies for Emerging Technologies Paper 2 2013年05月

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE Design & Test of Computers 30 ( 4 ) 60 - 70 2013年04月

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression 査読有り国際誌

K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, L.-T. Wang

26th International Conference on VLSI Design 279 - 284 2013年01月

Fault Detection with Optimum March Test Algorithm 査読有り国際誌

N. Zakaria, W. Hassan, I. Halin, R. Sidek, X. Wen

Journal of Theoretical and Applied Information Technology 47 ( 1 ) 18 - 27 2013年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents a research work aimed to detect previously-undetected faults, either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both in March Algorithm such as MATS++(6N), March C-(10N), March SR(14N), and March CL(12N). The main focus of this research is to improve fault coverage on Single Cell Faults as well as Static Double Cell Faults detection, using specified test algorithm. Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds) and Deceptive Read Destructive Faults (CFdrds) are types of faults mainly used in this research. The experiment result published in [1] shows BIST (Built-In-Self-Test) implementation with the new algorithm. It provides the same test length but with bigger area overhead, we therefore proposed a new 14N March Test Algorithm with fault coverage of more than 95% using solid 0s and 1s Data Background (DB). This paper reveals the design methodology to generate DB covers all memories function by applying non-transition data, transition data, and single read and double read data. The automation hardware was designed to give the flexibility to the user to generate other new March Algorithm prior to the selected algorithm and analyzed the performance in terms of fault detection and power consumption. © 2005 - 2013 JATIT & LLS. All rights reserved.

Kyutacar

Scopus

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Estimation of the Amount of Don't-Care Bits in Test Vectors 査読有り国際誌

K. Miyase, S. Kajihara, X. Wen

IEEE Workshop on RTL and High Level Testing 2012年11月

A Transition Isolation Scan Cell Design for Low Shift and Capture Power 査読有り国際誌

Y.-T. Lin, J.-L Huang, X. Wen

IEEE Asian Test Symposium 107 - 112 2012年11月

On Pinpoint Capture Power Management in At-Speed Scan Test Generation 査読有り国際誌

X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE International Test Conference Paper 6.1 2012年11月

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang

ACM Transactions on Design Automation of Electronic Systems 17 ( 4 ) Article No. 48 2012年10月

A Transition Isolation Scan Cell Design for Low Shift and Capture Power 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop 2012年07月

Power-Aware Testing: The Next Stage 招待有り査読有り国際誌

X. Wen

IEEE European Test Symposium Invited Talk 2012年05月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

France Annecy 2012年05月28日 - 2012年06月01日

Complex power management circuitry in low-power designs and the excessive gap between functional power and test power have made power-aware testing (DFT and test generation) a must. Although significant progress has been made in the past decade, more is still needed in order to achieve test power safety while maximizing test quality and minimizing test cost. This paper highlights the needs for moving to the next-stage of power-aware testing, primarily characterized by a shift of focus from global test power reduction to pinpoint test power management. © 2012 IEEE.

DOI： 10.1109/ETS.2012.6233000

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84864686941&origin=inward

A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits 査読有り国際誌

K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara

IEEE VLSI Test Symposium 197 - 202 2012年04月

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns 査読有り国際誌

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

ASP Journal of Lower Power Electronics 8 ( 2 ) 248 - 258 2012年04月

Fault Detection with Optimum March Test Algorithm 査読有り国際誌

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE International Conference on Intelligent Systems, Modeling and Simulation Paper S8 2012年02月

Testing static single cell faults using static and dynamic data background 査読有り国際誌

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE Student Conference on Research and Development 1 - 6 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Malaysia Cyberjaya 2011年12月19日 - 2011年12月20日

This work proposes a bit-adjacent Data Background (DB) management scheme to improve fault coverage of March algorithms while simultaneously maintaining the shortest test cycle. Both static and dynamic DB transitions are used in order to detect Deceptive Read Destructive Faults (DRDFs) and Write Disturb Faults (WDFs) that are not detected by previous algorithms. A conventional March Test Algorithm can be modified by using the DB management scheme to form a new March Test Algorithm (referred to as Mod March Test Algorithm), e.g., MATS++(6N) becoming Mod MATS++(6N). This paper shows that Mod March SR (14N) and Mod March CL (12N) can detect DRDFs and WDFs while the corresponding conventional algorithms cannot. It is also shown that Mod March CL(12N) and Mod March SR(14N) with DB management can detect all Static Single Cell Faults based on the Bit-Oriented-Memories (BOM) test method. Comparisons on test cycle time for Mod March SR, March SR, and March SS in the context of memory Built-In-Self-Test (BIST) are also presented. From the simulation result, it shows that by including Data Backgrounds (DBs) management in Bit-Oriented Memories (BOM), the cycle test time is the same after a given multiple of DBs in the test algorithm. © 2011 IEEE.

DOI： 10.1109/SCOReD.2011.6148694

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84857880363&origin=inward

Additional Path Delay Fault Detection with Adaptive Test Data 査読有り国際誌

K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing 31 - 34 2011年11月

Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling 査読有り国際誌

K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard

IEEE Asian Test Symposium 90 - 95 2011年11月

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