研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 161 - 180 件目／全件表示 >>

On Pinpoint Capture Power Management in At-Speed Scan Test Generation 査読有り国際誌

X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang

IEEE International Test Conference Paper 6.1 2012年11月

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang

ACM Transactions on Design Automation of Electronic Systems 17 ( 4 ) Article No. 48 2012年10月

A Transition Isolation Scan Cell Design for Low Shift and Capture Power 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

VLSI Test Technology Workshop 2012年07月

Power-Aware Testing: The Next Stage 招待有り査読有り国際誌

X. Wen

IEEE European Test Symposium Invited Talk 2012年05月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

France Annecy 2012年05月28日 - 2012年06月01日

Complex power management circuitry in low-power designs and the excessive gap between functional power and test power have made power-aware testing (DFT and test generation) a must. Although significant progress has been made in the past decade, more is still needed in order to achieve test power safety while maximizing test quality and minimizing test cost. This paper highlights the needs for moving to the next-stage of power-aware testing, primarily characterized by a shift of focus from global test power reduction to pinpoint test power management. © 2012 IEEE.

DOI： 10.1109/ETS.2012.6233000

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84864686941&origin=inward

A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits 査読有り国際誌

K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara

IEEE VLSI Test Symposium 197 - 202 2012年04月

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns 査読有り国際誌

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

ASP Journal of Lower Power Electronics 8 ( 2 ) 248 - 258 2012年04月

Fault Detection with Optimum March Test Algorithm 査読有り国際誌

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE International Conference on Intelligent Systems, Modeling and Simulation Paper S8 2012年02月

Testing static single cell faults using static and dynamic data background 査読有り国際誌

N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen

IEEE Student Conference on Research and Development 1 - 6 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Malaysia Cyberjaya 2011年12月19日 - 2011年12月20日

This work proposes a bit-adjacent Data Background (DB) management scheme to improve fault coverage of March algorithms while simultaneously maintaining the shortest test cycle. Both static and dynamic DB transitions are used in order to detect Deceptive Read Destructive Faults (DRDFs) and Write Disturb Faults (WDFs) that are not detected by previous algorithms. A conventional March Test Algorithm can be modified by using the DB management scheme to form a new March Test Algorithm (referred to as Mod March Test Algorithm), e.g., MATS++(6N) becoming Mod MATS++(6N). This paper shows that Mod March SR (14N) and Mod March CL (12N) can detect DRDFs and WDFs while the corresponding conventional algorithms cannot. It is also shown that Mod March CL(12N) and Mod March SR(14N) with DB management can detect all Static Single Cell Faults based on the Bit-Oriented-Memories (BOM) test method. Comparisons on test cycle time for Mod March SR, March SR, and March SS in the context of memory Built-In-Self-Test (BIST) are also presented. From the simulation result, it shows that by including Data Backgrounds (DBs) management in Bit-Oriented Memories (BOM), the cycle test time is the same after a given multiple of DBs in the test algorithm. © 2011 IEEE.

DOI： 10.1109/SCOReD.2011.6148694

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84857880363&origin=inward

Additional Path Delay Fault Detection with Adaptive Test Data 査読有り国際誌

K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing 31 - 34 2011年11月

Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling 査読有り国際誌

K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard

IEEE Asian Test Symposium 90 - 95 2011年11月

Power-Aware Test Pattern Generation for At-Speed LOS Testing 査読有り国際誌

A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase, X. Wen

IEEE Asian Test Symposium 506 - 510 2011年11月

Efficient BDD-based Fault Simulation in Presence of Unknown Values 査読有り国際誌

M. A. Kochte, S. Kundu, K. Miyase, X. Wen, H.-J. Wunderlich

IEEE Asian Test Symposium 383 - 388 2011年11月

Towards the Next Generation of Low-Power Test Technologies 査読有り国際誌

X. Wen

IEEE International Conference on ASIC Paper 1E-1 2011年10月

Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing 査読有り国際誌

L.-T. Wang, N. A. Touba, M. S. Hsiao, J.-L. Huang, C.-M. Li, S. Wu, X. Wen, M. Bhattarai, F. Li, Z. Jiang

IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits Paper 5.4 2011年09月

A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE International Test Conference Paper 12.1 2011年09月

Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

IEEE International Test Conference Paper 2.3 2011年09月

SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures 査読有り国際誌

M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enokimoto, H.-J. Wunderlich

IEEE International Symposium on Low Power Electronics and Design 33 - 38 2011年08月

低消費電力LSIのための低消費電力テスト技術招待有り査読有り

温暁青

情報・システムソサイエティ誌 ( 電子情報通信学会　情報・システムソサイエティ ) 16 ( 2 ) 10 - 11 2011年08月

VLSI Testing and Test Power 査読有り国際誌

X. Wen

Workshop on Low Power System on Chip Paper 4.1 2011年07月

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing 査読有り国際誌

K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara

IEICE Transactions on Information and Systems E94-D ( 6 ) 1216 - 1226 2011年06月

　前のページ - 次のページ　

<温 暁青>

論文 - 温 暁青

<温　暁青>

論文 - 温　暁青