研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 161 - 180 件目／全件表示 >>

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications 査読有り

Yan A., Wu Z., Zhou J., Hu Y., Chen Y., Ying Z., Wen X., Girard P.

Proceedings of the Asian Test Symposium 2019-December 55 - 60 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The Aggressive technology scaling makes modern advanced SRAMs more and more sensitive to soft errors that include single-node upsets (SNUs) and double-node upsets (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs. The cell mainly consists of six cross-coupled input-split inverters, constructing a large error-interceptive feedback loop to robustly retain stored values. Since the cell has many redundant storage nodes, the cell achieves the following robustness: (1) the cell can self-recover from all possible SNU; (2) the cell can self-recover from partial DNUs; (3) the cell can avoid the occurrence of other DNUs due to node-separation. Simulation results validate the excellent robustness of the proposed cell. Moreover, compared with the state-of-the-art typical existing hardened cells, the proposed cell achieves an approximate 61% read access time as well as 12% write access time reduction at the costs of 47% power dissipation as well as 44% silicon area on average.

DOI： 10.1109/ATS47505.2019.00006

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Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications 査読有り

Yan A., Wu Z., Lu L., Chen Z., Song J., Ying Z., Girard P., Wen X.

Proceedings of the Asian Test Symposium 2019-December 43 - 48 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.

DOI： 10.1109/ATS47505.2019.000-2

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Targeted partial-shift for mitigating shift switching activity hot-spots during scan test 査読有り

Holst S., Shi S., Wen X.

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2019-December 124 - 129 2019年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Shifting scan chains during testing causes high switching activity in the combinational logic. Excessive shift switching activity can give rise to severe, localized IR-drop that may invalidate the test by corrupting the contents of scan flip-flops or inducing excessive shift clock skew. In this work, we propose new methods to (1) quickly analyze all shift cycles of a given scan design and a test set for potential shift switching activity hot-spots and to (2) avoid them by targeted partial shifting of the scan chains. The results on ITC'99 benchmark circuits show the computational feasibility of the analysis and demonstrate the effectiveness of targeted partial-shift for mitigating test data corruption risk with minimal impact on test time.

DOI： 10.1109/PRDC47002.2019.00042

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Variation-aware small delay fault diagnosis on compressed test responses 査読有り

Holst S., Schneider E., Kochte M.A., Wen X., Wunderlich H.J.

Proceedings - International Test Conference 2019-November 2019年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two main challenges: (1) production test responses are usually highly compressed reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compressed test responses and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compressed test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

DOI： 10.1109/ITC44170.2019.9000143

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A fault-tolerant MPSoC for CubeSats 査読有り国際誌

Fuchs C., Chou P., Wen X., Murillo N., Furano G., Holst S., Tavoularis A., Lu S., Plaat A., Marinis K.

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 2019年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 W of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.

DOI： 10.1109/DFT.2019.8875417

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A static method for analyzing hotspot distribution on the LSI 査読有り

Miyase K., Kawano Y., Lu S., Wen X., Kajihara S.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 73 - 78 2019年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Performance degradation caused by high IR-drop in normal functional mode of LSI can be avoided by improving the power supply network in the layout design phase. However, while IR-drop increases much more in test mode than in normal functional mode, excessive IR-drop in test mode is not appropriately considered in the layout design phase. Excessive IR-drop in test mode causes over-testing, which wrongly determines a fault free LSI in normal functional mode to be faulty. In this work, we propose a method for analyzing high IR-drop areas (hotspot distribution), which is necessary to effectively and efficiently reduce excessive IR-drop.

DOI： 10.1109/ITC-Asia.2019.00026

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A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells 査読有り国際誌

Song Z., Yan A., Cui J., Chen Z., Li X., Wen X., Lai C., Huang Z., Liang H.

Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 139 - 144 2019年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81% for the proposed latch compared with the only existing SETU hardened latch.

DOI： 10.1109/ITC-Asia.2019.00037

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Power-Aware Testing for Low-Power VLSI Circuits 招待有り査読有り国際誌

X. Wen

15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits Paper S12-1 2019年06月

Small Delay Fault Diagnosis with Compacted Responses 査読有り国際誌

S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich

Poster at ACM Design Automation Conf. 2019年06月

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications 査読有り国際誌

Yan A., Hu Y., Song J., Wen X.

Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 1679 - 1684 2019年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 EDAA. This paper presents a single-event double-upset (SEDU) self-recoverable and single-event transient (SET) pulse filterable latch design for low power applications in 22nm CMOS technology. The latch mainly consists of eight mutually feeding back C-elements and a Schmitt trigger. Simulation results have demonstrated both the SEDU self-recoverability and SET pulse filterability for the latch using redundant silicon area. Using clock gating technology, the latch saves about 54.85% power dissipation on average compared with the up-to-date SEDU self-recoverable latch designs which are not SET pulse filterable at all.

DOI： 10.23919/DATE.2019.8714841

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STAHL: A novel scan-test-aware hardened latch design 査読有り国際誌

Ma R., Holst S., Wen X., Yan A., Xu H.

Proceedings of the European Test Workshop 2019-May 2019年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. As modern technology nodes become more susceptible to soft errors, many radiation hardened latch designs have been proposed. However, redundant circuitry used to tolerate soft errors in such hardened latches also reduces the test coverage of cell-internal manufacturing defects. To avoid potential test escapes that lead to soft error vulner-ability and reliability issues, this paper proposes a novel Scan-Test-Aware Hardened Latch (STAHL). Simulation results show that STAHL has superior defect coverage compared to previous hardened latches while maintaining full radiation hardening in function mode.

DOI： 10.1109/ETS.2019.8791544

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Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout 査読有り国際誌

Yan A., Wu Z., Guo J., Song J., Wen X.

IEEE Transactions on Reliability 68 ( 1 ) 354 - 363 2019年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2018 IEEE. This paper presents two novel memory cell designs that can completely tolerate double-node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant storage nodes, the cell achieves the following robustness: 1) In the case of 1 being stored, the cell can self-recover from any double-node upset (DNU) as well as any single node upset (SNU); 2) in the case of 0 being stored, the cell can self-recover from any double-adjacent-node upset (DANU), partial double-separated-node upset (DSNU) as well as any SNU. Any other DSNU can be tolerated by the cell due to the use of the layout approach. Second, a layout-independent cell is proposed that can self-recover from any DNU as well as any SNU. Simulation results validate the robustness of the proposed cell designs. Furthermore, compared with typical existing radiation hardened memory cells, the proposed layout-dependent cell saves 55.60% read access time and 33.76% write access time at the costs of 4.28% power dissipation and 39.01% silicon area on average, still low compared with layout-independent cell designs.

DOI： 10.1109/TR.2018.2876243

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Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory 査読有り国際誌

Alioto M., Abadir M.S., Arslan T., Boon C.C., Burg A., Chang C.H., Chang M.F., Chang Y.W., Chen P., Corsonello P., Crovetti P., Dosho S., Drechsler R., Elfadel I.A.M., Han R., Hashimoto M., Heng C.H., Heo D., Ho T.Y., Homayoun H., Hwang Y.S., Joshi A., Joshi R.V., Karnik T., Kim C., Kim T.H.T., Kulkarni J., Kursun V., Lee Y., Li H.H., Li H., Mishra P., Mohammad B., Kermani M.M., Nagata M., Nii K., Pande P.P., Paul B.C., Pavlidis V.F., De Gyvez J.P., Savidis I., Schaumont P., Sebastiano F., Sengupta A., Seok M., Stan M.R., Tehranipoor M.M., Todri-Sanial A., Verhelst M., Vignoli V., Wen X., Xu J., Zhang W., Zhang Z., Zhou J., Zwolinski M., Weber S.

IEEE Transactions on Very Large Scale Integration VLSI Systems 27 ( 2 ) 253 - 280 2019年02月

記述言語：英語掲載種別：記事・総説・解説・論説等（学術雑誌）

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades [1] (see Fig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown in Fig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade [2], [3]. At the same time, the energy per task has been decreasing at 10-100 X/decade, as shown in Fig. 2, for several systems and system-on-chip subsystems [4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit [5].

DOI： 10.1109/TVLSI.2018.2886389

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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults 査読有り国際誌

Ni T., Yao Y., Chang H., Lu L., Liang H., Yan A., Huang Z., Wen X.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 ( 10 ) 2938 - 2951 2019年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

IEEE Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the FTSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3D-ICs. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based RTSV architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this paper, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.

DOI： 10.1109/TCAD.2019.2946243

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Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets 査読有り

Yan A., Zhou J., Hu Y., Cui J., Huang Z., Girard P., Wen X.

IEEE Access 7 176188 - 176196 2019年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

DOI： 10.1109/ACCESS.2019.2958109

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85077130774&origin=inward

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing 査読有り国際誌

Zhang Y., Wen X., Holst S., Miyase K., Kajihara S., Wunderlich H., Qian J.

Proceedings of the Asian Test Symposium 2018-October 149 - 154 2018年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. High scan shift power often leads to excessive heat as well as shift timing failures. Partial shift (shifting a subset of scan chains at a time) is a widely adopted approach for avoiding excessive heat by reducing global switching activity, we show for the first time that it may actually cause excessive IR-drop on some clock buffers and worsen shift clock skews, thus increasing the risk of shift timing failures. This paper addresses this problem with an innovative method, namely Clock-Skew-Aware Scan Chain Grouping (CSA-SCG). CSA-SCG properly groups scan chains to be shifted simultaneously so as to reduce the imbalance of switching activity around the clock paths for neighboring scan flip-flops in scan chains. Experiments on large ITC'99 benchmark circuits demonstrate the effectiveness of CSA-SCG for reducing scan shift clock skews to lower the risk of shift timing failures in partial shift.

DOI： 10.1109/ATS.2018.00037

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85060029684&origin=inward

Message from the Technical Program Co-Chairs 招待有り査読有り国際誌

Li H., Wen X., Huang Z.

Proceedings of the Asian Test Symposium 2018-October 2018年12月

Foreword 査読有り国際誌

Li X., Li H., Cheng K.T.T., Wen X.

Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018 2018年09月

The impact of production defects on the soft-error tolerance of hardened latches 査読有り国際誌

Holst S., Ma R., Wen X.

Proceedings of the European Test Workshop 2018-May 1 - 6 2018年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces the test coverage of cell-internal production defects. Moreover, the test escapes reduce the soft-error tolerance of the defective latches. This work introduces a new soft-error vulnerability metric called Post Test Vulnerability Factor that correctly measures the added vulnerability to transiant frults such as particle strikes caused by undiscovered production defects within hardened latches.

DOI： 10.1109/ETS.2018.8400694

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85050003309&origin=inward

Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

Proceedings of the 27th International Workshop on Logic and Synthesis 124 - 131 2018年06月

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