研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 241 - 260 件目／全件表示 >>

Power-Aware Test Pattern Generation for At-Speed LOS Testing 査読有り国際誌

A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase, X. Wen

IEEE Asian Test Symposium 506 - 510 2011年11月

Efficient BDD-based Fault Simulation in Presence of Unknown Values 査読有り国際誌

M. A. Kochte, S. Kundu, K. Miyase, X. Wen, H.-J. Wunderlich

IEEE Asian Test Symposium 383 - 388 2011年11月

Towards the Next Generation of Low-Power Test Technologies 査読有り国際誌

X. Wen

IEEE International Conference on ASIC Paper 1E-1 2011年10月

Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing 査読有り国際誌

L.-T. Wang, N. A. Touba, M. S. Hsiao, J.-L. Huang, C.-M. Li, S. Wu, X. Wen, M. Bhattarai, F. Li, Z. Jiang

IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits Paper 5.4 2011年09月

A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang

IEEE International Test Conference Paper 12.1 2011年09月

Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing 査読有り国際誌

Y.-T. Lin, J.-L. Huang, X. Wen

IEEE International Test Conference Paper 2.3 2011年09月

SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures 査読有り国際誌

M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enokimoto, H.-J. Wunderlich

IEEE International Symposium on Low Power Electronics and Design 33 - 38 2011年08月

低消費電力LSIのための低消費電力テスト技術招待有り査読有り

温暁青

情報・システムソサイエティ誌 ( 電子情報通信学会　情報・システムソサイエティ ) 16 ( 2 ) 10 - 11 2011年08月

VLSI Testing and Test Power 査読有り国際誌

X. Wen

Workshop on Low Power System on Chip Paper 4.1 2011年07月

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing 査読有り国際誌

K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara

IEICE Transactions on Information and Systems E94-D ( 6 ) 1216 - 1226 2011年06月

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns 査読有り国際誌

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011年05月

Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011年05月

Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing 査読有り国際誌

X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, M. Tehranipoor

IEEE VLSI Test Symposium 166 - 171 2011年05月

Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era 1 - 6 2011年04月

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara

IEICE Transactions on Information and Systems E94-D ( 4 ) 833 - 840 2011年04月

Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation 査読有り国際誌

K. Miyase, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

Design, Automation and Test in Europe 895 - 898 2011年03月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

France Grenoble 2011年03月14日 - 2011年03月18日

Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. This paper presents a novel metric, called the TTR (Transition-Time-Relation-based) metric, which takes transition time relations into consideration in capture-safety checking. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation. © 2011 EDAA.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79957551358&origin=inward

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

S. Wu,L.-T. Wang,X. Wen,Z. Jiang,M. Hsiao,W.-B. Jone,L. Tan,Y. Zhang,Y. Hu,C.-M. Li,Member,J.-L. Huang,L. Yu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30 ( 3 ) 455 - 463 2011年03月

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme 査読有り国際誌

K. Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara

IEEE Workshop on RTL and High Level Testing 125 - 129 2010年12月

Hybrid Memory Built-In Self-Test Architecture for Multi-port Static RAMs 査読有り国際誌

L. Yu, J. Hung, B. Sheu, B. Huynh, L. Nguyen, S. Wu, L.-T. Wang, X. Wen

IEEE Int Symposium on Defect and Fault Tolerance in VLSI Systems 331 - 339 2010年11月

Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver 査読有り国際誌

K. Miyase,M. A. Kochte,X. Wen,S. Kajihara,H.-J. Wunderlich

IEEE Workshop on Defect and Date Driven Testing 4 Pages 2010年11月

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