研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示339 件中 181 - 200 件目／全件表示 >>

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application 査読有り国際誌

A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

IEEE Transactions on Circuits and Systems II: Express Briefs 66 ( 2 ) 287 - 291 Early Access 2018年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.

DOI： 10.1109/TCSII.2018.2849028

Scopus

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A Method to Detect Bit Flips in a Soft-Error Resilient TCAM 査読有り国際誌

I. Syafalni, T. Sasao, X. Wen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 ( 6 ) 1185 - 1196 2018年06月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE. Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors k. KX-TCAM corrects up to k -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers.

DOI： 10.1109/TCAD.2017.2748019

Scopus

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The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches 査読有り国際誌

S. Holst, R. Ma, X. Wen

Proceedings of IEEE European Test Symposium Paper 7A-1 2018年05月

Design Automation for Legacy Circuits 査読有り国際誌

I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies 174 - 179 2018年03月

Locating Hot Spot with Justification Techniques in a Layout Design 査読有り国際誌

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

Proceedings of IEEE Workshop on RTL and High Level Testing Paper S1.2 2017年11月

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption 査読有り国際誌

Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian

Proceedings of the Asian Test Symposium 140 - 145 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Taiwan Taipei 2017年11月27日 - 2017年11月30日

© 2017 IEEE. Loading and unloading test patterns during scan testing causes many scan flip-flops to trigger simultaneously. This instantaneous switching activity during shift in turn may cause excessive IR-drop that can disrupt the states of some scan flip-flops and corrupt test stimuli or responses. A common design technique to even out these instantaneous power surges is to design multiple scan chains and shift only a group of the scan chains at a same time. This paper introduces a novel algorithm to optimally group scan chains so as to minimize the probability of test data corruption caused by excessive instantaneous IR-drop on scan flip-flops. The experiments show optimal results on all large ITC'99 benchmark circuits.

DOI： 10.1109/ATS.2017.37

Kyutacar

Scopus

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Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors 査読有り国際誌

S. Holst, E. Schneider, H. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen

Proceedings - International Test Conference 2017-December 1 - 8 Paper 3.4 2017年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

USA Fort Warth 2017年10月29日 - 2017年11月03日

© 2017 IEEE. Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases of test data corruption are mitigated in a non-intrusive way by selective test data manipulation and masking of affected responses. Evaluation results show the computational feasibility of our method for large benchmark circuits, and demonstrate that a few targeted pattern changes provide large potential gains in shift safety and test time with negligible cost in fault coverage.

DOI： 10.1109/TEST.2017.8242055

Scopus

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A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips 査読有り国際誌

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Transactions on Emerging Topics in Computing 8 ( 3 ) 591 - 601 Early Access 2017年10月

記述言語：英語掲載種別：研究論文（学術雑誌）

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

DOI： 10.1109/TETC.2017.2767070

Kyutacar

Scopus

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Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs 査読有り国際誌

T. Ni, M. Nie, H. Liang, J. Bian, X. Xu, X. Fang, Z. Huang, X. Wen

IEICE Electronics Express 18 ( 14 ) Letter 20170590 2017年10月

GPU-Accelerated Simulation of Small Delay Faults 査読有り国際誌

E. Schneider, M. Kochte, S. Holst, X. Wen, H. Wunderlich

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 ( 5 ) 829 - 841 2017年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 1982-2012 IEEE.Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs towards even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this work, we present a method for fast and waveformaccurate simulation of small delay faults on graphics processing units (GPUs) with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.

DOI： 10.1109/TCAD.2016.2598560

Scopus

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On Optimal Power-Aware Path Sensitization 査読有り国際誌

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian

Workshop of Test and Reliability for Circuits and Systems 2017年03月

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudo-Random Test Pattern Generation and Reseeding 査読有り国際誌

D. Xiang., X. Wen, L.-T. Wang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 ( 3 ) 942 - 953 2017年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach.

DOI： 10.1109/TVLSI.2016.2606248

Scopus

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Vernier ring based pre-bond through silicon vias test in 3D ICs 査読有り国際誌

Ni T., Nie M., Liang H., Bian J., Xu X., Fang X., Huang Z., Wen X.

IEICE Electronics Express ( 一般社団法人電子情報通信学会 ) 14 ( 18 ) 20170590 - 20170590 2017年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.

DOI： 10.1587/elex.14.20170590

Scopus

CiNii Article

CiNii Research

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Logic-Path-and-Clock-Path-Aware at-Speed Scan Test Generation 査読有り国際誌

F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara

International Symposium on Applied Engineering and Sciences 2016年12月

Logic-path-and-clock-path-aware at-speed scan test generation 査読有り国際誌

Li F., Wen X., Miyase K., Holst S., Kajihara S.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人電子情報通信学会 ) E99A ( 12 ) 2310 - 2319 2016年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power- safety without significant test vector count inflation and test quality loss.

DOI： 10.1587/transfun.E99.A.2310

Scopus

CiNii Article

CiNii Research

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A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST 査読有り国際誌

T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen

IEEE Asian Test Symposium 203 - 208 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.

DOI： 10.1109/ATS.2016.59

Kyutacar

Scopus

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Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test 査読有り国際誌

S. Eggersglub, S. Holst, D. Tille, K. Miyase, X. Wen

IEEE Asian Test Symposium 173 - 178 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

Launch-Switching-Activity (LSA) is a serious problem during at-speed testing of integrated circuits, since localized LSA may lead to severe IR-drop and thus failures. The excessive LSA is conventionally mitigated by reducing the switching activity through special low-power test generation techniques, typically resulting in severe test pattern inflation and high test costs. This work introduces a novel concept of Low-Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power (HCP) regions. LCP-TPs also help in retaining high test compaction capability. An optimization- SAT based procedure is proposed to compute a small set of optimal LCP-TP locations for compact at-speed test sets with effective capture power reduction. Experimental results clearly demonstrate the advantages of LCP-TP insertion.

DOI： 10.1109/ATS.2016.41

Scopus

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On Optimal Power-Aware Path Sensitization 査読有り国際誌

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian

IEEE Asian Test Symposium 179 - 184 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

Detailed knowledge of a circuit's timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit's inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls the switching activity in the circuit region surrounding the path. The procedure can maximize or minimize switching activity, or set it to a user-specified value. We study the accuracy-vs.-efficiency trade-offs for a hierarchy of timing models, from coarse zero-delay assumption to a waveformaccurate approach with sub-cycle resolution. For the first time, we present a MaxSAT formulation which guarantees maximization or minimization of switching activity, stemming from transitions and from glitches, simultaneously with path sensitization. We validate the quality of the generated test patterns using a mixed-mode IR-drop-aware timing simulator.

DOI： 10.1109/ATS.2016.63

Scopus

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Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths during At-Speed Scan Test 査読有り国際誌

S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H. Wunderlich, M. Kochte

IEEE Asian Test Symposium 19 - 24 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Hiroshima 2016年11月21日 - 2016年11月24日

IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations.

DOI： 10.1109/ATS.2016.49

Scopus

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Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures 査読有り国際誌

T. Chen, D. Shen, X. Yi, H. Liang, X. Wen

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E99D ( 11 ) 2672 - 2681 2016年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2016 The Institute of Electronics, Information and Communication Engineers.Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

DOI： 10.1587/transinf.2015EDP7289

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論文 - 温　暁青