研究者詳細 - 温　暁青

論文 - 温　暁青

分割表示269 件中 181 - 200 件目／全件表示 >>

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns 査読有り国際誌

H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, X. Wen

IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011年05月

Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Workshop on Impact of Low-Power design on Test and Reliability 4 Pages 2011年05月

Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing 査読有り国際誌

X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, M. Tehranipoor

IEEE VLSI Test Symposium 166 - 171 2011年05月

Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era 1 - 6 2011年04月

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing 査読有り国際誌

Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara

IEICE Transactions on Information and Systems E94-D ( 4 ) 833 - 840 2011年04月

Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation 査読有り国際誌

K. Miyase, X. Wen, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara

Design, Automation and Test in Europe 895 - 898 2011年03月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

France Grenoble 2011年03月14日 - 2011年03月18日

Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. This paper presents a novel metric, called the TTR (Transition-Time-Relation-based) metric, which takes transition time relations into consideration in capture-safety checking. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation. © 2011 EDAA.

Scopus

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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 査読有り国際誌

S. Wu,L.-T. Wang,X. Wen,Z. Jiang,M. Hsiao,W.-B. Jone,L. Tan,Y. Zhang,Y. Hu,C.-M. Li,Member,J.-L. Huang,L. Yu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30 ( 3 ) 455 - 463 2011年03月

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme 査読有り国際誌

K. Miyase,F. Wu,L. Dilillo,A. Bosio,P. Girard,X. Wen,S. Kajihara

IEEE Workshop on RTL and High Level Testing 125 - 129 2010年12月

Hybrid Memory Built-In Self-Test Architecture for Multi-port Static RAMs 査読有り国際誌

L. Yu, J. Hung, B. Sheu, B. Huynh, L. Nguyen, S. Wu, L.-T. Wang, X. Wen

IEEE Int Symposium on Defect and Fault Tolerance in VLSI Systems 331 - 339 2010年11月

Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver 査読有り国際誌

K. Miyase,M. A. Kochte,X. Wen,S. Kajihara,H.-J. Wunderlich

IEEE Workshop on Defect and Date Driven Testing 4 Pages 2010年11月

Is Test Power Reduction Through X-Filling Good Enough? 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

IEEE International Test Conference 805 - 805 Poster 2010年11月

On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test 査読有り国際誌

S. Kajihara, M. Matsuzono, H. Yamaguchi, Y. Sato, K. Miyase, X. Wen

10th International Symposium on Communications and Information Technologies 723 - 726 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Tokyo 2010年10月26日 - 2010年10月29日

This paper proposes a test compaction method for full scan circuits based on multiple capture clock cycles. The multiple cycle test applies more than one capture clock signals for a circuit after scan shift operation, while the capture clock cycle of the conventional scan test is one. Because every captured value at scan flip-flops is used for fault detection, the opportunity of fault detection for each fault increases. As a result, the number of test vectors would be decreased compared with the single cycle mode. Such a test compaction method would be useful in field test that requires less test data so as to store them on-chip. Experimental results show that the proposed method is effective for test compaction. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665084

Scopus

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Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains 査読有り国際誌

S. Wu,L.-T. Wang,L. Yu,H. Furukawa,X. Wen,W.-B. Jone,N. A. Touba,F. Zhao,J. Liu,H.-J. Chao,F. Li,Z. Jiang

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 358 - 366 2010年10月

Case Studies on Transition Fault Test Generation for At-Speed Scan Testing 査読有り国際誌

N. A. Zakariz, E. V. Bautista, S. M. Jusoh, W. F. Lee, X. Wen

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 180 - 188 2010年10月

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes 査読有り国際誌

F. Wu,L. Dilillo,A. Bosio,P. Girard,S. Pravossoudovitch,A. Virazel,M. Tehranipoor,X. Wen,N. Ahmed

ASP Journal of Lower Power Electronics 6 ( 2 ) 359 - 374 2010年08月

On Delay Test Quality for Test Cubes 査読有り国際誌

S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen

IPSJ Transactions on System LSI Design Methodology 3 283 - 291 2010年08月

A Study of Capture-Safe Test Generation Flow for At-Speed Testing 査読有り国際誌

K. Miyase, X. Wen, S. Kajihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja

IEICE Transactions on Information and Systems E93-A ( 7 ) 1309 - 1318 2010年07月

On Estimation of NBTI-Induced Delay Degradation 査読有り国際誌

M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura

IEEE European Test Symposium 107 - 111 2010年05月

Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes 査読有り国際誌

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, X. Wen

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 376 - 381 2010年04月

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme 査読有り国際誌

K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L. Wang, M. Tehranipoor

IEICE Transactions on Information and Systems E93-D ( 1 ) 2 - 9 2010年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock- Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design. Copyright © 2010 The Institute of Electronics.

Kyutacar

Scopus

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