研究者詳細 - 森江　隆

論文 - 森江　隆

分割表示 >> ／全件表示315 件中 1 - 315 件目

Robustness of Spiking Neural Networks based on Time-To-First-Spike Encoding against Adversarial Attacks 査読有り国際誌

Nomura O., Sakemi Y., Hosomi T., Morie T.

IEEE Transactions on Circuits and Systems II: Express Briefs 2022年06月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

Spiking neural networks (SNNs) more closely mimic the human brain than artificial neural networks (ANNs). For SNNs, time-to-first-spike (TTFS) encoding, which represents the output values of neurons based on the timing of a single spike, has been proposed as a promising model to reduce power consumption. Adversarial attacks that can lead ANNs to misrecognize images have been reported in many studies. However, the characteristics of TTFS-based SNNs trained using a backpropagation algorithm against adversarial attacks have not yet been clarified. In particular, the dependence of the robustness against adversarial attacks on spike timings has not been investigated. In this study, we investigated the robustness of SNNs against adversarial attacks and compared it with that of an ANN. We found that SNNs trained with the appropriate temporal penalty settings are more robust against adversarial images than ANNs.

DOI： 10.1109/TCSII.2022.3184313

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85133755727&origin=inward

A Memory-Based Entorhinal-Hippocampal Model and its FPGA Implementation by On-Chip RAMs 査読有り国際誌

I. Kawashima, K. Tateno, T. Morie, H. Tamukoh

Int. Symp. on Circuits and Systems (ISCAS 2022) ( IEEE ) 2022年05月

A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing 査読有り国際誌

Y. Sakemi, K. Morino, T. Morie, T. Hosomi, K. Aihara

Int. Symp. on Circuits and Systems (ISCAS 2022) ( IEEE ) 2022年05月

A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing 査読有り国際誌

Nakagawa H., Tateno K., Takada K., Morie T.

IEEE Access 10 43003 - 43012 2022年04月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

To solve a navigation task based on experiences, we need a mechanism to associate places with objects and recall them along the course of action. In a reward-oriented task, if the route to a reward location is simulated in mind after experiencing it once, it might be possible that the reward is gained efficiently. One way to solve this is to incorporate a biologically plausible mechanism. In this study, we propose a neural network that stores a sequence of events associated with a reward. The proposed network recalls the reward location by tracing them in its mind in order. We simulated a virtual mouse that explores a figure-eight maze and recalls the route to the reward location. During the learning period, a sequence of events related to firing along a passage was temporarily stored in the heteroassociative network, and the sequence of events is consolidated in the synaptic weight matrix when a reward is fed. For retrieval, an impetus input internally generates the sequential activation of conjunctive cue-place cells toward the reward location. In the figure-eight maze task, the location of the reward was estimated by mind travel, irrespective of whether the reward is in the counterclockwise or distant clockwise route. The mechanism of efficiently reaching the goal by mind travel in the brain based on experiences is beneficial for mobile service robots that perform autonomous navigation.

DOI： 10.1109/ACCESS.2022.3168715

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85129211400&origin=inward

An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing 査読有り国際誌

Kawashima I., Katori Y., Morie T., Tamukoh H.

International Conference on Field-Programmable Technology (ICFPT 2021) 2021年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In our work, a new area-efficient multiply-accumulation scheme for time-domain neural processing named differential multiply-accumulation is proposed. Our new scheme reduces hardware resources utilization of multiply-accumulation with suppressing the increasing computational time resulting from the time-multiplexing. As a result, 2,048 neurons of fully connected CBM and RC-CBM were synthesized for a single field-programmable gate array (FPGA).

DOI： 10.1109/ICFPT52863.2021.9609809

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85123208884&origin=inward

Brain-inspired neural network navigation system with hippocampus, prefrontal cortex, and amygdala functions 査読有り国際誌

Mizutani A., Tanaka Y., Tamukoh H., Katori Y., Tateno K., Morie T.

International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2021) 2021年11月

担当区分：最終著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We propose a brain-inspired neural network model consisting of the hippocampus, prefrontal cortex, and amygdala models for a navigation system that acquires specific knowledge in home environments from few experiences. The proposed model was evaluated in a home environment using a robot simulator. In the experiment, the robot determines a path for navigation based on the knowledge acquired by the brain-inspired model.

DOI： 10.1109/ISPACS51563.2021.9651058

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85124147021&origin=inward

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design 査読有り国際誌

Sakemi Y., Morino K., Morie T., Aihara K.

IEEE Transactions on Neural Networks and Learning Systems ( IEEE ) 2021年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms but also energy-efficient computational models when implemented in very-large-scale integration (VLSI) circuits. In this article, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultrahigh energy efficiency can be achieved. We also propose several techniques to improve the performance on recognition tasks and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST and Fashion-MNIST datasets. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.

DOI： 10.1109/TNNLS.2021.3095068

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85111030237&origin=inward

An Energy-efficient Time-domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-width Modulation Approach 査読有り国際誌

Yamaguchi M., Iwamoto G., Nishimura Y., Tamukoh H., Morie T.

IEEE Access 2020年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

DOI： 10.1109/ACCESS.2020.3047619

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85099109848&origin=inward

An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots 査読有り国際誌

Tanaka Y., Morie T., Tamukoh H.

IEEE Access 8 212066 - 212078 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

This study develops an intelligent system for home service robots mimicking human brain function that can manage common knowledge applicable to any environment and local knowledge reflecting its specific environment. Deep learning is effective for acquiring common knowledge because the performance of deep learning relies on the amounts of training and big training data that can be accessed for such knowledge; however, deep learning is ineffective for acquiring local knowledge because no big training data for such knowledge exist. Thus, we propose a brain-inspired learning model and system for acquiring local knowledge using small training data. We focus on the amygdala because its classical fear conditioning is effective for training using small training data. We propose an amygdala-inspired classical conditioning model comprising multiple self-organizing maps (lateral nucleus) and a fully connected neural network (central nucleus), imitating the function and structure of the amygdala. The proposed model is applied to a task of a waiter robot in a restaurant, and the model can learn customers' preferences after only a few human-robot interactions. We accelerate the computation of the model and reduce its power consumption by proposing a hardware-oriented algorithm for the model and its digital hardware design and implement it in an XCZU9EG field programmable gate array. The hardware-oriented algorithm reduces the multiplication operations and exponential functions requiring huge hardware resources. The performance of the hardware operated at 150 MHz is 1,273 times faster than the software implementation on Arm Cortex-A53, and the power consumption of the chip is 5.009 W.

DOI： 10.1109/ACCESS.2020.3038161

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85097712435&origin=inward

FPGA implementation of hardware-oriented chaotic Boltzmann machines 査読有り国際誌

Kawashima I., Morie T., Tamukoh H.

IEEE Access 8 204360 - 204377 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

DOI： 10.1109/ACCESS.2020.3036882

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85102831540&origin=inward

A Time-domain Analog Weighted-sum Calculation Circuit Using Ferroelectric-gate Field-effect Transistors for Artificial Intelligence Processors 招待有り査読有り国際誌

M, Harada, M, Takahashi, S. Sakai, T. Morie

Japanese Journal of Applied Physics 59 ( 4 ) 040604-1 - 040604-12 2020年04月

A Chaotic Boltzmann Machine Working as a Reservoir and Its Analog VLSI Implementation 査読有り

Yamaguchi M., Katori Y., Kamimura D., Tamukoh H., Morie T.

Proceedings of the International Joint Conference on Neural Networks 2019-July 2019年07月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Reservoir computing is attracting great interest because of its high computing ability especially for time-series prediction, despite its simple structure and learning scheme. This paper proposes a reservoir computing hardware model using a chaotic Boltzmann machine (CBM) as the reservoir, which can achieve complex motion in a dynamical system on a high-dimensional hypercube. The CBM uses analog nonlinear dynamics, unlike the stochastic operation of the original Boltzmann machine model. To utilize CBMs as a reservoir, chaotic operation must be suppressed, and the echo state property should be satisfied. We modify the CBM model for simpler analog complementary metal-oxide-semiconductor very-large-scale integration (CMOS VLSI) implementation, and propose its use as a reservoir by adding an external reference clock signal. We then verify its proper operation by numerical simulation. We also refine the CMOS VLSI circuit design based on the proposed modified CBM model to improve power consumption and calculation precision.

DOI： 10.1109/IJCNN.2019.8852325

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85073242376&origin=inward

ニューロモルフィックシステムと物理デバイス招待有り査読有り

森江隆

応用物理 ( 公益社団法人応用物理学会 ) 88 ( 7 ) 481 - 485 2019年07月

担当区分：筆頭著者,　責任著者記述言語：日本語掲載種別：記事・総説・解説・論説等（学術雑誌）

本稿では，人工知能（AI）に関連して頻繁に聞く「ニューロモルフィックシステム」や「スパイキングニューロンモデル」について，その意味，歴史，現在の位置づけを紹介します．また，それらの実現へ向けてどのような処理モデルが提案され，どのようなデバイスが求められているかを解説します．AIに対して応用物理の材料・デバイス分野がどのように貢献できるのか，本稿がそれを考えるヒントになれば幸いです．

DOI： 10.11470/oubutsu.88.7_481

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007709468

Reservoir Computing Based on Dynamics of Pseudo-Billiard System in Hypercube 査読有り

Katori Y., Tamukoh H., Morie T.

Proceedings of the International Joint Conference on Neural Networks 2019-July 2019年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Reservoir computing (RC) is a framework for constructing recurrent neural networks with simple training rule and sparsely and randomly connected nonlinear units. The network (called reservoir) generates complex motion that can be used for many tasks including time series generation and prediction. We construct a reservoir based on the dynamics of the pseudo-billiard system that produce complex motion in a high-dimensional hypercube. In particular, we use the chaotic Boltzmann machine (CBM) whose units exhibit chaotic behavior in the hypercube. The units interact with each other in a time-domain manner through its binary state, and thus an efficient hardware implementation of the system is expected. In order to utilize the CBM as the reservoir, it is necessary to control its chaotic behavior for ensuring the echo state property of RC and establish encoding and decoding for input and output signal. For this purpose, we introduce a reference clock and analyze effects and properties of the reference input. We evaluate the proposed model on the time series generation tasks and show that the model works properly on a broad range of parameter values. Our approach presents a novel mechanism for time-domain information processing and a fundamental technology for a brain like artificial intelligence system.

DOI： 10.1109/IJCNN.2019.8852329

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85073235480&origin=inward

Live demonstration: A VLSI implementation of time-domain analog weighted-sum calculation model for intelligent processing on robots 査読有り国際誌

Yamaguchi M., Iwamoto G., Abe Y., Tanaka Y., Ishida Y., Tamukoh H., Morie T.

IEEE International Symposium on Circuits and Systems (ISCAS 2019) 2019-May 2019年05月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE This live demonstration presents a VLSI chip based on “Time-domain Analog Computing with Transient states (TACT)” approach for intelligent processing on robots. This TACT chip, fabricated using 250-nm CMOS technology, implements a time-domain analog weighted-sum calculation model with very high energy efficiency. We integrate the TACT chip into a robot via Robot Operating System (ROS) interfaces. A human tracking robot demonstration is performed by the TACT chip with energy efficiency of 300 TOPS/W.

DOI： 10.1109/ISCAS.2019.8702222

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85066803614&origin=inward

A CMOS Chaotic Boltzmann Machine Circuit and Three-neuron Network Operation 査読有り国際誌

M. Yamaguchi, H. Tamukoh, H. Suzuki, T. Morie

Proc. Int. Joint Conf. on Neural Networks (IJCNN 2017) 1218 - 1224 2017年06月

Silicon Nanodisk Array with a Fin Field-effect Transistor for Time-domain Weighted Sum Calculation toward Massively Parallel Spiking Neural Networks,, 査読有り国際誌

T. Tohara, H. Liang, H. Tanaka, M. Igarashi, S. Samukawa, K. Endo, Y. Takahashi, T. Morie

Applied Physics Express Vol. 9 ( No. 3 ) 034201 2016年02月

Parameterized Digital Hardware Design of Pulse-coupled Phase Oscillator Networks 査読有り国際誌

Y. Suedomi, H. Tamukoh, K. Matsuzaka, M. Tanaka, T. Morie

Neurocomputing 165 54 - 62 2015年10月

A PWM-mode Pixel-parallel Image Processing Circuit Performing Directional State-propagation and Its Application to Subjective Contour Generation 査読有り国際誌

Y. Kim, T. Morie

Circuits, Systems & Signal Processing 34 ( 2 ) 605 - 623 2015年02月

VLSI Implementation of a Coupled MRF Model Using Pulse-coupled Phase Oscillators 査読有り国際誌

K. Matsuzaka, H. Tanaka, S. Ohkubo, T. Morie

Electronics Letters 51 ( 1 ) 46 - 48 2015年01月

Single-electron Devices and Circuits Utilizing Stochastic Operation for Intelligent Information Processing 招待有り査読有り国際誌

T. Morie

Int. J. of Nanotechnology and Molecular Computation 1 ( 2 ) 1 - 28 2009年04月

A Subjective-Contour Generation LSI System with Expandable Pixel-Parallel Architecture for Vision Systems, 査読有り国際誌

T. Morie,Y. Kim

IEEE Int. Solid-State Circuits Conf. (ISSCC2009) 478 - 479 2009年02月

An efficient hardware-oriented dropout algorithm 査読有り国際誌

Yeoh Y.J., Morie T., Tamukoh H.

Neurocomputing 427 191 - 200 2021年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a hardware-oriented dropout algorithm, which is efficient for field programmable gate array (FPGA) implementation. In deep neural networks (DNNs), overfitting occurs when networks are overtrained and adapt too well to training data. Consequently, they fail in predicting unseen data used as test data. Dropout is a common technique that is often applied in DNNs to overcome this problem. In general, implementing such training algorithms of DNNs in embedded systems is difficult due to power and memory constraints. Training DNNs is power-, time-, and memory- intensive; however, embedded systems require low power consumption and real-time processing. An FPGA is suitable for embedded systems for its parallel processing characteristic and low operating power; however, due to its limited memory and different architecture, it is difficult to apply general neural network algorithms. Therefore, we propose a hardware-oriented dropout algorithm that can effectively utilize the characteristics of an FPGA with less memory required. Software program verification demonstrates that the performance of the proposed method is identical to that of conventional dropout, and hardware synthesis demonstrates that it results in significant resource reduction.

DOI： 10.1016/j.neucom.2020.11.055

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85098454549&origin=inward

Performance Evaluation of Reservoir Computing Using Pseudo-Billiard Dynamics in Hypercube 査読有り

D. Kamimura, Y. Katori, H. Tamukoh, and T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 135 - 135 2020年11月

A Reservoir Based Q-learning Model for Autonomous Mobile Robots 査読有り

M. Inada, Y. Tanaka, H. Tamukoh, K. Tateno, T. Morie, Y. Katori

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 213 - 216 2020年11月

FPGA Implementation and Verification of Reservoir Computing Based on Pseudo-Billiard Dynamics in Hypercube 査読有り

D. Yamamoto, I. Kawashima, H. Tamukoh, T. Morie, Y. Katori

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 264 - 264 2020年11月

A Brain-inspired Artificial Intelligence Model of Hippocampus, Amygdala, and Prefrontal Cortex on Home Service Robots 査読有り

Y. Tanaka, H. Tamukoh, K. Tateno, Y. Katori, T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 138 - 141 2020年11月

A Reservoir Computing System Using a CMOS Chaotic Boltzmann Machine Chip Controlled by SoC FPGA 査読有り

Y. Nishimura, M. Yamaguchi, D. Kamimura, H. Tamukoh, T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 137 - 137 2020年11月

A Hippocampus Model for Episodic Memory Processing Using Associative Memory 査読有り

H. Nakagawa, K. Tateno, K. Takada, T. Morie

Proc. of the 2020 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2020) 136 - 136 2020年11月

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design 国際誌

Y. Sakemi, K. Morino, T. Morie, K. Aihara

arXiv.org 2020年01月

An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach 国際誌

M. Yamaguchi, G. Iwamoto, H. Tamukoh, T. Morie

arXiv.org 1810.06819 2019年02月

A Time-domain Analog Weighted-sum Calculation Model for Extremely Low Power VLSI Implementation of Multi-layer Neural Networks 国際誌

Q. Wang, H. Tamukoh, T. Morie

arXiv.org 1810.06819 2018年10月

Spike-based Time-domain Weighted-sum Calculation Using Nanodevices for Low Power Operation 招待有り査読有り

T. Morie, H. Liang, T. Tohara, H. Tanaka, M. Igarashi, S. Samukawa, K. Endo, Y. Takahashi

16th Int. Conf. on Nanotechnology (IEEE NANO) 390 - 392 2016年08月

Measurement and Analysis of a CMOS Chaotic Spiking Oscillator Circuit That Acts as a Filter of Spike Trains 査読有り

M. Yamaguchi, S. Uenohara, T. Morie, H. Tamukoh, K. Aihara,

Proc. of the 2015 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2015) 515 - 518 2015年12月

A CMOS Circuit for PWM-mode Nonlinear Transformation Robust to Device Mismatches to Implement Coupled Map Lattice Models 査読有り

S. Uenohara, D. Atuti, K. Matsuzaka, H. Tamukoh, T. Morie, K. Aihara

Nonlinear Theory and Its Applications, IEICE 6 ( 4 ) 570 - 581 2015年10月

VLSI Pulse-Coupled Phase Oscillator Networks and Their Emulator toward Spike-based Computation for Intelligent Processing 招待有り査読有り

H. Tamukoh, Y. Suedomi, K. Matsuzaka, T. Morie

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM 2015) 806 - 807 2015年09月

Shadow Detection and Elimination Using a Light-source Color Vector and Its Application to In-vehicle Camera Images 査読有り

M. Tanaka, T. Morie

International Journal of Innovative Computing, Information and Control 11 ( 3 ) 865 - 879 2015年06月

A Silicon Nanodisk Array Structure Realizing Synaptic Response of Spiking Neuron Models with Noise 招待有り査読有り

T. Morie, H. Liang, Y. Sun, T. Tohara, M. Igarashi, S. Samukawa

The 19th Asia and South Pacific Design Automation Conference 185 - 190 2014年01月

Three-terminal Ferroelectric Synapse Device with Concurrent Learning Function for Artificial Neural Networks 査読有り

Y. Nishitani, Y. Kaneko, M. Ueda, T. Morie, E. Fujii

Journal of Applied Physics 111 124108 2012年06月

Analog CMOS Circuit Implementation of a Pulse-coupled Phase Oscillator System and Observation of Synchronization Phenomena, 査読有り

K. Matsuzaka, T. Tohara, K. Nakada, T. Morie

Nonlinear Theory and Its Applications, IEICE 3 ( 2 ) 180 - 190 2012年04月

A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation 査読有り

F. Maldonado H., H. Tanaka, T. Matsuo, T. Morie, K. Aihara

18th Int. Conf. on Neural Information Processing (ICONIP2011) III ( 7064 ) 381 - 388 2011年11月

知的画像認識技術と脳型LSI実装招待有り査読有り

森江隆, 石川聖二

電子情報通信学会誌 94 ( 6 ) 459 - 463 2011年06月

アナログ・デジタル融合方式LSI技術による脳型視覚システム招待有り査読有り

森江隆

IEICE Fundamentals Review 1 ( 1 ) 19 - 29 2007年07月

A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information 査読有り国際誌

Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024年06月

CMOS Digital-Analog Mixed Signal VLSI Implementation of a Hippocampus-Inspired Model 査読有り国際誌

Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024年06月

Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers 査読有り国際誌

Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh

International Symposium on Circuits and Systems (ISCAS 2024) 2024年05月

Learning reservoir dynamics with temporal self-modulation 査読有り国際誌

Sakemi Y., Nobukawa S., Matsuki T., Morie T., Aihara K.

Communications Physics 7 ( 29 ) 1 - 11 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Reservoir computing (RC) can efficiently process time-series data by mapping the input signal into a high-dimensional space via randomly connected recurrent neural networks (RNNs), which are referred to as a reservoir. The high-dimensional representation of time-series data in the reservoir simplifies subsequent learning tasks. Although this simple architecture allows fast learning and facile physical implementation, the learning performance is inferior to that of other state-of-the-art RNN models. In this study, to improve the learning ability of RC, we propose self-modulated RC (SM-RC) that extends RC by adding a self-modulation mechanism. SM-RC can perform attention tasks where input information is retained or discarded depending on the input signal. We find that a chaotic state can emerge as a result of learning in SM-RC. Furthermore, we demonstrate that SM-RC outperforms RC in NARMA and Lorenz model tasks. Because the SM-RC architecture only requires two additional gates, it is physically implementable as RC, thereby providing a direction for realizing edge artificial intelligence.

DOI： 10.1038/s42005-023-01500-w

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85182165175&origin=inward

Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory 査読有り国際誌

Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024年06月

FPGA Implementation of a Chaotic Boltzmann Machine Annealer 査読有り国際誌

K. Yoshioka, Y. Katori, Y. Tanaka, O. Nomura, T. Morie

International Joint Conference on Neural Networks (IJCNN 2023) 2023年06月

Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-volatile Memory with Write-errors 査読有り国際誌

N. Fuengfusin, H. Tamukoh, Y. Tanaka, O. Nomura, T. Morie

International Joint Conference on Neural Networks (IJCNN 2023) 2023年06月

Random Network Structure of Materials Developing Next Generation AI Devices for Autonomous Robotics 招待有り国際誌

H. Tanaka, H. Tamukoh, T. Morie

239th ECS Meeting with the 18th International Meeting on Chemical Sensors (IMCS) 2021年06月

A hardware intelligent processing accelerator for domestic service robots 査読有り

Y. Ishida, T. Morie, H. Tamukoh

Advanced Robotics 2020年07月

Initial states and analog switching behaviors of two major tantalum oxide resistive memories 査読有り国際誌

Li Y., Tsurumaki-Fukuchi A., Arita M., Morie T., Takahashi Y.

Japanese Journal of Applied Physics 59 ( 4 ) 2020年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2020 The Japan Society of Applied Physics. A systematic study was performed to understand the two major operation modes, valence change memory (VCM) and electrochemical memory (ECM), of tantalum oxide resistive memory, which were categorized by the type of conductive filament. The tantalum oxide insulator layer was predictably fabricated to modify the pristine oxygen-vacancy concentration in the insulator layer, where tantalum and copper top electrodes were used to achieve VCM and ECM modes. The distinguishable characteristics of the initial state and analog resistive switching operation revealed the prerequisites for switching capabilities and demonstrated the effects of oxygen vacancies in the two switching modes.

DOI： 10.35848/1347-4065/ab8022

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85083310643&origin=inward

Reconstructing bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems 査読有り

Itoh Y., Uenohara S., Adachi M., Morie T., Aihara K.

Chaos 30 ( 1 ) 2020年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2020 Author(s). Bifurcation-diagram reconstruction estimates various attractors of a system without observing all of them but only from observing several attractors with different parameter values. Therefore, the bifurcation-diagram reconstruction can be used to investigate how attractors change with the parameter values, especially for real-world engineering and physical systems for which only a limited number of attractors can be observed. Although bifurcation diagrams of various systems have been reconstructed from time-series data generated in numerical experiments, the systems that have been targeted for reconstructing bifurcation diagrams from time series measured from physical phenomena so far have only been continuous-time dynamical systems. In this paper, we reconstruct bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems with different parameter values. The generated time-series datasets are perturbed by dynamical noise and contaminated by observational noise. To reconstruct the bifurcation diagrams only from the time-series datasets, we use an extreme learning machine as a time-series predictor because it has a good generalization property. Hereby, we expect that the bifurcation-diagram reconstruction with the extreme learning machine is robust against dynamical noise and observational noise. For quantitatively verifying the robustness, the Lyapunov exponents of the reconstructed bifurcation diagrams are compared with those of the bifurcation diagrams generated in numerical experiments and by the electronic circuits.

DOI： 10.1063/1.5119187

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85078467746&origin=inward

超立方体上の疑似ビリヤードダイナミクスに基づくレザバー計算のFPGA実装

山本大智, 川島一郎, 田向権, 森江隆, 香取勇一

人工知能学会全国大会論文集 ( 一般社団法人人工知能学会 ) 2020 ( 0 ) 3Rin422 - 3Rin422 2020年01月

記述言語：日本語掲載種別：研究論文（その他学術会議資料等）

レザバー計算(RC)はリカレントニューラルネットワーク(RNN)の枠組みの1つで，時系列データの処理を目的に応用されている．機械学習モデルに対して，ディジタル回路実装を行うことで高速な演算速度を省電力で実現することが期待できる．香取らはディジタル回路との親和性が高いレザバー計算モデルを提案した．しかし，香取らのモデルをField Programmable Gate Array(FPGA)のようなディジタル回路に実装する場合，ニューロン数の変更に大きな制限が発生する．小規模な回路実装を行う手法として川嶋らがカオスボルツマンマシンのディジタル回路実装に用いたハードウェア指向アルゴリズムを提案している．本研究では川嶋らの提案したハードウェア指向アルゴリズムを基に対象のレザバー計算モデルを改良することで，ディジタル回路実装における回路リソースの消費を軽減可能なモデルを構築した．また，本研究のハードウェア指向アルゴリズムにより、レザバー計算の高速化の実現、人工知能構築のための新しいプラットフォームの確立が期待される．

DOI： 10.11517/pjsai.JSAI2020.0_3Rin422

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007857093

Hippocampus Model for Episodic Memory Processing Using Associative Memory 査読有り

立野勝巳, 森江隆

The proceedings of NOLTA2020 - 138 2020年01月

Prediction of Sensory Information and Generation of Motor Commands for Autonomous Mobile Robots Using Reservoir Computing 査読有り国際誌

M. Inada, Y. Tanaka, H. Tamukoh, K. Tateno, T. Morie, Y. Katori

Proc. of the 2019 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2015) 2019年12月

脳型人工知能技術の開発招待有り

石井信, 岡田真人, 菅生康子, 大羽成征, 山崎匡, 森江隆, 國吉康夫

人工知能 2019年11月

Switching current of Ta<inf>2</inf>O<inf>5</inf>-based resistive analog memories 査読有り

Li Y., Tsurumaki-Fukuchi A., Arita M., Morie T., Takahashi Y.

2019 Silicon Nanoelectronics Workshop, SNW 2019 2019年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 JSAP. Multilevel switching (MS) behaviors in Ta2O5-based resistive random-access-memory (ReRAM) have been drawing attentions as hardware artificial synapse. However, operating resistances, which decide the power consumption of whole system, are relatively low for future integration. In this work, we investigated the characteristics of two kinds of ReRAMs operating with different mechanisms; Cu-top-electrode and Ta-top-electrode Ta2O5-based ReRAMs. By taking account of resistance of high resistive state (HRS), we clarify the difference of MS characteristics between the two kinds of ReRAM devices.

DOI： 10.23919/SNW.2019.8782931

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85070868210&origin=inward

社会実装を目指したホームサービスロボットの研究開発

小野智寛, 坂田拓馬, 吉井拓巳, 上村大地, 金丸和樹, 中村健太郎, 西村雄太, 森江隆, 田向権, 堀三晟, 石田裕太郎, 田中悠一朗, 吉元裕真, 阿部佑志, 武藤冬樹, 椛島康平, 福宿将士

ロボティクス・メカトロニクス講演会講演概要集 ( 一般社団法人日本機械学会 ) 2019 ( 0 ) 1P2 - I02 2019年01月

記述言語：日本語掲載種別：研究論文（その他学術会議資料等）

Home service robots have begun attracting attention due to decreasing birthrate and increasing aging population. We,"Hibikino-Musashi@Home"team, develop home service robots, and participate international competitions; RoboCup@Home and World Robot Challenge (WRC), which are established to realize that robots will work and live with people in domestic environments. In this paper, we introduce our robots and technologies, especially an object recognition and manipulation system. We use You Only Look Once (YOLO) for object recognition. To train YOLO, a big dataset which is difficult to prepare in a short term is required. For this, we develop an automatic annotation system for YOLO which can generate 1.7 million training data, and we can complete training of YOLO in a day. To grasp objects, estimation of object orientations is required. Our system can detect the orientations by processing point clouds of objects. By using the system, we obtained about 30% of scores in Tidy Up Task in the WRC.

DOI： 10.1299/jsmermd.2019.1P2-I02

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007774525

Investigation for Multilevel Memory Capability of ReRAM using Ta2O5-δ Insulator 査読有り

Y. Li, R. Katsumura, M. K. Gronroos, A. Tsurumaki-Fukuchi, M. Arita, H. Andoh, T. Morie, Y. Takahashi

IEEE Silicon Nanoelectronics Workshop (SNW) 78 - 79 2018年06月

Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots 査読有り

Ishida Y., Morie T., Tamukoh H.

Proceedings - IEEE International Symposium on Circuits and Systems 2018年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. This live demonstration presents a 'connective object for middleware to accelerator (COMTA),' an intelligent processing system that uses hardware accelerators (i.e., field programmable gate arrays (FPGAs)) and robot middleware. The key idea of COMTA is to automatically generate the system via robot middleware interfaces. To realize the proposed system, we have developed a block of programs called an 'object' in a hardware/software complex system. We demonstrate an implementation of a human tracking image processing application on a vehicle robot accelerated by COMTA. The demonstration system achieved 3.3 times better power efficiency than a general PCs.

DOI： 10.1109/ISCAS.2018.8351837

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85057134814&origin=inward

A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots 査読有り

Ishida Y., Morie T., Tamukoh H.

Proceedings - IEEE International Symposium on Circuits and Systems 2018-May 2018年04月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Service robots require implementation of intelligent processing, e.g., image processing. However, the computational resources of standard PCs typically used in service robots are not sufficient for such processes. Furthermore, robot middleware is widely used in many robots because such systems facilitate integration and are suitable for rapid prototyping. We propose a 'connective object for middleware to accelerator (COMTA),' which is a processing system that uses hardware accelerators, i.e., field programmable gate arrays (FPGAs), and robot middleware. Users can access the FPGAs in the proposed system via middleware interfaces; thus, complex internal circuits are not required. For human tracking using image processing, the proposed system can automatically generate from a single configuration file. The proposed system performs 3.3 times more efficiently relative to computation than standard PCs in robots.

DOI： 10.1109/ISCAS.2018.8351722

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85057089804&origin=inward

A pulse-width-modulation mode CMOS integrated circuit implementation of threshold-coupled map 査読有り

Uenohara Seiji, Morie Takashi, Tamukoh Hakaru, Aihara Kazuyuki

Nonlinear Theory and Its Applications, IEICE 9 ( 2 ) 268 - 280 2018年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

We propose a coupled-map-lattice complementary-metal-oxide-semiconductor very-large-scale-integration (CMOS VLSI) circuit based on the threshold-coupled map (TCM) that has been proposed previously as a unidirectional connected network model exhibiting different spatiotemporal patterns according to its underlying nonlinear map and update scheme. We introduce mutual connections and arbitrarily valued connection weights into the TCM to realize cellular automata. In this study, we design, fabricate, and evaluate a CMOS integrated circuit with which to implement this extended TCM (ETCM). The ETCM is a universal Turing machine as confirmed in circuit experiments using the fabricated circuit, which can achieve Rule110 of a one-dimensional cellular automaton.

DOI： 10.1587/nolta.9.268

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130006602774

A shared synapse architecture for efficient FPGA implementation of autoencoders 査読有り

A. Suzuki, T. Morie, H. Tamukoh

PLoS ONE 13 ( 3 ) e0194049 2018年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

Copyright: © 2018 Suzuki et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers’ units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

DOI： 10.1371/journal.pone.0194049

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85044091289&origin=inward

脳型アナログ演算と専用集積回路招待有り査読有り

森江隆

人工知能 33 ( 1 ) 39 - 44 2018年01月

A hardware-oriented dropout algorithm for efficient FPGA implementation 査読有り

Yeoh Y., Morie T., Tamukoh H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10639 LNCS 821 - 829 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Guangzhou 2017年11月14日 - 2017年11月18日

© Springer International Publishing AG 2017. This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

DOI： 10.1007/978-3-319-70136-3_87

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85035101597&origin=inward

An implementation of a spiking neural network using digital spiking silicon neuron model on a SIMD processor 査読有り

Hori S., Zapata M., Madrenas J., Morie T., Tamukoh H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10613 LNCS 437 - 438 2017年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Italy Alghero 2017年09月11日 - 2017年09月14日

© Springer International Publishing AG 2017. We implement a digital spiking silicon neuron (DSSN) [1] in a single instruction multiple data (SIMD) processor. The SIMD processor is a scalable, reconfigurable, and real-time spiking neural network emulator based on field programmable gate arrays [2]. We implement the DSSN model in the SIMD processor for the first time. The behavior of the membrane potential of one neuron based on the DSSN model is shown in Fig. 1. The operation results of the SIMD processor with 16-bit fixed-point operation are compared with software simulation results based on 64-bit floating-point operation. From the results, it is concluded that the SIMD processor successfully emulated the behavior of the membrane potential. In addition, a full-connection network consisting of 100 neurons is simulated in a software using fixed-point binary numbers to evaluate the bit width for the SIMD processor. In this experiment, the network stores two patterns selected from [1]. In the recall phase, the first pattern with noise is given to this network to recall the pattern. Experimental results show that the network with 16-bit fixed-point numbers, each of which includes a 12-bit fraction, a 3-bit integer, and a 1-bit sign, successfully recalled the input pattern as shown in Fig. 2. Here, Muis a recall rate [1]. From this result, a large DSSN network simulation on the SIMD processor is promising.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85034266960&origin=inward

カーロボ連携大学院での自動車・ロボットの知能化高度化に向けた専門人材育成招待有り査読有り

森江隆, 石井和男, 我妻広明, 田向権, 榎田修一, 齊藤剛史, 松永良一, 松波勲, 大貝晴俊

工学教育 65 ( 4 ) 51 - 56 2017年07月

Evaluation of multilevel memory capability of ReRAM using Ta<inf>2</inf>O<inf>5</inf>insulator and different electrode materials 査読有り

Li Y., Katsumura R., Grönroos M., Tsurumaki-Fukuchi A., Arita M., Andoh H., Morie T., Takahashi Y.

2017 Silicon Nanoelectronics Workshop, SNW 2017 85 - 86 2017年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Kyoto 2017年06月04日 - 2017年06月05日

© 2017 JSAP. ReRAM (Resistive Random Access Memory) has been drawing attention for its neural network applications with low-power and high-speed operation. The multilevel data storage capability is inherently needed to use the ReRAM as synaptic devices. In this study, two ReRAM devices with different electrode materials in which the operation mechanisms are thought to be different was fabricated and tested. It was clarified that the multilevel resistance characteristics were achieved in both devices.

DOI： 10.23919/SNW.2017.8242309

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85051019890&origin=inward

Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links 査読有り

D. Pramanta, T. Morie, H. Tamukoh

Journal of Robotics, Networking and Artificial Life 4 ( 1 ) 91 - 96 2017年06月

Self-Feedback Electrically Coupled Spin-Hall Oscillator Array for Pattern-Matching Operation 査読有り

K. Kudo, T. Morie

Appl. Phys. Express 10 ( 4 ) 043001 2017年03月

Multi-Valued Quantization Neural Networks toward Hardware Implementation 査読有り

Y. Aratani, Y. Y. Jye, A. Suzuki, D. Shuto, T. Morie, H. Tamukoh

Proc. of the 2017 International Conference On Artificial Life And Robotics (ICAROB2017) 58 - 58 2017年01月

Implementation of multi-FPGA Communication using Pulse-Coupled Phase Oscillators 査読有り

D. Pramanta, T. Morie, H. Tamukoh

Proc. of the 2017 International Conference On Artificial Life And Robotics (ICAROB2017) 57 - 57 2017年01月

An Electrically Coupled Spin-Hall Oscillator Array for Pattern Matching Operation 査読有り

K. Kudo, T. Morie

61st Annual Conf. on Magnetism and Magnetic Materials (MMM 2016) 2016年11月

A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines 査読有り

M. Yamaguchi, T. Kato, Q. Wang, H. Suzuki, H. Tamukoh, T. Morie

Proc. 23rd Int. Conf. on Neural Information Processing (ICONIP2016) 9947 248 - 255 2016年10月

FPGA Implementation of Autoencoders Having Shared Synapse Architecture 査読有り

A. Suzuki, T. Morie, H. Tamukoh

Proc. 23rd Int. Conf. on Neural Information Processing (ICONIP2016) 9947 231 - 239 2016年10月

Time-domain Weighted-sum Calculation for Ultimately Low Power VLSI Neural Networks 査読有り

Q. Wang, H. Tamukoh, T. Morie

Proc. 23rd Int. Conf. on Neural Information Processing (ICONIP2016) 9947 240 - 247 2016年10月

Analog VLSI Circuits and Devices for Neuro-Inspired Time-Domain Computing 招待有り査読有り

T. Morie

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM 2016) 117 - 118 2016年09月

Hardware-oriented Algorithm for Chaotic Boltzmann Machines 査読有り

I. Kawashima, S. Uenohara, T. Kato, M. Yamaguchi, H. Suzuki, T. Morie, H. Tamukoh

Int. Workshop on Smart Info-Media Systems in Asia (SISA) 2016年09月

Restricted Boltzmann Machines without Random Number Generators for Efficient Digital Hardware Implementation 査読有り

S. Hori, T. Morie, H. Tamukoh

The 25th Int. Conf. on Artificial Neural Networks (ICANN) 9886 391 - 398 2016年09月

Depth-Based Visual Servoing Using Low-Accurate Arm 査読有り

L. Hofer, M. Tanaka, H. Tamukoh, A. A. F. Nassiraei, T. Morie

Joint 8th Int. Conf. on Soft Computing and Intelligent Systems and 17th Int. Symp. on Advanced Intelligent Systems (SCIS & ISIS 2016) 2016年08月

Analog Memory Characteristics of 1T1R MoOx Resistive Random Access Memory 査読有り

M. Jo, R. Katsumura, A. Tsurumaki-Fukuchi, M. Arita, Y. Takahashi, H. Ando, T. Morie

IEEE Silicon Nanoelectronics Workshop (SNW) 78 - 79 2016年06月

Human Detection and Face Recognition Using 3D Structure of Head and Face Surfaces Detected by RGB-D Sensor 査読有り

M. Tanaka, H. Matsubara, T. Morie

Journal of Robotics and Mechatronics 27 ( 6 ) 691 - 697 2015年12月

A Pixel-Parallel State-Propagation Algorithm with Self-Update of Propagation Direction for Subjective Contour Generation 査読有り

H. Sou, T. Morie

Int. Sympo. on Intelligent Signal Processing and Communication Systems (ISPACS 2015) 53 - 56 2015年11月

CMOS Circuits and Nanodevices for Spike Based Neural Computing 招待有り査読有り

T. Morie

IEEE Int. Meeting for Future of Electron Devices, Kansai 112 - 113 2015年06月

More than Mooreでブレークスルーを狙う脳型チップ

森江隆

日本神経回路学会誌 ( Japanese Neural Network Society ) 22 ( 2 ) 51 - 52 2015年01月

Morphological Associative Memory Employing a Split Store Method 査読有り

H. Tamukoh, K. Koga, H. Harada, T. Morie

Proc. 21th Int. Conf. on Neural Information Processing (ICONIP2014), (Lecture Notes in Computer Science, LNCS 8836) 3 341 - 348 2014年10月

A Chaotic Spiking Oscillator That Acts As a Filter of Spike Trains 査読有り

S. Uenohara, T. Morie

Abs. Collection of the 2014 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2014) 723 - 726 2014年09月

A Motion Detection Model Inspired by Hippocampal Function and Its Applications to Obstacle Detection 査読有り

H. Liang, T. Morie

Neurocomputing 129 59 - 66 2014年04月

M-HOG 特徴量と色相の共起情報を用いた人検出法査読有り

中島佑樹, タンジュークイ, 金亨燮, 森江隆, 石川聖二

バイオメディカル・ファジィ・システム学会誌 16 ( 1 ) 67 - 74 2014年04月

Digital Circuit Design of Pulse-coupled Phase Oscillator Systems for Coupled MRF Models 査読有り

Y. Suedomi, H. Tamukoh, M. Tanaka, K. Matsuzaka, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 89 - 92 2014年03月

Object Segmentation Using 3D Information Obtained from RGB-D Sensor 査読有り

T. Matsumoto, M. Tanaka, H. Tamukoh, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 377 - 380 2014年03月

Sound Quality Improvement of Low Bit Rate Coded Audio Signals with Nonlinear Functions 査読有り

T. Yoshino, Y. Sato, H. Tamukoh, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 237 - 240 2014年03月

Robustness to CMOS Device Mismatches of Time-domain Voltage/Current Sampling Circuits for Implementing Large-scale Coupled Nonlinear Dynamical Systems 査読有り

S. Uenohara, D. Atuti, K. Matsuzaka, H. Tamukoh, T. Morie

2014 RISP Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014) 93 - 96 2014年03月

Videotaped obstacle extraction from a moving camera 査読有り

Qian S., Tan J., Kim H., Ishikawa S., Morie T., Shinomiya T.

International Journal of Innovative Computing, Information and Control 10 ( 2 ) 717 - 728 2014年02月

記述言語：英語掲載種別：研究論文（学術雑誌）

In automatic collision avoidance systems, the ability to detect obstacles is important. This paper proposes a method of automatic obstacles detection employing a camera mounted on a vehicle. Although various methods of obstacles detection have already been reported, they normally detect moving objects such as pedestrians and bicycles. In this paper, a method is proposed for detecting obstacles on a road, even if they are moving or static, by the use of background modeling and road region classification. Background modeling is often used to detect moving objects when a camera is static. In this paper, we apply it to a moving camera case in order to obtain foreground images. Then we calculate the camera motion parameters using the correspondence of feature points between two consecutive images and detect the road region using motion compensation. In this road region, we carry out regional classification. We can delete all objects which are not obstacles in the foreground images based on the result of the regional classification. In the performed experiments, it is shown that the proposed method is able to extract the shape of both static and moving obstacles in a frontal view from a car. © 2014 ISSN 1349-4198.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84893413251&origin=inward

Classifying 2D and 3D objects on a road employing the road plane 査読有り

Qian S., Tan J., Kim H., Ishikawa S., Morie T., Shinomiya T.

Proceedings of the SICE Annual Conference 1689 - 1692 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Obstacles detection is an important technology in autonomous collision avoidance systems. We have already proposed an obstacle detection method based on background modeling. But this method detects 2D and 3D objects simultaneously. Since these 2D objects are not dangerous to driving, they will reduce the accuracy of detection if they are detected as obstacles. In order not to detect these 2D objects, this paper proposes a method for classifying 2D objects and 3D objects. The proposed method first estimates the camera motion parameters from the correspondences of feature points between two successive images. We calculate the 3D positions of the feature points on a detected object in the world coordinate system using triangulation. Then we estimate the parameters of the road plane using 3D positions of those feature points. Finally we calculate the distances from the 3D positions of the feature points to the road plane. Based on these distances, we can classify 2D objects and 3D objects. Experimental results show satisfactory performance of the proposed method.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84888611260&origin=inward

Parameterized Digital Hardware Design of Pulse-coupled Phase Oscillator Model toward Spike-based Computing 招待有り査読有り

Y. Suedomi, H. Tamukoh, M. Tanaka, K. Matsuzaka, T. Morie

Proc. 20th Int. Conf. on Neural Information Processing (ICONIP2013) 2013年11月

A PWM-Mode CMOS Threshold-Coupled-Map Circuit Robust to Device Mismatches 査読有り

S. Uenohara, D. Atuti, K. Matsuzaka, H. Tamukoh, T. Morie, K. Aihara

Abs. Collection of the 2013 Int. Symp. on Nonlinear Theory and Its Applications (NOLTA2013) 503 - 506 2013年09月

Road region estimation and obstacles extraction using a monocular camera 査読有り

Qian S., Tan J., Kim H., Ishikawa S., Morie T., Shinomiya T.

International Journal of Innovative Computing, Information and Control 9 ( 9 ) 3561 - 3572 2013年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

An obstacles detection method is proposed which employs a camera mounted on a vehicle. Although various methods of obstacles detection have already been reported, they normally detect only moving obstacles and not static obstacles, and a detected obstacle is represented by a rectangular frame that surrounds this obstacle, which does not provide shape of the obstacle. In this paper, a method is proposed for detecting obstacles on a road, irrespective of moving or static, by use of background modeling and road region detection. The output of the proposed method is the shape of obstacles. Background modeling is often used to detect moving objects when a camera is static. In this paper, we apply it to a moving camera case in order to obtain foreground images. Then we extract the road region using SVM. In this road region, we carry out region classification. We can delete all the objects which are not obstacles in the foreground images based on the result of the region classification. In the performed experiments, it is shown that the proposed method is able to extract the shape of both static and moving obstacles when a car is driving. © 2013 ISSN 1349-4198.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84880054018&origin=inward

Experimental Distinction between Chaotic and Strange Nonchaotic Attractors on the Basis of Consistency 査読有り

Uenohara, T. Mitsui, Y. Hirata, T. Morie, Y. Horio, K. Aihara

Chaos 23 ( 2 ) 23110-1 - 23110-9 2013年05月

Obstacles extraction using a moving camera 査読有り

Qian S., Tan J., Kim H., Ishikawa S., Morie T.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7729 LNCS ( PART 2 ) 441 - 453 2013年04月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

A method of automatic obstacles detection is proposed which employs a camera mounted on a vehicle. Although various methods of obstacles detection have already been reported, they normally detect moving objects such as pedestrians and bicycles. In this paper, a method is proposed for detecting obstacles on a road, irrespective of moving or static, by the employment of the background modeling and the road region classification. The background modeling is often used to detect moving objects when a camera is static. In this paper, we apply it to the moving camera case to get foreground images. Then we extract the road region using SVM. In this road region, we carry out region classification. Then we can delete all the things which are not obstacles in the foreground images using the result of the region classification. In the performed experiments, it is shown that the proposed method is able to extract the shapes of both static and moving obstacles in a frontal view from a car. © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-37484-5_36

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84876011141&origin=inward

Gabor Features for Real-Time Road Environment Classification 査読有り

L. Mioulet, T. P. Breckon, A. Mouton, H. Liang, T. Morie

Proc. IEEE Int. Conf. on Industrial Technology (ICIT) 1117 - 1121 2013年02月

スパイクベース非線形演算のためのCMOS結合位相振動子回路

東原敬, 松坂建治, 西広海, 森江, 隆

電子情報通信学会 NLP研究会 112 ( 389 ) 137 - 142 2013年01月

FPGAにより制御される専用アナログチップを用いたスパイキングニューラルネットワークシステムの開発

前田道孝, Frank Maldonado H., 松尾貴之, 田中秀樹, 梁海超, 松坂建治, 森江隆, 合原一幸

電子情報通信学会 NC研究会 112 ( 390 ) 181 - 186 2013年01月

電圧・電流波形サンプリング方式によるしきい値結合カオス回路の設計

上ノ原誠二, 厚地泰輔, 松坂建治, 森江隆, 合原一幸

電子情報通信学会 NLP研究会 112 ( 389 ) 105 - 110 2013年01月

Obstacles Extraction from a Video Taken by a Moving Camera 査読有り

S. Qian, J. K. Tan, H. Kim, S. Ishikawa, and T. Morie

1st Int. Conf. on Connected Vehicles & Expo 2012年12月

知的センシグデバイスデバイスのための脳型処理モデルを実現するアナログ・ディジタル融合LSI 招待有り

森江隆, 秦佑輔、西広海、松坂建治

電気学会センサ・マイクロマシン部門大会, 第29回「センサ・マイクロマシンと応用システム」シンポジウム 2012年10月

LSI実装に向けたパルス結合位相振動子系に基づくスパイクベース演算

松坂建治, 田中秀樹, 大久保悟, 東原敬, 森江隆

電子情報通信学会 NC研究会 112 ( 227 ) 127 - 132 2012年10月

トマト果実自動収穫のためのKinectセンサを利用した果実・萼位置検出手法

栗谷康隆, 田中宙夫, 松原弘樹, 清水昌樹, 森江隆

画像の認識・理解シンポジウム IS1-76 2012年08月

A Hierarchical Extension of the HOG Model Implemented in the Convolution-net for Human Detection 査読有り

Y. Arakaki, H. Shouno, K. Takahashi, and T. Morie

IPSJ Transactions on Mathematical Modeling and Its Applications 5 ( 3 ) 54 - 62 2012年08月

Biologically-inspired Learning Device using Three-terminal Ferroelectric Memristor 査読有り

M. Ueda, Y. Kaneko, Y. Nishitani, T. Morie and E. Fujii

70th Device Research Conference 275 - 276 2012年06月

Bicycle Detection Using Pedaling Movement by Spatiotemporal Gabor Filtering 査読有り

K. Takahashi, Y. Kuriya, T. Morie

Int. J. of innovative Computing Information and Control 8 ( 6 ) 2012年06月

Torus-doubling Process via Strange Nonchaotic Attractors 査読有り

T. Mitsui, S. Uenohara, T. Morie, Y. Horio, and K. Aihara

Physics Letters A 376 1907 - 1914 2012年05月

画像処理による道路状態・歩行者の認識,

森江隆, 石川聖二, 松岡　悟

光技術コンタクト ( 社団法人日本オプトメカトロニクス協会 ) 50 ( 6 ) 20 - 24 2012年04月

強誘電体ゲートトランジスタを用いたシナプス素子におけるSTDP機能の実証

.西谷雄, 金子幸広, 上田路人, 森江隆, 藤井映志

電子情報通信学会 NC研究会 111 ( 483 ) 203 - 207 2012年03月

A hierarchical extension of the HOG model implemented in the convolution-net for human detection

Y. Arakaki, H. Shouno, K. Takahashi, and T. Morie

情報処理学会研究報告. MPS, 数理モデル化と問題解決研究報告 2012年02月

A Motion Detection Model Inspired by the Neuronal Propagation in the Hippocampus 査読有り

H. Liang, T. Morie

IEICE Trans. Fundamentals E95-A ( 2 ) 576 - 585 2012年02月

Obstacle detection using a moving camera 査読有り

Qian S., Tan J., Ishikawa S., Morie T.

Proceedings of the 16th International Symposium on Artificial Life and Robotics, AROB 16th'11 767 - 770 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a method of detecting obstacles from a video taken by a moving camera mounted on a vehicle by background subtraction. The background subtraction is often used to detect moving objects when camera is static. But according to the characteristics of a road, we can also employ Gaussian mixture model to detect all objects (either static or moving objects) on the road in the case of moving camera. Then we use two consecutive image frames, and warps the first image according to the geometrical relationship between these two images. The road area is then extracted by comparing the warped image with the second image. Using this road area, we can delete all things which are not obstacles. In the performed experiments, it is shown that the proposed method is able to detect obstacles such as vehicles and pedestrians on a road. © 2011 ISAROB.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84866717620&origin=inward

Moving objects detection at an intersection by sequential background extraction 査読有り

Sonoda S., Tan J., Kim H., Ishikawa S., Morie T.

International Conference on Control, Automation and Systems 1752 - 1755 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, there are many traffic accidents in turning right at an intersection. They are mainly caused by a driver's oversight of pedestrians and motorcycles that are occluded by oncoming cars. Therefore a system is necessary to detect moving objects such as oncoming cars and pedestrians at an intersection, and warn a vehicle driver. This paper describes a technique for detecting moving objects in turning right at an intersection when vehicle is stopping. Moving objects are detected by Mixture of Gaussians (MoG). In addition, we distinguish cars from pedestrians using the difference of the area size and the aspect ratio of detected objects. The object which is classified as a pedestrian is tracked using Lucas-Kanade Tracker. If the detected cars and pedestrians overlap or a car completely obscures pedestrians, we perform the estimation of pedestrian's location by using the information on past frames. By doing this, it is possible to detect pedestrians that drivers are actually difficult to see. The performance of the proposed technique was examined employing car videos and satisfactory results were obtained. © 2011 ICROS.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84863041517&origin=inward

Extraction of individual pedestrians employing stereo camera images 査読有り

Kawabe M., Tan J., Kim H., Ishikawa S., Morie T.

International Conference on Control, Automation and Systems 1744 - 1747 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

A traffic accident occurs mainly because of carelessness of a driver. To prevent such an accident, many systems which detect pedestrians from vehicle are proposed. But most of these systems give a warning to a driver every time when a pedestrian is detected. The effect of warning becomes lower if the frequency of warning increases in a busy area. The objective of this study is to develop a technique for detecting pedestrians from a vehicle and to arrange them according to their potential risks by analyzing their behaviors. In this paper, we propose a technique for segmenting pedestrians employing stereo camera images to analyze a pedestrian's behavior. First, foreground regions are extracted employing background estimation using the mixture of Gaussian model. After extracting foreground regions in an input image, these regions are segmented by using the distance information. By using this method, each shape of the detected pedestrians can be obtained even when pedestrians are overlapping with each other. The proposed technique was examined experimentally employing real video images and satisfactory results were obtained. © 2011 ICROS.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84863049839&origin=inward

Applying HOG feature to the detection and tracking of a human on a bicycle 査読有り

Jung H., Tan J., Ishikawa S., Morie T.

International Conference on Control, Automation and Systems 1740 - 1743 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Detection of a human on a bicycle is an important research subject in an advanced safety vehicle driving system to decrease traffic accidents. The Histograms of Oriented Gradients (HOG) feature has been proposed as useful feature for detecting a standing human in various kinds of background. So, many researchers use currently the HOG feature to detect a human. Detecting a human on a bicycle is more difficult than detecting a human because a bicycle's appearance can change dramatically according to viewpoints. In this paper, we propose a method of detecting a human on a bicycle using HOG feature and RealAdaboost algorithm. When detecting a human on a bicycle, occlusion is a cause of decreasing detection efficiency. Occlusion is a serious matter in car vision research because there are occlusions in real transportation environment. We decide the next position of a human on a bicycle using object tracking. Experimental results and evaluation show satisfactory performance of the proposed method. © 2011 ICROS.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84856534795&origin=inward

A 1-D CMOS Pixel Circuit Array Implementing a Region-Based Coupled MRF Model for Coarse Image Region Segmentation 査読有り

H. Nishi, Y. Hata, K. Matsuzaka, K. Nakada, T. Morie

The 21st Annual Conference of the Japanese Neural Network Society (JNNS 2011) 210 - 211 2011年12月

Analysis of Associative Memory Operation in a VLSI Spiking Neural Network 査読有り

F. Maldonado H., H. Tanaka, T. Matsuo, T. Morie, K. Aihara

The 21st Annual Conference of the Japanese Neural Network Society (JNNS 2011) 208 - 209 2011年12月

Fundamental Study on Spiking Neuron Devices 査読有り

T. Morie, H. Liang, Y. Sun, M. Igarashi, S. Samukawa

Proc. of the Eleventh Int. Symp. on Advanced Fluid Information and Transdisciplinary Fluid Integration (AFI/TFI 2011) 120 - 121 2011年11月

A Motion Detection Model Inspired by Hippocampal Function and Its FPGA Implementation 査読有り

H. Liang T. Morie

18th Int. Conf. on Neural Information Processing (ICONIP2011) III ( 7064 ) 522 - 529 2011年11月

ナノディスクアレイ構造とCMOS回路を結合したスパイキングニューロンデバイス

梁海超, 森江隆, 孫意来, 五十嵐誠, 寒川誠二

電子情報通信学会ニューロコンピューティング研究会 111 ( 241 ) 125 - 129 2011年10月

Detecting a Human Body Direction Using Multiple-HOG 査読有り

Y. Nakashima, J. K. Tan, S. Ishikawa, T. Morie

First Int. Symp. on Future Active Safety Technology toward zero-traffic-accident (FAST-zero '11) 20117394-1 - 20117394-6 2011年09月

Detection of Road Surface Condition Using Gabor Filter 査読有り

M. Tanaka, T. Morie, K. Iwase, T. Kume, S. Matsuoka, Y. Yamamoto

First Int. Symp. on Future Active Safety Technology toward zero-traffic-accident (FAST-zero '11) 20117341-1 - 20117341-5 2011年09月

脳型情報処理デバイスの現状と今後の展開招待有り

森江隆, 梁海超, 孫意来, 田中秀樹, 五十嵐誠, 寒川誠二

応用物理学会シリコンテクノロジー分科会第140回研究集会 28 - 32 2011年08月

A CMOS Nonlinear-Map Circuit Array for Threshold-Coupled Chaotic Maps Using Pulse-Modulation Approach 査読有り

T. Morie, D. Atuti, K. Ifuku, Y. Horio, K. Aihara

European Conf. on Circuit Theory and Design (ECCTD 2011) 125 - 128 2011年08月

Analog CMOS Circuit Implementation of a System of Pulse-Coupled Oscillators for Spike-Based Computation 査読有り

K. Matsuzaka, K. Nakada, T. Morie

IEEE Int. Symp. on Circuits and Systems (ISCAS 2011) 2849 - 2852 2011年05月

画素並列ハードウェアのための曲率を有する主観的輪郭生成アルゴリズム

山口雄一郎,森江隆

電子情報通信学会 NC研究会 110 ( 461 ) 65 - 70 2011年03月

大局的画像領域分割のための領域および境界ベース結合MRFモデルを実現するPWM方式画素並列型LSIの設計

秦佑輔,松坂建治,西広海,中田一紀,森江隆

電子情報通信学会 NC研究会 110 ( 461 ) 59 - 64 2011年03月

集積回路化を目指した大局的画像領域分割のための領域ベース結合MRFモデル査読有り

梁海超, 川嶋佑輔, 松坂建治, 中田一紀, 岡田真人, 森江隆

電気学会論文誌C 131 ( 3 ) 567 - 575 2011年03月

海馬の神経活動にヒントを得た単眼カメラ映像での動き検出モデルおよびその障害物検知への応用

梁海超,森江隆

電子情報通信学会 ITS研究会, Vol. 110, No. 420, ITS2010-62, pp. 269-274, 2011年2月22日, 北海道大学（札幌） 110 ( 420 ) 269 - 274 2011年02月

時空間ガボールフィルタによるペダル漕ぎ運動検出を用いた自転車識別

高橋和志,栗谷康隆,森江隆

電子情報通信学会 ITS研究会 110 ( 420 ) 257 - 262 2011年02月

車載カメラ画像のガボールフィルタ処理による自動車前方路面の乾湿判定

田中宙夫,森江隆,松岡悟,岩瀬耕二,山本康典

電子情報通信学会 ITS研究会 110 ( 420 ) 263 - 267 2011年02月

Parametric Control in a Region-based Coupled MRF model with Phase Dynamics for Coarse Image Region Segmentation 査読有り

H. Liang,K. Nakada,K. Matsuzaka,T. Morie,M. Okada

The 13th IEEE International Conference on Computational Science and Engineering (CSE 2010) 190 - 195 2010年12月

Bicycle Detection Using Pedaling Movement by Spatiotemporal Gabor Filtering 査読有り

K. Takahashi,Y. Kuriya,T. Morie

Int. Tech. Conf. of IEEE Region 10 (TENCON2010) 918 - 922 2010年11月

Detecting a Human Body Direction Using a Feature Selection Method 査読有り

Y. Nakashima,J. K. Tan,S. Ishikawa,T. Morie

Proc. of Int. Conf. on Control, Automation and Systems 1424 - 1427 2010年10月

集積回路実装に向けた大局的画像領域分割のための領域ベース結合MRFモデルのパラメータ制御

梁海超,松坂建治,中田一紀,岡田真人,森江隆

電子情報通信学会ニューロコンピューティング研究会 110 ( 264 ) 35 - 40 2010年10月

Control of Activation Energy for Electron Transport in Two-Dimensional Array of Si Nanodisks 査読有り

M. Igarashi,C. H. Huang,T. Morie,S. Samukawa

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM) 934 - 935 2010年09月

Coarse Image Edge Detection Using Self-Adjusting Resistive-Fuse Networks 査読有り

H. Liang,T. Morie

Proc. of 10th Int. Workshop on Pattern Recognition in Information Systems (PRIS 2010) 43 - 52 2010年06月

A 2-Dimensional Si Nanodisk Array Structure for Spiking Neuron Models 査読有り

T. Morie,Y. Sun,H. Liang,M. Igarashi,C. Huang,S. Samukawa

IEEE Int. Symp. on Circuits and Systems (ISCAS 2010) 781 - 784 2010年06月

Coarse Image Region Segmentation Performance of a Region-based Coupled MRF Model with Improved Evaluation Function 査読有り

K. Nakada,K. Matsuzaka,T. Morie

Fourteenth International Conference on Cognitive and Neural Systems (ICCNS), p. 31, Boston, USA, May 19-22 (May 20), 2010. 31 - 31 2010年05月

車載カメラ映像からの横断歩道上の歩行者の検出法査読有り

タンジュークイ,三好誠,石川聖二,森江隆

バイオメディカル・ファジィ・システム学会誌 12 ( 1 ) 99 - 103 2010年05月

Automatic Detection of Pedestrians from Stereo Camera Images 査読有り

J. K. Tan,K. Inumaru,S. Ishikawa,T. Morie

Artificial Life and Robotics 15 ( 4 ) 459 - 463 2010年04月

On Detecting a Human and Its Body Direction from a Video 査読有り

Y. Nakashima,J. K. Tan,S. Ishikawa,T. Morie

Artificial Life and Robotics 15 ( 4 ) 455 - 458 2010年04月

HOG特徴量と人マスクを用いた人物および身体方向の検出査読有り

中島佑樹,タンジュークイ,石川聖二,森江隆

画像電子学会誌 39 ( 6 ) 1104 - 1111 2010年04月

Markerless Arm Posture Estimation Independent of Environment 査読有り

M. Shimizu,I. R. Khan,Y. Kuriya,H. Miyamoto,T. Morie

J. Signal Processing 14 ( 6 ) 475 - 481 2010年04月

Coarse Image Region Segmentation in Spatio-Temporal Domain Using a Region-based Coupled MRF Model with Phase Dynamics 査読有り

K. Nakada,K. Matsuzaka,T. Morie

Australian Journal of Intelligent Information Processing Systems 11 ( 2 ) 6 - 11 2010年04月

Control of Electron Transport in Two-Dimensional Array of Si Nanodisks for Spiking Neuron Device 査読有り

M. Igarashi,C.-H. Huang,T. Morie,S. Samukawa

Appl. Phys. Express 3 085202 - 085202 2010年04月

Markerless Arm Posture Estimation Independent of Environment 査読有り

M. Shimizu,I. R. Khan,Y. Kuriya,H. Miyamoto,T. Morie

RISP 2010 Int. Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'10) 2010年03月

On Detecting a Human and Its Body Direction from a Video 査読有り

Y. Nakashima,J. K. Tan,S. Ishikawa,T. Morie

Int. Symp. on Artificial Life and Robotics (AROB 15th '10) #GS2-5 294 - 297 2010年02月

Automatic Detection of Pedestrians from Stereo Camera Images 査読有り

K. Inumaru,J. K. Tan,S. Ishikawa,T. Morie

Int. Symp. on Artificial Life and Robotics (AROB 15th '10) #GS9-4 1018 - 1021 2010年02月

しきい値処理により結合されたカオス力学系のパルス変調方式CMOS回路実現,

井福一毅,厚地泰輔,森江隆,堀尾喜彦,合原一幸

電子情報通信学会非線形問題研究会, NLP2009-154 109 ( 366 ) 65 - 70 2010年01月

画素並列型異方性拡散LSIとそれを用いてエッジ補完を行う画像処理システム,

財津賢一郎,金永宰,栗谷康隆,森江隆

映像情報メディア学会技術報告情報センシング研究会 33 ( 56 ) 17 - 20 2009年12月

A Simplified Region-Based Coupled MRF Model for Coarse Image Region Segmentation Toward its VLSI Implementation, 査読有り

K. Matsuzaka,T. Morie

Proc. of Int. Symp. on Nonlinear Theory and its Applications (NOLTA2009) 202 - 205 2009年10月

Video Monitoring of Slope Failure Using Spatiotemporal Gabor Filtering 査読有り

K. Okamoto,T. Watanabe,H. Ban,Y. Maeda,A. Hanazawa,T. Morie

Proc. of the 2009 IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC2009) 986 - 991 2009年10月

New Functional Device Characteristics with 2-Dimensional Array of Si Nanodisks Fabricated by Combination of Bio-Template and Ultimate Top-down Etching 査読有り

M. Igarashi,C. H. Huang,M. Tomura,M. Takeguchi,S. Horita,Y. Uraoka,T. Fuyuki,I. Yamashita,T. Morie,S. Samukawa

Ext. Abstracts of Int. Conf. on Solid State Devices and Materials (SSDM) 1364 - 1365 2009年08月

A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function, 査読有り

H. Tanaka,T. Morie,K. Aihara

IEICE Trans. Fundamentals E92-A ( 7 ) 2009年07月

Coarse Image Region Segmentation Using Region- and Boundary-based Coupled MRF Models and Their PWM VLSI Implementation 査読有り

Y. Kawashima,D. Atuti,K. Nakada,M. Okada,T. Morie

Proc. Int. Joint Conf. on Neural Networks (IJCNN 2009) 1559 - 1565 2009年06月

A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach, 査読有り

D. Atuti,T. Morie,K. Aihara

IEICE Trans. Fundamentals E92-A ( 5 ) 1308 - 1315 2009年05月

パルス変調方式を用いた電流サンプリング型CMOS任意カオス生成回路,

厚地泰輔,森江隆,合原一幸

電気学会電子回路研究会, ECT-09-19, 25 - 30 2009年01月

時空間ガボールフィルタによる土砂災害前兆現象検知

岡本健,渡辺敏雄,花沢明俊,森江隆,伴弘司,前田裕二

電子情報通信学会パターン認識・メディア理解研究会, PRMU2008-131 108 ( 327 ) 139 - 144 2008年11月

A Prototype System for Secure Human-Machine Interaction Based on Face and Gesture Recognition, 査読有り

I..R. Khan,T. Morie,H. Miyamoto,M. Shimizu,and Y. Kuriya

The 34th Annual Conf. of the IEEE Industrial Electronics Society (IECON'08), 1572 - 1577 2008年11月

時間領域情報処理による脳型集積システム

森江隆,田中秀樹,厚地泰輔,是角圭祐,中田一紀

電子情報通信学会ニューロコンピューティング研究会, NC2008-68 108 ( 281 ) 55 - 60 2008年11月

MOSFETのしきい値電圧の温度依存性を利用した温度補償電流源回路とその応用,

中島規成,森江隆

電気学会C部門電子回路研究会, ECT-08-64 1 - 5 2008年10月

Face and Arm-Posture Recognition for Secure Human-Machine Interaction 査読有り

I. R. Khan,T. Morie,H. Miyamoto

IEEE Int. Conf. on Systems, Man and Cybernetics (SMC2008) 411 - 417 2008年10月

CMOS Pulse-Modulation Circuit Implementation of Phase-Locked Loop Neural Networks, 査読有り

D. Atuti,K. Nakada,T. Morie

IEEE Int. Symp. on Circuits and Systems (ISCAS2008) 2174 - 2177 2008年05月

領域ベース結合MRFモデルによる大局的画像領域分割とCMOS回路実現

川嶋佑輔,厚地泰輔,中田一紀,岡田真人,森江隆

電子情報通信学会ニューロコンピューティング研究会, NC2007-120 107 ( 542 ) 49 - 54 2008年03月

パルス変調方式による相互結合位相振動子のCMOS 回路実現と評価

厚地泰輔,加藤直人,中田一紀,森江隆

電気学会電子回路研究会 25 - 29 2007年12月

STDPを有するCMOSスパイキングニューラルネットワークLSIの評価

田中秀樹,森江隆,合原一幸

電子情報通信学会ニューロコンピューティング研究会, NC2007-61 107 ( 328 ) 37 - 42 2007年11月

Projection-field-type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach 査読有り

O. Nomura,T. Morie

Neural Information Processing (Lecture Notes in Computer Science, Springer Berlin/Heidelberg 4984/2008 1081 - 1090 2007年11月

Projection-field-type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach 査読有り

O. Nomura,T. Morie

14th Int. Conf. on Neural Information Processing (ICONIP2007) 196 - 196 2007年11月

Brain-inspired Visual Processing: Real-time Face Authentication, arm Posture Recognition, and Shadow Elimination 査読有り

T. Morie,H. Miyamoto,A. Hanazawa,I. R. Khan,T. Kamada,Y. Kuriya,and M. Shimizu

4th Int. Conf. on Brain-Inspired Information Technology (BrainIT2007) 33 - 33 2007年11月

An FPGA-based Collision Warning System Using Hybrid Approach 査読有り

H. Liang,T. Morie,Y. Suzuki,K. Nakada,T. Miki,H. Hayashi

7th Int. Conf. on Hybrid Intelligent Systems (HIS07) 30 - 35 2007年09月

CMOS Circuit Implementation of a Coupled Phase Oscillator System Using Pulse Modulation Approach 査読有り

D. Atuti,N. Kato,K. Nakada,T. Morie

2007 European Conference on Circuit Theory and Design (ECCTD 2007) 827 - 830 2007年08月

A Pulse-Modulation Circuit for Nonlinear Systems with Self Regulatory Threshold Dynamics 査読有り

D. Atuti,T. Morie,K. Aihara

15th IEEE Int. Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2007) 145 - 148 2007年07月

Evaluation of a CMOS Spiking Neural Network Circuit with STDP Function 査読有り

H. Tanaka,T. Morie,K. Aihara

15th IEEE Int. Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2007) 313 - 316 2007年07月

A Cellular-Automaton-Based Anisotropic Diffusion Algorithm for Subjective Contour Generation and Its Digital VLSI Implementation 査読有り

T. Morie,T. Yamamoto

Accepted for presentation at 2007 Conference on Unconventional Computing (UC 2007) 2007年07月

Design of a CMOS Pixel Circuit for Coarse Region Segmentation/Extraction Based on Merged Analog/Digital Architecture 査読有り

N. Kato,T. Morie

J. Signal Processing 11 ( 4 ) 317 - 320 2007年07月

Digital VLSI Architecture for Image Matching Based on 2D Cross-correlation 査読有り

M. Mitarai,K. Korekado,T. Morie

J. Signal Processing 11 ( 4 ) 345 - 348 2007年07月

An Element Circuit for Nonlinear Dynamical Systems Using Phase Variables 査読有り

D. Atuti,T. Morie,T. Nakano,K. Nakada

Brain-Inspired IT III, International Congress Series 1301 156 - 159 2007年07月

A CMOS Circuit for STDP with a Symmetric Time Window 査読有り

H. Tanaka,T. Morie,K. Aihara

Brain-Inspired IT III, International Congress Series 1301 152 - 155 2007年07月

Moving Object Detection Algorithm Inspired by the Sequence Detection in the Hippocampus and its Digital LSI Implementation 査読有り

H. Hayashi,K. Nakada,T. Morie

Brain-Inspired IT III, International Congress Series 1301 35 - 38 2007年07月

Brain-inspired Visual Processing for Robust Gesture Recognition 査読有り

T. Morie,H. Miyamoto,A. Hanazawa

Brain-Inspired IT III, International Congress Series 1301 31 - 34 2007年07月

Digital VLSI Implementation of a Moving Object Detection Algorithm Based on Neuronal Propagation in the Hippocampus 査読有り

H. Liang,H. Nakayama,K. Nakada,T. Morie,H. Hayashi

International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2006) 614 - 617 2006年12月

A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms 査読有り

D. Atuti,T. Morie,K. Aihara

IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS 2006) 1961 - 1965 2006年12月

アナログ・デジタル融合回路方式による主観的輪郭生成のための画素並列型CMOS異方性拡散回路

金永宰,森江隆

電子情報通信学会ニューロコンピューティング研究会 106 ( 341 ) 31 - 36 2006年11月

A CMOS Circuit for STDP with a Symmetric Time Windoww 査読有り

H. Tanaka,T. Morie,K. Aihara

Abst. of The 3rd Int. Conf. on Brain-Inspired Information Technology (BrainIT2006) 65 - 65 2006年09月

An Element Circuit for Nonlinear Dynamical Systems Using Phase Variables 査読有り

D. Atuti,T. Morie,T. Nakano,K. Nakada

Abst. of The 3rd Int. Conf. on Brain-Inspired Information Technology (BrainIT2006) 66 - 66 2006年09月

Brain-inspired Visual Processing for Robust Gesture Recognition 査読有り

T. Morie,H. Miyamoto,A. Hanazawa

Abst. of The 3rd Int. Conf. on Brain-Inspired Information Technology (BrainIT2006) 31 - 31 2006年09月

A Real-time Image Processing System Using a Gabor-filtering LSI Realizing Primary Visual Cortex Functions 査読有り

S. Nagano,T. Morie,T. Nakano,K. Nakamura

Joint 3rd Int. Conf. on Soft Computing and Intelligent Systems and 7th Int. Symp. on Advanced Intelligent Systems (SCIS & ISIS 2006) 516 - 519 2006年09月

A CMOS Synapse with STDP Function and Its Application to Hopfield-type Associative Memory 査読有り

H. Tanaka,T. Morie,K. Aihara

Int. Symp. on Nonlinear Theory and its Applications (NOLTA2006) 495 - 498 2006年09月

An FPGA-based Real-time Scene-image Recognition System Using Relationship between Coarsely Segmented Regions 査読有り

T. Morie,T. Nakano

Int. Symp. on Artificial Brain with Emotion and Learning (ISABEL 2006) - Bio-Inspired Models and Hardware for Brain-like Intelligent Functions - 158 - 158 2006年08月

A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory 査読有り

K. Sasaki,T. Morie,A. Iwata

IEICE Transactions on Electronics E89-C ( 11 ) 1637 - 1644 2006年04月

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model based on a Merged/Mixed Analog-Digital Architecture 査読有り

O. Nomura,T. Morie,K. Korekado,T. Nakano,M. Matsugu,A. Iwata

IEICE Transactions on Electronics E89-C ( 6 ) 781 - 791 2006年04月

A Pixel Circuit Implementing an Anisotropic Diffusion Algorithm for Subjective Contour Generation Using Merged Analog-Digital circuit Approach 査読有り

Y. Kim,T. Morie

J. Signal Processing 10 ( 4 ) 259 - 262 2006年04月

An Image Recognition Algorithm Using Relationships between Segmented Coarse Regions 査読有り

T. Nakano,T. Morie

Brain-Inspired IT II, International Congress Series 1291 241 - 244 2006年04月

An Analog CMOS Circuit for Spiking Neuron Models 査読有り

H. Tanaka,T. Morie,K. Aihara

Brain-Inspired IT II, International Congress Series 1291 217 - 220 2006年04月

Subjective Contour Generation Using a Pixel-parallel Anisotropic Diffusion Algorithm 査読有り

Y. Kim,T. Morie

Brain-Inspired IT II, International Congress Series 1291 241 - 244 2006年04月

Face Position Detection by a Convolutional Neural Network Using an Image Filtering Processor VLSI 査読有り

K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata

Brain-Inspired IT II, International Congress Series 1291 253 - 256 2006年04月

Digital VLSI Architecture for Image Matching Based on 2D Cross-correlation 査読有り

M. Mitarai,K. Korekado,T. Morie

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 277 - 280 2006年03月

An FPGA-based Real-time Moving-object Detection System Based on Neuronal Propagation in the Hippocampus 査読有り

H. Liang,T. Morie,H. Nakayama,K. Nakada,H. Hayashi

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 509 - 512 2006年03月

Design of an 2D Image Matching Processor LSI Based on Merged Analog/Digital Architecture 査読有り

M. Sakai,T. Morie,M. Mitarai,K. Korekado

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 81 - 84 2006年03月

Design of a CMOS Pixel Circuit for Coarse Region Segmentation/Extraction Based on Merged Analog/Digital Architecture 査読有り

N. Kato,T. Morie

RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 89 - 92 2006年03月

A Pixel Circuit Implementing an Anisotropic Diffusion Algorithm for Subjective Contour Generation Using Merged Analog-Digital circuit Approach 査読有り

Y. Kim,T. Morie

2006 RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'06) 2006年03月

FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation 査読有り

T. Nakano,T. Morie,H. Ishizu,H. Ando,A. Iwata

Intelligent Automation and Soft Computing 12 ( 3 ) 307 - 316 2006年03月

顔／物体認識のためのElastic Graph MatchingのFPGA実装とその性能評価

中野鉄平,森江隆

電子情報通信学会ニューロコンピューティング研究会 25 - 30 2005年11月

Associative Memory Operation in a Hopfield-type Spiking Neural Network with Modulation of Resting Membrane Potential 査読有り

H. Tanaka,T. Morie,K. Aihara

2005 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2005) 313 - 316 2005年10月

An Image Recognition Algorithm Using Coarse Region Segmentation and Relationship between the Regions 査読有り

T. Nakano,T. Morie

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 81 - 81 2005年10月

Subjective Contour Generation Using a Pixel-parallel Anisotropic Diffusion Algorithm 査読有り

Y. Kim,T. Morie

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 94 - 94 2005年10月

An Analog CMOS Circuit for Spiking Neuron Models 査読有り

H. Tanaka,T. Morie,K. Aihara

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 2005年10月

Face Position Detection Using an Image Filtering Processor VLSI 査読有り

K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 86 - 86 2005年10月

A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach 査読有り

D. Atuti,T. Morie,K. Aihara

Abstracts of Brain-Inspired Information Technology (BrainIT2005) 73 - 73 2005年10月

A Convolutional Neural Network VLSI Architecture Using Sorting Algorithm 査読有り

O. Nomura,T. Morie,K. Korekado,M. Matsugu,A. Iwata

Int. Conf. on Advances in Natural Computation (ICNC'05) 1006 - 1014 2005年08月

A Gabor Filtering VLSI Processor Mimicking a Primary Visual Cortex Function 査読有り

T. Morie,K. Nakamura,K. Korekado

Post-IJCNN2005 Workshop, Biologically-Inspired Models and Hardware for Human-like Intelligent Functions (BIMH2005) 2005年08月

A Digital LSI Architecture of Elastic Graph Matching and Its FPGA Implementation 査読有り

T. Nakano,T. Morie

Proc. Int. Joint Conference on Neural Networks (IJCNN05) 689 - 694 2005年07月

AD融合／混載アーキテクチャによる顔・物体認識のための画像フィルタリングプロセッサ

是角圭祐,森江隆,野村修,中野鉄平,真継優和,岩田穆

電子情報通信学会集積回路研究会 19 - 24 2005年07月

V1単純細胞の機能を模倣するガボールフィルタLSIの評価

中村享平,是角圭祐,森江隆

電子情報通信学会ニューロコンピューティング研究会 17 - 22 2005年06月

An Image Filtering Processor for Face/Object Recognition Using Merged/Mixed Analog-Digital Architecture 査読有り

K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata

2005 Symposium on VLSI Circuits 220 - 223 2005年06月

A Pixel-parallel Anisotropic Diffusion Algorithm for Subjective Contour Generation 査読有り

Y. Kim,T. Morie

IEEE Int. Symp. on Circuits and Systems (ISCAS2005) 4237 - 4240 2005年05月

A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation 査読有り

T. Nakano,T. Morie,M. Nagata,A. Iwata

J. Robotics and Mechatronics 17 ( 4 ) 378 - 386 2005年04月

投射野型積和演算及び荷重基底分解アルゴリズムを用いたConvolutional Neural Network VLSI アーキテクチャ

野村修,森江隆,是角圭祐,真継優和,岩田穆

電子情報通信学会ニューロコンピューティング研究会 25 - 29 2004年11月

主観的輪郭生成のための画素並列型異方性拡散アルゴリズム

金永宰,森江隆

映像情報メディア学会技術報告 41 - 44 2004年10月

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition 査読有り

O. Nomura,T. Morie,K. Korekado,M. Matsugu,and A. Iwata

Int. Conf. on Knowledge-Based Intelligent Information and Engineering Systems (KES'2004) 995 - 1001 2004年09月

A Face/Object Recognition System Using Coarse Region Segmentation and Dynamic-Link Matching 査読有り

T. Morie,T. Nakano

Brain-Inspired IT I, International Congress Series 1269 177 - 180 2004年09月

Hardware Modeling and Design of Brain-like Information Systems 査読有り

T. Miki,T. Morie,and T. Yamakawa

Joint 2nd Int. Conf. on Soft Computing and Intelligent Systems and 5th Int. Symposium on Advanced Intelligent Systems (SCIS & ISIS 2004) 2004年09月

AD融合回路方式による画素並列型ガボールフィルタLSI

森江隆,梅澤淳,岩田穆

電子情報通信学会信学技報 2004年08月

A Spiking Neural Network with Negative Thresholding and Its Application to Associative Memory 査読有り

K. Sasaki,T. Morie,and A. Iwata

2004 IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS2004) IIー89 - IIIー92 2004年07月

Gabor Filtering Using Cellular Neural Networks and its Application to Face/Object Recognition 査読有り

T. Morie,T. Nakano,J. Umezawa,and A. Iwata

World Automation Congress 2004年07月

A Pixel-Parallel Image Processor for Gabor Filtering Based on Merged Analog-Digital Architecture 査読有り

T. Morie,J. Umezawa,and A. Iwata

2004 Symposium on VLSI Circuits 212 - 213 2004年06月

Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps 査読有り

T. Morie,K Murakoshi,M Nagata,A. Iwata

IEICE Trans. Electron. E87-C ( 11 ) 1856 - 1862 2004年04月

A VLSI Convolutional Neural Network for Image Recognition Using　Merged/Mixed Analog-Digital Architecture 査読有り

K. Korekado,T. Morie,O. Nomura,H. Ando,T. Nakano,M. Matsugu,A. Iwata

J. Intelligent & Fuzzy Systems 15 ( 3/4 ) 173 - 179 2004年04月

Gabor-Type Filtering Using Transient States of Cellular Neural Networks 査読有り

T. Morie,J. Umezawa,A. Iwata

Intelligent Automation and Soft Computing 10 ( 2 ) 95 - 104 2004年04月

A Face/Object Recognition System Using Coarse Region Segmentation and Dynamic-Link Matching 査読有り

T. Morie,T. Nakano

Brain-Inspired IT I, International Congress Series 1269 177 - 180 2004年04月

A Face/Object Recognition System Using Coarse Region Segmentation and Dynamic-Link Matching 査読有り

T. Morie,T. Nakano

International Symposium on Bio-Inspired Systems, Part IV, Brain-inspired Information Technology (BrainIT 2004) 2004年03月

抵抗ネットワークの過渡状態を利用するガボール型フィルタ回路

森江隆,梅澤淳,岩田穆

電子情報通信学会信学技報 13 - 18 2003年11月

減衰シナプスを導入したスパイキングニューロンによるホップフィールドネットワークを用いた高速連想メモリ

佐々木寛弥,森江隆,岩田穆

電子情報通信学会信学技報 55 - 60 2003年11月

A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture 査読有り

K. Korekado,T. Morie,O. Nomura,H. Ando,T. Nakano,M. Matsugu,A. Iwata

Knowledge-Based Intelligent Information and Engineering Systems （KES2003） 2 169 - 176 2003年09月

A Face/Object Recognition System Using FPGA Implementation of Coarse Region Segmentation 査読有り

T. Nakano,T. Morie,and A. Iwata

SICE Annual Conference 2003 1418 - 1423 2003年08月

Coarse Image Region Segmentation Using Resistive-fuse Networks Implemented in FPGA 査読有り

T. Nakano,H. Ando,H. Ishizu,T. Morie,A. Iwata

The 7th World Multiconference on Systemics, Cybernetics and Informatics （SCI 2003） Proceedings IV 186 - 191 2003年07月

A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models 査読有り

T. Morie,T. Matsuura,M. Nagata,A. Iwata

IEEE Transactions on Nanotechnology 2 ( 3 ) 158 - 164 2003年04月

Pulse Modulation VLSI Implementation of Clustering Algorithm Based on Stochastic Association Model 査読有り

T. Morie,T. Matsuura,A. Iwata

Artificial Neural Networks and Neural Information Processing ICANN/ICONIP 2003 International Conference Supplementary Proceedings 434 - 437 2003年04月

大局的画像領域分割のためのデジタル方式抵抗ヒューズネットワークの設計とFPGAへの実装

中野鉄平,森江隆,安藤博士,石津任章,岩田穆

電子情報通信学会技術研究報告(ICD) 2003年03月

パルスタイミングに基づくスパイキングホップフィールドネットワークによる高速連想メモリ

佐々木寛弥,森江隆,伊井慎一郎,岩田穆

電子情報通信学会技術研究報告(NC) 2002年11月

A Cellular-Automaton-Type Image Extraction Algorithm and Its Implementation Using an FPGA 査読有り

T. Nakano,T. Morie,M. Nagata,A. Iwata

Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems 2 197 - 200 2002年10月

自律移動ロボット用のビジョンシステムと画素選択処理機能を有する並列マッチングプロセッサの開発

山本美子,武田幹雄,渡部悠紀,岩田穆,森江隆,渡邊睦

電子情報通信学会技術研究報告（DSP,ICD,IE） 2002年10月

画像処理IPとFPGA実装

石津任章,武田幹雄,馬場祥宏,佐野誠,藤原義也,原正純,森江隆,岩田穆

電子情報通信学会技術研究報告（DSP,ICD,IE） 2002年10月

An Image Region Extraction LSI Based on a Merged/Mixed-Signal Nonlinear Oscillator Network Circuit 査読有り

H. Ando,T. Morie,M. Nagata,A. Iwata

28th European Solid-State Circuits Conference 703 - 706 2002年09月

適応型CMOSイメージセンサ

今村俊文,山本美子,岩田穆,石津任章,森江隆

電子情報通信学会技術研究報告(ICD) 2002年09月

An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing 査読有り

K. Katayama,M. Nagata,T. Morie,A. Iwata

IEICE Transactions on Electronics E85-C ( 8 ) 1596 - 1603 2002年08月

A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models 査読有り

T. Morie,T. Matsuura,M. Nagata,A. Iwata

2002 IEEE Silicon Nanoelectronics Workshop 53 - 54 2002年06月

A Multi-Nano-Dot Circuit and Structure Using Thermal-Noise Assisted Tunneling for Stochastic Associative Processing 査読有り

T. Morie,T. Matsuura,M. Nagata,A. Iwata

Journal of Nanoscience and Nanotechnology 2 ( 3 ) 343 - 349 2002年06月

Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits 査読有り

M. Nagata,T. Morie,A. Iwata

IEEE 2002 Custom Integrated Circuit Conference 501 - 504 2002年05月

Image Segmentation/Extraction Using Nonlinear Cellular Networks and their VLSI Implementation Using Pulse-Modulation Techniques 査読有り

未入力

IEICE Trans. Fundamentals E85-A ( 2 ) 381 - 388 2002年04月

An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures 査読有り

T. Morie,T. Matsuura,M. Nagata,and A. Iwata

Advances in Neural Information Processing Systems 14,MIT Press 1115 - 1122 2002年04月

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models 査読有り

M. Nagata,Y. Murasaka,Y. Nishimori,T. Morie,and A. Iwata

Proc. 7th Asia and South Pacific Design Automation Conference 71 - 76 2002年04月

アナログ・ディジタル融合回路による視覚情報処理アーキテクチャ（特別招待論文）

岩田穆,森江隆

電子情報通信学会信学技報 2002年04月

Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits 査読有り

未入力

IEEE Journal of Solid-State Circuits 36 ( 3 ) 539 - 549 2001年04月

Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications 査読有り

未入力

IEICE Transactions on Fundamentals E84-A ( 2 ) 486 - 496 2001年04月

A PWM Analog Memory Programming Circuit for Floating-Gate MOSFETs with 75us Programming Time and 11b Updating Resolution 査読有り

未入力

IEEE Journal of Solid-State Circuits 36 ( 8 ) 1286 - 1290 2001年04月

A CMOS Stochastic Associative Processor Using PWM Chaotic Signals 査読有り

未入力

IEICE Trans. Electronics E84-C ( 12 ) 1723 - 1729 2001年04月

Test Circuits for Substrate Noise Evaluation in CMOS Digital ICs 査読有り

未入力

Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC2001) 13 - 14 2001年04月

A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation 査読有り

未入力

Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials(SSDM2001) 90 - 91 2001年04月

Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies 査読有り

未入力

Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials (SSDM2001) 88 - 89 2001年04月

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation 査読有り

未入力

Proceedings of International Symposium on Quality Electronic Design (ISQED2001) 482 - 487 2001年04月

Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits 査読有り

未入力

Symposium on VLSI Circuits 159 - 162 2001年04月

Design of a Pixel-Parallel Feature Extraction VLSI System for Biologically-Inspired Object Recognition Methods 査読有り

未入力

Proc. International Symposium on Nonlinear Theory and its Application (NOLTA2001) 371 - 374 2001年04月

A Nonlinear Oscillator Network for Gray-level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation 査読有り

未入力

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E83-A ( 2 ) 329 - 336 2000年04月

Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment 査読有り

未入力

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19 ( 6 ) 671 - 678 2000年04月

Wafer-assisted Repair of Plasma-induced damage in the Silicon/Silicon-dioxide System 査読有り

未入力

Journal of Vacuum Science & Technology B 18 ( 3 ) 1268 - 1275 2000年04月

CMOS Circuits Generating Arbitrary Chaos by Using Pulse Width Modulation Techniques 査読有り

未入力

IEEE Transactions on Circuits and Systems-I 47 ( 11 ) 1652 - 1657 2000年04月

Quantum Dot Structures Measuring Hamming Distance for Associative Memories 査読有り

未入力

Superlattices & Microstructures 27 ( 5/6 ) 613 - 616 2000年04月

A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors 査読有り

未入力

Nanotechnology 11 ( 3 ) 154 - 160 2000年04月

A Smart Imager for the Vision Processing Front-end 査読有り

未入力

Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC2000) 19 - 20 2000年04月

Reduced Substrate Noise Digital Design for Improving Embedded Analog Performance 査読有り

未入力

2000 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC2000) 224 - 225 2000年04月

A Multi-Functional Cellular Neural Network Circuit Using Pulse Modulation Signals for Image Recognition 査読有り

未入力

Proceedings of 7th International Conference on Neural Information Processing (ICONIP-2000) 613 - 617 2000年04月

A High-Resolution Hadamard Transform Circuit Using Pulse Width Modulation Technique 査読有り

未入力

Extended Abstracts of the 2000 InternationalConference on Solid State Devices and Materials (SSDM2000) 366 - 367 2000年04月

A Multi-Quantum-Dot Associative Circuit Using Thermal-Noise Assisted Tunneling 査読有り

未入力

Extended Abstracts of the 2000 InternationalConference on Solid State Devices and Materials (SSDM2000) 306 - 307 2000年04月

Quantitative Characterization of Substrate Noise for Physical Design Guides in Digital Circuits 査読有り

未入力

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (CICC2000) 95 - 98 2000年04月

Pulse Modulation Circuit Architecture and its Application to Functional Image Sensors 査読有り

未入力

Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS2000) Ⅱ 301 - 304 2000年04月

Quantum Dot Structures Measuring Hamming Distance for Associative Memories 査読有り

未入力

Extended Abstracts, 4th International Workshop on Quantum Functional Devices (QFD2000) 210 - 213 2000年04月

Image Object Extraction using Resistive-Fuse and Oscillator Networks and a Pulse-Modulation Circuit for their LSI Implementation 査読有り

未入力

Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials (SSDM2000) 368 - 369 2000年04月

An Arbitrary Chaos Generator Core Circuit Using PWM/PPM Signals 査読有り

未入力

Proceedings of the Asia and South Pacific Design Automation Conference(ASP-DAC2000) 23 - 24 2000年04月

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique 査読有り

未入力

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E82-A ( 2 ) 356 - 363 1999年04月

The Architecture of Delta Sigma Analog-to-Digital Converter using Voltage-Controlled Oscillator as a Multibit Quantizer 査読有り

未入力

IEEE Transactions on Circuits and Systems-II 46 ( 7 ) 941 - 945 1999年04月

New Non-Volatile Analog Memory Circuits Using PWM Methods 査読有り

未入力

IEICE Transactions on Electronics E82-C ( 9 ) 1655 - 1661 1999年04月

Analog LSI Implementation of Self-Learning Neural Networks 査読有り

未入力

Computers and Electrical Engineering 25 ( 5 ) 339 - 355 1999年04月

Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment 査読有り

未入力

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (CICC'99) 575 - 578 1999年04月

A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation 査読有り

未入力

Extended Abstracts of the 1999 InternationalConference on Solid State Devices and Materials (SSDM'99) 98 - 99 1999年04月

A Nonlinear Oscillator Network Circuit for Image Segmentation with Double-threshold Phase Detection 査読有り

未入力

9th International Conference on Artificial Neural Networks(ICANN'99) 655 - 660 1999年04月

Nonlinear Dynamical Systems Utilizing Pulse Modulation Signals and A CMOS Chip Generating Arbitrary Chaos 査読有り

未入力

Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-inspired Systems (MicroNeuro'99) 254 - 260 1999年04月

A Stochastic Association Circuit Using PWM Chaotic Signals 査読有り

未入力

Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials (SSDM'99) 100 - 101 1999年04月

A Smart CMOS Imager with Pixel Level PWM Signal Processing 査読有り

未入力

1999 Symposium on VLSI Circuits Digest of Technical Papers 141 - 144 1999年04月

A Stochastic Associative Memory Using Single-Electron Tunneling Devices 査読有り

未入力

IEICE Transactions on Electronics E81-C ( 1 ) 30 - 35 1998年04月

Pulse Modulation Circuit Techniques for Nonlinear Dynamical Systems 査読有り

未入力

Proceedings 1998 International Symposium on Nonlinear Theory and its Application (NOLTA'98) 447 - 450 1998年04月

Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation 査読有り

未入力

Proceedings of the 5th International Conference on Neural InformationProcessing (ICONIP'98) 582 - 585 1998年04月

An Architecture of Delta-Sigma A-to-D Converters using a Voltage Controlled Oscillator as a Multi-bit Quantizer 査読有り

未入力

Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'98) I 389 - 392 1998年04月

Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Methods 査読有り

未入力

Proceedings of the 5th International Conference on Neural Information Processing (ICONIP'98) 586 - 589 1998年04月

LSI Implementation of Neural Networks Using A Pulse-Width Modulation Method 査読有り

未入力

Proceedings of the 5th International Conference on Soft Computing and Information/Intelligent Systems (IIZUKA'98) 118 - 121 1998年04月

Stochastic Associative Memory Using Single-Electron Devices and Its Application to Digit Pattern Association 査読有り

未入力

Extended Abstracts of the 1998 International Conference on Solid State Devices and Materials (SSDM'98) 190 - 191 1998年04月

Novel Line-Test Methods Using A Subscriber Line Interface Circuit

未入力

Electronics and Communications in Japan, Part 1 81 ( 1 ) 22 - 30 1998年04月

Nonlinear function generators and chaotic signal generators using a pulse-width modulation method 査読有り

未入力

Electronics Letters 33 ( 16 ) 1351 - 1352 1997年04月

Self-Learning Neural Network LSI with High-Resolution Non-Volatile Analog Memory 査読有り

未入力

Proceedings International Conference on Neural Networks (ICNN'95) IV 1628 - 1632 1995年04月

Analog LSI Implementation of Self-Learning Neural Networks 査読有り

未入力

Proceedings of the 3rd International Conference on Fuzzy Logic, Neural Nets and Soft Computing (IIZUKA'94) 565 - 566 1994年04月

Analog VLSI Implementation of Adaptive Algorithms by an Extended Hebbian Synapse Circuit 査読有り

未入力

Proceedings of Third Australian Conference on Neural Networks (ACNN'92) 21 - 24 1992年04月

A Submicrometer Megabit DRAM Process Technology Using Trench Capacitors 査読有り

未入力

IEEE J. Solid-State Circuits SC-20 ( 1 ) 130 - 136 1985年04月

Electrical Characteristics of Isolation-Merged Vertical Capacitor (IVEC) Cell 査読有り

未入力

1985 Symposium on VLSI Technology Digest of Technical Papers 88 - 89 1985年04月

Trench Coverage Characteristics of Polysilicon Deposited by Thermal Decomposition of Silane 査読有り

未入力

Japanese Journal of Applied Physics 23 ( 7 ) L482 - L484 1984年04月

An Isolation-merged Vertical Capacitor Cell for Large Capacity DRAM 査読有り

未入力

Proceedings of the International Electron Device Meeting (IEDM'84) 240 - 243 1984年04月

Depletion Trench Capacitor Technology for Megabit Level MOS dRAM 査読有り

未入力

IEEE Electron Device Letters 4 ( 11 ) 411 - 414 1983年04月

Depletion Trench Capacitor Cell 査読有り

未入力

Extended Abstracts of 15th Conference Solid State Devices and Materials (SSDM'83) 253 - 256256 1983年04月

　前のページ-次のページ　

<森江 隆>

論文 - 森江 隆

<森江　隆>

論文 - 森江　隆