研究者詳細 - 森江　隆

論文 - 森江　隆

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Robustness of Spiking Neural Networks based on Time-To-First-Spike Encoding against Adversarial Attacks 査読有り国際誌

Nomura O., Sakemi Y., Hosomi T., Morie T.

IEEE Transactions on Circuits and Systems II: Express Briefs 2022年06月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

Spiking neural networks (SNNs) more closely mimic the human brain than artificial neural networks (ANNs). For SNNs, time-to-first-spike (TTFS) encoding, which represents the output values of neurons based on the timing of a single spike, has been proposed as a promising model to reduce power consumption. Adversarial attacks that can lead ANNs to misrecognize images have been reported in many studies. However, the characteristics of TTFS-based SNNs trained using a backpropagation algorithm against adversarial attacks have not yet been clarified. In particular, the dependence of the robustness against adversarial attacks on spike timings has not been investigated. In this study, we investigated the robustness of SNNs against adversarial attacks and compared it with that of an ANN. We found that SNNs trained with the appropriate temporal penalty settings are more robust against adversarial images than ANNs.

DOI： 10.1109/TCSII.2022.3184313

Scopus

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A Memory-Based Entorhinal-Hippocampal Model and its FPGA Implementation by On-Chip RAMs 査読有り国際誌

I. Kawashima, K. Tateno, T. Morie, H. Tamukoh

Int. Symp. on Circuits and Systems (ISCAS 2022) ( IEEE ) 2022年05月

A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing 査読有り国際誌

Y. Sakemi, K. Morino, T. Morie, T. Hosomi, K. Aihara

Int. Symp. on Circuits and Systems (ISCAS 2022) ( IEEE ) 2022年05月

A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing 査読有り国際誌

Nakagawa H., Tateno K., Takada K., Morie T.

IEEE Access 10 43003 - 43012 2022年04月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

To solve a navigation task based on experiences, we need a mechanism to associate places with objects and recall them along the course of action. In a reward-oriented task, if the route to a reward location is simulated in mind after experiencing it once, it might be possible that the reward is gained efficiently. One way to solve this is to incorporate a biologically plausible mechanism. In this study, we propose a neural network that stores a sequence of events associated with a reward. The proposed network recalls the reward location by tracing them in its mind in order. We simulated a virtual mouse that explores a figure-eight maze and recalls the route to the reward location. During the learning period, a sequence of events related to firing along a passage was temporarily stored in the heteroassociative network, and the sequence of events is consolidated in the synaptic weight matrix when a reward is fed. For retrieval, an impetus input internally generates the sequential activation of conjunctive cue-place cells toward the reward location. In the figure-eight maze task, the location of the reward was estimated by mind travel, irrespective of whether the reward is in the counterclockwise or distant clockwise route. The mechanism of efficiently reaching the goal by mind travel in the brain based on experiences is beneficial for mobile service robots that perform autonomous navigation.

DOI： 10.1109/ACCESS.2022.3168715

Scopus

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An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing 査読有り国際誌

Kawashima I., Katori Y., Morie T., Tamukoh H.

International Conference on Field-Programmable Technology (ICFPT 2021) 2021年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In our work, a new area-efficient multiply-accumulation scheme for time-domain neural processing named differential multiply-accumulation is proposed. Our new scheme reduces hardware resources utilization of multiply-accumulation with suppressing the increasing computational time resulting from the time-multiplexing. As a result, 2,048 neurons of fully connected CBM and RC-CBM were synthesized for a single field-programmable gate array (FPGA).

DOI： 10.1109/ICFPT52863.2021.9609809

Scopus

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Brain-inspired neural network navigation system with hippocampus, prefrontal cortex, and amygdala functions 査読有り国際誌

Mizutani A., Tanaka Y., Tamukoh H., Katori Y., Tateno K., Morie T.

International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2021) 2021年11月

担当区分：最終著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We propose a brain-inspired neural network model consisting of the hippocampus, prefrontal cortex, and amygdala models for a navigation system that acquires specific knowledge in home environments from few experiences. The proposed model was evaluated in a home environment using a robot simulator. In the experiment, the robot determines a path for navigation based on the knowledge acquired by the brain-inspired model.

DOI： 10.1109/ISPACS51563.2021.9651058

Scopus

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A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design 査読有り国際誌

Sakemi Y., Morino K., Morie T., Aihara K.

IEEE Transactions on Neural Networks and Learning Systems ( IEEE ) 2021年07月

記述言語：英語掲載種別：研究論文（学術雑誌）

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms but also energy-efficient computational models when implemented in very-large-scale integration (VLSI) circuits. In this article, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultrahigh energy efficiency can be achieved. We also propose several techniques to improve the performance on recognition tasks and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST and Fashion-MNIST datasets. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.

DOI： 10.1109/TNNLS.2021.3095068

Scopus

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An Energy-efficient Time-domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-width Modulation Approach 査読有り国際誌

Yamaguchi M., Iwamoto G., Nishimura Y., Tamukoh H., Morie T.

IEEE Access 2020年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

DOI： 10.1109/ACCESS.2020.3047619

Scopus

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An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots 査読有り国際誌

Tanaka Y., Morie T., Tamukoh H.

IEEE Access 8 212066 - 212078 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

This study develops an intelligent system for home service robots mimicking human brain function that can manage common knowledge applicable to any environment and local knowledge reflecting its specific environment. Deep learning is effective for acquiring common knowledge because the performance of deep learning relies on the amounts of training and big training data that can be accessed for such knowledge; however, deep learning is ineffective for acquiring local knowledge because no big training data for such knowledge exist. Thus, we propose a brain-inspired learning model and system for acquiring local knowledge using small training data. We focus on the amygdala because its classical fear conditioning is effective for training using small training data. We propose an amygdala-inspired classical conditioning model comprising multiple self-organizing maps (lateral nucleus) and a fully connected neural network (central nucleus), imitating the function and structure of the amygdala. The proposed model is applied to a task of a waiter robot in a restaurant, and the model can learn customers' preferences after only a few human-robot interactions. We accelerate the computation of the model and reduce its power consumption by proposing a hardware-oriented algorithm for the model and its digital hardware design and implement it in an XCZU9EG field programmable gate array. The hardware-oriented algorithm reduces the multiplication operations and exponential functions requiring huge hardware resources. The performance of the hardware operated at 150 MHz is 1,273 times faster than the software implementation on Arm Cortex-A53, and the power consumption of the chip is 5.009 W.

DOI： 10.1109/ACCESS.2020.3038161

Scopus

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FPGA implementation of hardware-oriented chaotic Boltzmann machines 査読有り国際誌

Kawashima I., Morie T., Tamukoh H.

IEEE Access 8 204360 - 204377 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

DOI： 10.1109/ACCESS.2020.3036882

Scopus

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A Time-domain Analog Weighted-sum Calculation Circuit Using Ferroelectric-gate Field-effect Transistors for Artificial Intelligence Processors 招待有り査読有り国際誌

M, Harada, M, Takahashi, S. Sakai, T. Morie

Japanese Journal of Applied Physics 59 ( 4 ) 040604-1 - 040604-12 2020年04月

A Chaotic Boltzmann Machine Working as a Reservoir and Its Analog VLSI Implementation 査読有り

Yamaguchi M., Katori Y., Kamimura D., Tamukoh H., Morie T.

Proceedings of the International Joint Conference on Neural Networks 2019-July 2019年07月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Reservoir computing is attracting great interest because of its high computing ability especially for time-series prediction, despite its simple structure and learning scheme. This paper proposes a reservoir computing hardware model using a chaotic Boltzmann machine (CBM) as the reservoir, which can achieve complex motion in a dynamical system on a high-dimensional hypercube. The CBM uses analog nonlinear dynamics, unlike the stochastic operation of the original Boltzmann machine model. To utilize CBMs as a reservoir, chaotic operation must be suppressed, and the echo state property should be satisfied. We modify the CBM model for simpler analog complementary metal-oxide-semiconductor very-large-scale integration (CMOS VLSI) implementation, and propose its use as a reservoir by adding an external reference clock signal. We then verify its proper operation by numerical simulation. We also refine the CMOS VLSI circuit design based on the proposed modified CBM model to improve power consumption and calculation precision.

DOI： 10.1109/IJCNN.2019.8852325

Scopus

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ニューロモルフィックシステムと物理デバイス招待有り査読有り

森江隆

応用物理 ( 公益社団法人応用物理学会 ) 88 ( 7 ) 481 - 485 2019年07月

担当区分：筆頭著者,　責任著者記述言語：日本語掲載種別：記事・総説・解説・論説等（学術雑誌）

<p>本稿では，人工知能（AI）に関連して頻繁に聞く「ニューロモルフィックシステム」や「スパイキングニューロンモデル」について，その意味，歴史，現在の位置づけを紹介します．また，それらの実現へ向けてどのような処理モデルが提案され，どのようなデバイスが求められているかを解説します．AIに対して応用物理の材料・デバイス分野がどのように貢献できるのか，本稿がそれを考えるヒントになれば幸いです．</p>

DOI： 10.11470/oubutsu.88.7_481

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007709468

Reservoir Computing Based on Dynamics of Pseudo-Billiard System in Hypercube 査読有り

Katori Y., Tamukoh H., Morie T.

Proceedings of the International Joint Conference on Neural Networks 2019-July 2019年07月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE. Reservoir computing (RC) is a framework for constructing recurrent neural networks with simple training rule and sparsely and randomly connected nonlinear units. The network (called reservoir) generates complex motion that can be used for many tasks including time series generation and prediction. We construct a reservoir based on the dynamics of the pseudo-billiard system that produce complex motion in a high-dimensional hypercube. In particular, we use the chaotic Boltzmann machine (CBM) whose units exhibit chaotic behavior in the hypercube. The units interact with each other in a time-domain manner through its binary state, and thus an efficient hardware implementation of the system is expected. In order to utilize the CBM as the reservoir, it is necessary to control its chaotic behavior for ensuring the echo state property of RC and establish encoding and decoding for input and output signal. For this purpose, we introduce a reference clock and analyze effects and properties of the reference input. We evaluate the proposed model on the time series generation tasks and show that the model works properly on a broad range of parameter values. Our approach presents a novel mechanism for time-domain information processing and a fundamental technology for a brain like artificial intelligence system.

DOI： 10.1109/IJCNN.2019.8852329

Scopus

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Live demonstration: A VLSI implementation of time-domain analog weighted-sum calculation model for intelligent processing on robots 査読有り国際誌

Yamaguchi M., Iwamoto G., Abe Y., Tanaka Y., Ishida Y., Tamukoh H., Morie T.

IEEE International Symposium on Circuits and Systems (ISCAS 2019) 2019-May 2019年05月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 IEEE This live demonstration presents a VLSI chip based on “Time-domain Analog Computing with Transient states (TACT)” approach for intelligent processing on robots. This TACT chip, fabricated using 250-nm CMOS technology, implements a time-domain analog weighted-sum calculation model with very high energy efficiency. We integrate the TACT chip into a robot via Robot Operating System (ROS) interfaces. A human tracking robot demonstration is performed by the TACT chip with energy efficiency of 300 TOPS/W.

DOI： 10.1109/ISCAS.2019.8702222

Scopus

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A CMOS Chaotic Boltzmann Machine Circuit and Three-neuron Network Operation 査読有り国際誌

M. Yamaguchi, H. Tamukoh, H. Suzuki, T. Morie

Proc. Int. Joint Conf. on Neural Networks (IJCNN 2017) 1218 - 1224 2017年06月

Silicon Nanodisk Array with a Fin Field-effect Transistor for Time-domain Weighted Sum Calculation toward Massively Parallel Spiking Neural Networks,, 査読有り国際誌

T. Tohara, H. Liang, H. Tanaka, M. Igarashi, S. Samukawa, K. Endo, Y. Takahashi, T. Morie

Applied Physics Express Vol. 9 ( No. 3 ) 034201 2016年02月

Parameterized Digital Hardware Design of Pulse-coupled Phase Oscillator Networks 査読有り国際誌

Y. Suedomi, H. Tamukoh, K. Matsuzaka, M. Tanaka, T. Morie

Neurocomputing 165 54 - 62 2015年10月

A PWM-mode Pixel-parallel Image Processing Circuit Performing Directional State-propagation and Its Application to Subjective Contour Generation 査読有り国際誌

Y. Kim, T. Morie

Circuits, Systems & Signal Processing 34 ( 2 ) 605 - 623 2015年02月

VLSI Implementation of a Coupled MRF Model Using Pulse-coupled Phase Oscillators 査読有り国際誌

K. Matsuzaka, H. Tanaka, S. Ohkubo, T. Morie

Electronics Letters 51 ( 1 ) 46 - 48 2015年01月

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論文 - 森江　隆