論文 - 森江 隆
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An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing 査読有り
K. Katayama,M. Nagata,T. Morie,A. Iwata
IEICE Transactions on Electronics E85-C ( 8 ) 1596 - 1603 2002年08月
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A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models 査読有り
T. Morie,T. Matsuura,M. Nagata,A. Iwata
2002 IEEE Silicon Nanoelectronics Workshop 53 - 54 2002年06月
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A Multi-Nano-Dot Circuit and Structure Using Thermal-Noise Assisted Tunneling for Stochastic Associative Processing 査読有り
T. Morie,T. Matsuura,M. Nagata,A. Iwata
Journal of Nanoscience and Nanotechnology 2 ( 3 ) 343 - 349 2002年06月
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Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits 査読有り
M. Nagata,T. Morie,A. Iwata
IEEE 2002 Custom Integrated Circuit Conference 501 - 504 2002年05月
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Image Segmentation/Extraction Using Nonlinear Cellular Networks and their VLSI Implementation Using Pulse-Modulation Techniques 査読有り
未入力
IEICE Trans. Fundamentals E85-A ( 2 ) 381 - 388 2002年04月
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An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures 査読有り
T. Morie,T. Matsuura,M. Nagata,and A. Iwata
Advances in Neural Information Processing Systems 14,MIT Press 1115 - 1122 2002年04月
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Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models 査読有り
M. Nagata,Y. Murasaka,Y. Nishimori,T. Morie,and A. Iwata
Proc. 7th Asia and South Pacific Design Automation Conference 71 - 76 2002年04月
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アナログ・ディジタル融合回路による視覚情報処理アーキテクチャ（特別招待論文）
岩田穆,森江隆
電子情報通信学会 信学技報 2002年04月
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Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits 査読有り
未入力
IEEE Journal of Solid-State Circuits 36 ( 3 ) 539 - 549 2001年04月
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Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications 査読有り
未入力
IEICE Transactions on Fundamentals E84-A ( 2 ) 486 - 496 2001年04月
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A PWM Analog Memory Programming Circuit for Floating-Gate MOSFETs with 75us Programming Time and 11b Updating Resolution 査読有り
未入力
IEEE Journal of Solid-State Circuits 36 ( 8 ) 1286 - 1290 2001年04月
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A CMOS Stochastic Associative Processor Using PWM Chaotic Signals 査読有り
未入力
IEICE Trans. Electronics E84-C ( 12 ) 1723 - 1729 2001年04月
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A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation 査読有り
未入力
Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials(SSDM2001) 90 - 91 2001年04月
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Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies 査読有り
未入力
Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials (SSDM2001) 88 - 89 2001年04月
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Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation 査読有り
未入力
Proceedings of International Symposium on Quality Electronic Design (ISQED2001) 482 - 487 2001年04月
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Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits 査読有り
未入力
Symposium on VLSI Circuits 159 - 162 2001年04月
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Design of a Pixel-Parallel Feature Extraction VLSI System for Biologically-Inspired Object Recognition Methods 査読有り
未入力
Proc. International Symposium on Nonlinear Theory and its Application (NOLTA2001) 371 - 374 2001年04月
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Test Circuits for Substrate Noise Evaluation in CMOS Digital ICs 査読有り
未入力
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC2001) 13 - 14 2001年04月
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A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors 査読有り
未入力
Nanotechnology 11 ( 3 ) 154 - 160 2000年04月
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A Nonlinear Oscillator Network for Gray-level Image Segmentation and PWM/PPM Circuits for Its VLSI Implementation 査読有り
未入力
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E83-A ( 2 ) 329 - 336 2000年04月