研究者詳細 - 森江　隆

論文 - 森江　隆

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Reconstructing bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems 査読有り

Itoh Y., Uenohara S., Adachi M., Morie T., Aihara K.

Chaos 30 ( 1 ) 2020年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2020 Author(s). Bifurcation-diagram reconstruction estimates various attractors of a system without observing all of them but only from observing several attractors with different parameter values. Therefore, the bifurcation-diagram reconstruction can be used to investigate how attractors change with the parameter values, especially for real-world engineering and physical systems for which only a limited number of attractors can be observed. Although bifurcation diagrams of various systems have been reconstructed from time-series data generated in numerical experiments, the systems that have been targeted for reconstructing bifurcation diagrams from time series measured from physical phenomena so far have only been continuous-time dynamical systems. In this paper, we reconstruct bifurcation diagrams only from time-series data generated by electronic circuits in discrete-time dynamical systems with different parameter values. The generated time-series datasets are perturbed by dynamical noise and contaminated by observational noise. To reconstruct the bifurcation diagrams only from the time-series datasets, we use an extreme learning machine as a time-series predictor because it has a good generalization property. Hereby, we expect that the bifurcation-diagram reconstruction with the extreme learning machine is robust against dynamical noise and observational noise. For quantitatively verifying the robustness, the Lyapunov exponents of the reconstructed bifurcation diagrams are compared with those of the bifurcation diagrams generated in numerical experiments and by the electronic circuits.

DOI： 10.1063/1.5119187

Scopus

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超立方体上の疑似ビリヤードダイナミクスに基づくレザバー計算のFPGA実装

山本大智, 川島一郎, 田向権, 森江隆, 香取勇一

人工知能学会全国大会論文集 ( 一般社団法人人工知能学会 ) 2020 ( 0 ) 3Rin422 - 3Rin422 2020年01月

記述言語：日本語掲載種別：研究論文（その他学術会議資料等）

レザバー計算(RC)はリカレントニューラルネットワーク(RNN)の枠組みの1つで，時系列データの処理を目的に応用されている．機械学習モデルに対して，ディジタル回路実装を行うことで高速な演算速度を省電力で実現することが期待できる．香取らはディジタル回路との親和性が高いレザバー計算モデルを提案した．しかし，香取らのモデルをField Programmable Gate Array(FPGA)のようなディジタル回路に実装する場合，ニューロン数の変更に大きな制限が発生する．小規模な回路実装を行う手法として川嶋らがカオスボルツマンマシンのディジタル回路実装に用いたハードウェア指向アルゴリズムを提案している．本研究では川嶋らの提案したハードウェア指向アルゴリズムを基に対象のレザバー計算モデルを改良することで，ディジタル回路実装における回路リソースの消費を軽減可能なモデルを構築した．また，本研究のハードウェア指向アルゴリズムにより、レザバー計算の高速化の実現、人工知能構築のための新しいプラットフォームの確立が期待される．

DOI： 10.11517/pjsai.JSAI2020.0_3Rin422

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007857093

Hippocampus Model for Episodic Memory Processing Using Associative Memory 査読有り

立野勝巳, 森江隆

The proceedings of NOLTA2020 - 138 2020年01月

Prediction of Sensory Information and Generation of Motor Commands for Autonomous Mobile Robots Using Reservoir Computing 査読有り国際誌

M. Inada, Y. Tanaka, H. Tamukoh, K. Tateno, T. Morie, Y. Katori

Proc. of the 2019 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2015) 2019年12月

脳型人工知能技術の開発招待有り

石井信, 岡田真人, 菅生康子, 大羽成征, 山崎匡, 森江隆, 國吉康夫

人工知能 2019年11月

Switching current of Ta<inf>2</inf>O<inf>5</inf>-based resistive analog memories 査読有り

Li Y., Tsurumaki-Fukuchi A., Arita M., Morie T., Takahashi Y.

2019 Silicon Nanoelectronics Workshop, SNW 2019 2019年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2019 JSAP. Multilevel switching (MS) behaviors in Ta2O5-based resistive random-access-memory (ReRAM) have been drawing attentions as hardware artificial synapse. However, operating resistances, which decide the power consumption of whole system, are relatively low for future integration. In this work, we investigated the characteristics of two kinds of ReRAMs operating with different mechanisms; Cu-top-electrode and Ta-top-electrode Ta2O5-based ReRAMs. By taking account of resistance of high resistive state (HRS), we clarify the difference of MS characteristics between the two kinds of ReRAM devices.

DOI： 10.23919/SNW.2019.8782931

Scopus

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社会実装を目指したホームサービスロボットの研究開発

小野智寛, 坂田拓馬, 吉井拓巳, 上村大地, 金丸和樹, 中村健太郎, 西村雄太, 森江隆, 田向権, 堀三晟, 石田裕太郎, 田中悠一朗, 吉元裕真, 阿部佑志, 武藤冬樹, 椛島康平, 福宿将士

ロボティクス・メカトロニクス講演会講演概要集 ( 一般社団法人日本機械学会 ) 2019 ( 0 ) 1P2 - I02 2019年01月

記述言語：日本語掲載種別：研究論文（その他学術会議資料等）

Home service robots have begun attracting attention due to decreasing birthrate and increasing aging population. We,"Hibikino-Musashi@Home"team, develop home service robots, and participate international competitions; RoboCup@Home and World Robot Challenge (WRC), which are established to realize that robots will work and live with people in domestic environments. In this paper, we introduce our robots and technologies, especially an object recognition and manipulation system. We use You Only Look Once (YOLO) for object recognition. To train YOLO, a big dataset which is difficult to prepare in a short term is required. For this, we develop an automatic annotation system for YOLO which can generate 1.7 million training data, and we can complete training of YOLO in a day. To grasp objects, estimation of object orientations is required. Our system can detect the orientations by processing point clouds of objects. By using the system, we obtained about 30% of scores in Tidy Up Task in the WRC.

DOI： 10.1299/jsmermd.2019.1P2-I02

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007774525

Investigation for Multilevel Memory Capability of ReRAM using Ta2O5-δ Insulator 査読有り

Y. Li, R. Katsumura, M. K. Gronroos, A. Tsurumaki-Fukuchi, M. Arita, H. Andoh, T. Morie, Y. Takahashi

IEEE Silicon Nanoelectronics Workshop (SNW) 78 - 79 2018年06月

Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots 査読有り

Ishida Y., Morie T., Tamukoh H.

Proceedings - IEEE International Symposium on Circuits and Systems 2018年05月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2018 IEEE. This live demonstration presents a 'connective object for middleware to accelerator (COMTA),' an intelligent processing system that uses hardware accelerators (i.e., field programmable gate arrays (FPGAs)) and robot middleware. The key idea of COMTA is to automatically generate the system via robot middleware interfaces. To realize the proposed system, we have developed a block of programs called an 'object' in a hardware/software complex system. We demonstrate an implementation of a human tracking image processing application on a vehicle robot accelerated by COMTA. The demonstration system achieved 3.3 times better power efficiency than a general PCs.

DOI： 10.1109/ISCAS.2018.8351837

Scopus

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A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots 査読有り

Ishida Y., Morie T., Tamukoh H.

Proceedings - IEEE International Symposium on Circuits and Systems 2018-May 2018年04月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Service robots require implementation of intelligent processing, e.g., image processing. However, the computational resources of standard PCs typically used in service robots are not sufficient for such processes. Furthermore, robot middleware is widely used in many robots because such systems facilitate integration and are suitable for rapid prototyping. We propose a 'connective object for middleware to accelerator (COMTA),' which is a processing system that uses hardware accelerators, i.e., field programmable gate arrays (FPGAs), and robot middleware. Users can access the FPGAs in the proposed system via middleware interfaces; thus, complex internal circuits are not required. For human tracking using image processing, the proposed system can automatically generate from a single configuration file. The proposed system performs 3.3 times more efficiently relative to computation than standard PCs in robots.

DOI： 10.1109/ISCAS.2018.8351722

Scopus

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A pulse-width-modulation mode CMOS integrated circuit implementation of threshold-coupled map 査読有り

Uenohara Seiji, Morie Takashi, Tamukoh Hakaru, Aihara Kazuyuki

Nonlinear Theory and Its Applications, IEICE 9 ( 2 ) 268 - 280 2018年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

We propose a coupled-map-lattice complementary-metal-oxide-semiconductor very-large-scale-integration (CMOS VLSI) circuit based on the threshold-coupled map (TCM) that has been proposed previously as a unidirectional connected network model exhibiting different spatiotemporal patterns according to its underlying nonlinear map and update scheme. We introduce mutual connections and arbitrarily valued connection weights into the TCM to realize cellular automata. In this study, we design, fabricate, and evaluate a CMOS integrated circuit with which to implement this extended TCM (ETCM). The ETCM is a universal Turing machine as confirmed in circuit experiments using the fabricated circuit, which can achieve Rule110 of a one-dimensional cellular automaton.

DOI： 10.1587/nolta.9.268

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130006602774

A shared synapse architecture for efficient FPGA implementation of autoencoders 査読有り

A. Suzuki, T. Morie, H. Tamukoh

PLoS ONE 13 ( 3 ) e0194049 2018年03月

記述言語：英語掲載種別：研究論文（学術雑誌）

Copyright: © 2018 Suzuki et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers’ units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

DOI： 10.1371/journal.pone.0194049

Scopus

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脳型アナログ演算と専用集積回路招待有り査読有り

森江隆

人工知能 33 ( 1 ) 39 - 44 2018年01月

A hardware-oriented dropout algorithm for efficient FPGA implementation 査読有り

Yeoh Y., Morie T., Tamukoh H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10639 LNCS 821 - 829 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

China Guangzhou 2017年11月14日 - 2017年11月18日

© Springer International Publishing AG 2017. This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

DOI： 10.1007/978-3-319-70136-3_87

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85035101597&origin=inward

An implementation of a spiking neural network using digital spiking silicon neuron model on a SIMD processor 査読有り

Hori S., Zapata M., Madrenas J., Morie T., Tamukoh H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10613 LNCS 437 - 438 2017年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Italy Alghero 2017年09月11日 - 2017年09月14日

© Springer International Publishing AG 2017. We implement a digital spiking silicon neuron (DSSN) [1] in a single instruction multiple data (SIMD) processor. The SIMD processor is a scalable, reconfigurable, and real-time spiking neural network emulator based on field programmable gate arrays [2]. We implement the DSSN model in the SIMD processor for the first time. The behavior of the membrane potential of one neuron based on the DSSN model is shown in Fig. 1. The operation results of the SIMD processor with 16-bit fixed-point operation are compared with software simulation results based on 64-bit floating-point operation. From the results, it is concluded that the SIMD processor successfully emulated the behavior of the membrane potential. In addition, a full-connection network consisting of 100 neurons is simulated in a software using fixed-point binary numbers to evaluate the bit width for the SIMD processor. In this experiment, the network stores two patterns selected from [1]. In the recall phase, the first pattern with noise is given to this network to recall the pattern. Experimental results show that the network with 16-bit fixed-point numbers, each of which includes a 12-bit fraction, a 3-bit integer, and a 1-bit sign, successfully recalled the input pattern as shown in Fig. 2. Here, Muis a recall rate [1]. From this result, a large DSSN network simulation on the SIMD processor is promising.

Scopus

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カーロボ連携大学院での自動車・ロボットの知能化高度化に向けた専門人材育成招待有り査読有り

森江隆, 石井和男, 我妻広明, 田向権, 榎田修一, 齊藤剛史, 松永良一, 松波勲, 大貝晴俊

工学教育 65 ( 4 ) 51 - 56 2017年07月

Evaluation of multilevel memory capability of ReRAM using Ta<inf>2</inf>O<inf>5</inf>insulator and different electrode materials 査読有り

Li Y., Katsumura R., Grönroos M., Tsurumaki-Fukuchi A., Arita M., Andoh H., Morie T., Takahashi Y.

2017 Silicon Nanoelectronics Workshop, SNW 2017 85 - 86 2017年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Kyoto 2017年06月04日 - 2017年06月05日

© 2017 JSAP. ReRAM (Resistive Random Access Memory) has been drawing attention for its neural network applications with low-power and high-speed operation. The multilevel data storage capability is inherently needed to use the ReRAM as synaptic devices. In this study, two ReRAM devices with different electrode materials in which the operation mechanisms are thought to be different was fabricated and tested. It was clarified that the multilevel resistance characteristics were achieved in both devices.

DOI： 10.23919/SNW.2017.8242309

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85051019890&origin=inward

Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links 査読有り

D. Pramanta, T. Morie, H. Tamukoh

Journal of Robotics, Networking and Artificial Life 4 ( 1 ) 91 - 96 2017年06月

Self-Feedback Electrically Coupled Spin-Hall Oscillator Array for Pattern-Matching Operation 査読有り

K. Kudo, T. Morie

Appl. Phys. Express 10 ( 4 ) 043001 2017年03月

Multi-Valued Quantization Neural Networks toward Hardware Implementation 査読有り

Y. Aratani, Y. Y. Jye, A. Suzuki, D. Shuto, T. Morie, H. Tamukoh

Proc. of the 2017 International Conference On Artificial Life And Robotics (ICAROB2017) 58 - 58 2017年01月

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