研究者詳細 - 森江　隆

論文 - 森江　隆

分割表示322 件中 41 - 60 件目／全件表示 >>

A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation 査読有り

F. Maldonado H., H. Tanaka, T. Matsuo, T. Morie, K. Aihara

18th Int. Conf. on Neural Information Processing (ICONIP2011) III ( 7064 ) 381 - 388 2011年11月

知的画像認識技術と脳型LSI実装招待有り査読有り

森江隆, 石川聖二

電子情報通信学会誌 94 ( 6 ) 459 - 463 2011年06月

アナログ・デジタル融合方式LSI技術による脳型視覚システム招待有り査読有り

森江隆

IEICE Fundamentals Review 1 ( 1 ) 19 - 29 2007年07月

Harnessing Nonidealities in Analog In-Memory Computing Circuits: A Physical Modeling Approach for Neuromorphic Systems 査読有り国際誌

Sakemi Y., Okamoto Y., Morie T., Nobukawa S., Hosomi T., Aihara K.

Advanced Intelligent Systems 8 ( 1 ) 2026年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Large-scale deep learning models are increasingly constrained by their immense energy consumption, which limits their scalability and applicability for edge intelligence. In-memory computing (IMC) offers a promising solution by addressing the von Neumann bottleneck inherent in traditional deep learning accelerators, significantly reducing energy consumption. However, the analog nature of IMC introduces hardware nonidealities that degrade model performance and reliability. This article presents a novel approach to directly train physical models of IMC, formulated as ordinary differential equation (ODE)-based physical neural networks (PNNs). To enable the training of large-scale networks, a technique called differentiable spike-time discretization is proposed, which reduces the computational cost of ODE-based PNNs by up to 20 times in speed and 100 times in memory. Such large-scale networks enhance learning performance by exploiting hardware nonidealities on the CIFAR-10 dataset. The proposed bottom-up methodology is validated through post-layout SPICE simulations on the IMC circuit with nonideal characteristics using the sky130 process. The proposed PNN approach reduces the discrepancy between model behavior and circuit dynamics by at least an order of magnitude. This work paves the way for leveraging nonideal physical devices, such as nonvolatile resistive memories, for energy-efficient deep learning applications.

DOI： 10.1002/aisy.202500351

Scopus

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Spike-based time-domain analog weighted-sum calculation model for extremely low power VLSI implementation of multi-layer neural networks 査読有り国際誌

Wang Q., Tamukoh H., Morie T.

Frontiers in Neuroscience 19 2025年09月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

In deep neural network (DNN) models, the weighted summation, or multiply-and-accumulate (MAC) operation, is an essential and heavy calculation task, which leads to high power consumption in current digital processors. The use of analog operation in complementary metal-oxide-semiconductor (CMOS) very-large-scale integration (VLSI) circuits is a promising method for achieving extremely low power-consumption operation for such calculation tasks. In this paper, a time-domain analog weighted-sum calculation model is proposed based on an integrate-and-fire-type spiking neuron model. The proposed calculation model is applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed, and two timings proportional to the positive and negative ones are produced, respectively, in each layer. The timings are then fed into the next layers without their subtraction operation. We also propose VLSI circuits to implement the proposed model. Unlike conventional analog voltage or current mode circuits, the time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can operate with extremely low power consumption. We designed a proof-of-concept (PoC) CMOS circuit to verify weighted-sum operation with the same weights. Simulation results showed that the precision was above 4-bit, and the energy efficiency for the weighted-sum calculation was 237.7 Tera Operations Per Second Per Watt (TOPS/W), more than one order of magnitude higher than that in state-of-the-art digital AI processors. Our model promises to be a suitable approach for performing intensive in-memory computing (IMC) of DNNs with moderate precision very energy-efficiently while reducing the cost of analog-digital-converter (ADC) overhead.

DOI： 10.3389/fnins.2025.1656892

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105017067115&origin=inward

An in-memory computing circuit with carry-over thermometer coding for a hippocampus-inspired model 査読有り国際誌

Shishido Y., Jones T.M., Tamukoh H., Morie T.

Proceedings IEEE International Symposium on Circuits and Systems (ISCAS 2025) 2025年05月

担当区分：最終著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The memory-based hippocampus-inspired model (MBHIM) that has been proposed by the authors is a model that reproduces episodic memory suitable for VLSI implementation. While an MBHIM VLSI circuit can achieve high energy efficiency using the in-memory computing architecture with thermometer coding, its computational functionality was limited to addition operation. The use of thermometer coding, though enabling simple VLSI implementation, remains an integration density challenge. In this paper, we propose a memory cell circuit for MBHIM, which supports addition and subtraction using in-memory computing, enabling broader applications, including time-dependent forgetting mechanisms. We also propose a carry-over thermometer coding scheme for efficient value representation, achieving a reduction of 60-90% transistor count compared to conventional approaches. This scheme maintains the advantages of thermometer coding while achieving high integration density, making it particularly effective for memory devices with high write error rates, such as MRAM and ReRAM. The proposed scheme is promising for realizing brain-inspired AI hardware that achieves low power consumption, high computational efficiency, and high integration density.

DOI： 10.1109/ISCAS56072.2025.11043380

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105010598370&origin=inward

Analog In-Memory Computing from a Memory-Agnostic Perspective: Theory, Nonidealities, and Hardware-Aware Training 招待有り査読有り

SAKEMI Yusuke, AWANO Hiromitsu, MORIE Takashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences ( 一般社団法人電子情報通信学会 ) advpub ( 0 ) 2025年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

Analog in-memory computing (AIMC) executes matrix-vector multiplications (MVMs) inside memory to alleviate the von Neumann bottleneck and improve energy efficiency. This tutorial classifies AIMC circuits in a memory-agnostic way, namely, current-domain, charge-domain, charge-redistribution, capacitive-division, resistive-division, and time-domain IMC. We explain each type of AIMC circuit with simple mathematical models. Furthermore, we review key device and circuit nonidealities (e.g., process variation, IR drop, sneak paths, and I/O quantization/ nonlinearity) with practical mitigation strategies in circuitry and peripherals. Finally, we organize hardware-aware training into three complementary families—probabilistic/precise modeling, physical modeling, and hardware-in-the-loop techniques—providing a mathematically grounded bridge between circuits and learning for robust, scalable AIMC accelerators.

DOI： 10.1587/transfun.2025gci0001

CiNii Research

A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information 査読有り国際誌

Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024年06月

CMOS Digital-Analog Mixed Signal VLSI Implementation of a Hippocampus-Inspired Model 査読有り国際誌

Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024年06月

Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers 査読有り国際誌

Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh

International Symposium on Circuits and Systems (ISCAS 2024) 2024年05月

Learning reservoir dynamics with temporal self-modulation 査読有り国際誌

Sakemi Y., Nobukawa S., Matsuki T., Morie T., Aihara K.

Communications Physics 7 ( 29 ) 1 - 11 2024年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

Reservoir computing (RC) can efficiently process time-series data by mapping the input signal into a high-dimensional space via randomly connected recurrent neural networks (RNNs), which are referred to as a reservoir. The high-dimensional representation of time-series data in the reservoir simplifies subsequent learning tasks. Although this simple architecture allows fast learning and facile physical implementation, the learning performance is inferior to that of other state-of-the-art RNN models. In this study, to improve the learning ability of RC, we propose self-modulated RC (SM-RC) that extends RC by adding a self-modulation mechanism. SM-RC can perform attention tasks where input information is retained or discarded depending on the input signal. We find that a chaotic state can emerge as a result of learning in SM-RC. Furthermore, we demonstrate that SM-RC outperforms RC in NARMA and Lorenz model tasks. Because the SM-RC architecture only requires two additional gates, it is physically implementable as RC, thereby providing a direction for realizing edge artificial intelligence.

DOI： 10.1038/s42005-023-01500-w

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85182165175&origin=inward

An efficient spatial representation scheme for memory-based hippocampus-inspired model with VLSI implementation 査読有り

Shishido Y., Nomura O., Tateno K., Tamukoh H., Morie T.

Nonlinear Theory and Its Applications IEICE ( 一般社団法人電子情報通信学会 ) 15 ( 4 ) 785 - 795 2024年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

Hippocampus integrates events and places information critical for episodic memory. Memory-based hippocampus-inspired model (MBHIM) is a hippocampus-inspired model suitable for VLSI implementation. This paper proposes an efficient spatial representation scheme for MBHIM with VLSI implementation. Each layer represents a space of a different size to represent and store spatial information at different resolutions. This scheme can achieve the representation of large spaces with high spatial resolutions, even when the number of memory cells per layer is limited. We conducted an experiment using a VLSI system of MBHIM to demonstrate the effectiveness of the proposed scheme.

DOI： 10.1587/nolta.15.785

Kyutacar

Scopus

CiNii Research

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105002769314&origin=inward

Hibikino-Musashi@Home RoboCup@Home DSPL Champion 2024 査読有り国際誌

Mizutani A., Isomoto K., Yamao K., Kobayashi R., Fumoto S., Arimura K., Yamaguchi N., Shiba T., Kimizuka K., Ohno Y., Terashima R., Yamaguchi H., Fujino T., Maruno R., Yoshimura W., Mine K., Phu Thien Nhan T., Yano Y., Tanaka Y., Nishida T., Morie T., Tamukoh H.

Lecture Notes in Computer Science 15570 LNAI 461 - 472 2025年04月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper provides an overview of the techniques employed by Hibikino-Musashi@Home during their participation in the Domestic Standard Platform League (DSPL). The team developed a robust perception system, navigation system, and task planner, as well as demonstrated their ability to secure first place in the DSPL. In particular, this paper summarizes the technologies employed in the competition.

DOI： 10.1007/978-3-031-85859-8_39

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105003860028&origin=inward

Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory 査読有り国際誌

Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie

International Joint Conference on Neural Networks (IJCNN 2024) 2024年06月

Reservoir Reinforcement Learning with Chaotic Boltzmann Machines Implemented on an FPGA 査読有り

Sakino Yamato, Tamukoh Hakaru, Morie Takashi, Katori Yuichi

IEICE Proceeding Series ( The Institute of Electronics, Information and Communication Engineers ) 76 422 - 425 2023年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Reinforcement learning has led to advances in areas such as attitude control in robotics and action planning in autonomous driving systems. However, reinforcement learning algorithms often face computational bottlenecks that limit their application to edge devices. In recent years, reservoir computing has emerged as a potential solution to this problem. One of these models updates the weight matrix using Q-learning, a popular reinforcement learning algorithm. This paper introduces reservoir reinforcement learning using chaotic Boltzmann machines on a field programmable gate array. We demonstrate the efficient implementation of reservoir computing with chaotic Boltzmann machines in hardware, achieving low computational costs. To demonstrate the effectiveness of this approach, we validate the proposed model using an action planning task in a two-dimensional environment consisting of nine rooms. The result shows that the model can be implemented in digital circuits with low power consumption and hardware resource savings while maintaining problem-solving capabilities. This result suggests efficient machine learning hardware in action planning could be applied to real-world scenarios.

DOI： 10.34385/proc.76.c1l-33

Kyutacar

CiNii Research

その他リンク： https://kyutech.repo.nii.ac.jp/records/2001134

FPGA Implementation of a Chaotic Boltzmann Machine Annealer 査読有り国際誌

K. Yoshioka, Y. Katori, Y. Tanaka, O. Nomura, T. Morie

International Joint Conference on Neural Networks (IJCNN 2023) 2023年06月

Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-volatile Memory with Write-errors 査読有り国際誌

N. Fuengfusin, H. Tamukoh, Y. Tanaka, O. Nomura, T. Morie

International Joint Conference on Neural Networks (IJCNN 2023) 2023年06月

Random Network Structure of Materials Developing Next Generation AI Devices for Autonomous Robotics 招待有り国際誌

H. Tanaka, H. Tamukoh, T. Morie

239th ECS Meeting with the 18th International Meeting on Chemical Sensors (IMCS) 2021年06月

A hardware intelligent processing accelerator for domestic service robots 査読有り

Y. Ishida, T. Morie, H. Tamukoh

Advanced Robotics 2020年07月

Initial states and analog switching behaviors of two major tantalum oxide resistive memories 査読有り国際誌

Li Y., Tsurumaki-Fukuchi A., Arita M., Morie T., Takahashi Y.

Japanese Journal of Applied Physics 59 ( 4 ) 2020年04月

記述言語：英語掲載種別：研究論文（学術雑誌）

© 2020 The Japan Society of Applied Physics. A systematic study was performed to understand the two major operation modes, valence change memory (VCM) and electrochemical memory (ECM), of tantalum oxide resistive memory, which were categorized by the type of conductive filament. The tantalum oxide insulator layer was predictably fabricated to modify the pristine oxygen-vacancy concentration in the insulator layer, where tantalum and copper top electrodes were used to achieve VCM and ECM modes. The distinguishable characteristics of the initial state and analog resistive switching operation revealed the prerequisites for switching capabilities and demonstrated the effects of oxygen vacancies in the two switching modes.

DOI： 10.35848/1347-4065/ab8022

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85083310643&origin=inward

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