Papers - NAKAMURA Kazuyuki
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A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch Reviewed
Y.Hirakawa, A. Motomura,K. Ota,N. Mimura, K. Nakamura
IEEE International Conference on Microelectronic Test Structures (ICMTS) 2012 2012.03
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Complementary Metal Oxide Semiconductor Operational Amplifier Offset Calibration Technique Using Closed Loop Offset Amplifier and Folded-Alternated Resistor String Digital-to-Analog Converter Reviewed
Hiroyuki Morimoto, Hiroaki Goto, Hajime Fujiwara, Kazuyuki Nakamura
Japanese Journal of Applied Physics 51 ( 2 ) 02BE10 - 02BE10-6 2012.02
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An Experimental Verification of the Design Margin Analysis Method for Even-Stage Ring Oscillators with CMOS Latch Reviewed
Y. Hirakawa, N. Mimura, A. Motomura, K. Nakamura
International Conference on Solid State Devices and Materials(SSDM) 2011.09
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CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC Reviewed
H. Morimoto, H. Goto, H. Fujiwara, K. Nakamura
2011 International Conference on Solid State Devices and Materials(SSDM) 2011.09
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An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-wire Serial I/O Reviewed
H. Morimoto, H. Koike, K. Nakamura
IEICE TRANSACTIONS on Electronics E94-C ( 6 ) 945 - 952 2011.06
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An Optimal Design Method for Complementary Metal Oxide Semiconductor Even-Stage Ring Oscillators Containing Latches Reviewed
Y. Kohara, M. Asano, Y. Kawakami, Y. Uchida, H. Koike, K. Nakamura
Japanese Journal of Applied Physics 49 ( 4 ) 04DE15 - 04DE15-6 2010.04
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An Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function Reviewed
H. Morimoto, H. Koike, K. Nakamura
15th Asia and South Pacific Design Automation Conference (ASP-DAC) 365 - 366 2010.01
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An Optimal Design Method for CMOS Even-Stage Ring Oscillators Containing Plural Latches Reviewed
Y. Kohara, Y. Kawakami, Y. Uchida, H. Koike, K. Nakamura
2009 International Conference on Solid State Devices and Materials(SSDM) 2009.10
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Static Noise Margin Evaluation Method Based on Direct Polynomial-Curve-Fitting with Universal SRAM Cell Inverter TEG Measurement Reviewed
K. Nakamura,K.Noda,H.Koike
IEEE International Conference on Microelectronic Test Structures (ICMTS) 2009.03
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An Optimal Design Method for Even-Stage Ring Oscillators with a CMOS Latch Reviewed
K. Nakamura,M.Asano,Y.Kohara,H.Koike
2008 International Conference on Solid State Devices and Materials (SSDM 2008) 2008.09
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A memory-based programmable logic device using look-up table cascade with synchronous static random access memories Reviewed
K. Nakamura,T. Sasao,M. Matsuura,K. Tanaka,K. Yoshizumi,H. Nakahara,Y. Iguch
Japanese Journal of Applied Physics 45 ( 4B ) 3295 - 3300 2006.04
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A memory-based programmable logic device using a look-up table cascade with synchronous SRAMs Reviewed
K. Nakamura,T. Sasao,M. Matsuura,K. Tanaka,K. Yoshizumi,H. Nakahara,Y. Iguchi
2005 International Conference on Solid State Devices and Materials (SSDM 2005) 2005.09
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Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs Reviewed
K. Nakamura,T. Sasao,M. Matsuura,K. Tanaka,K. Yoshizumi,H. Qin,Y. Iguchi
Cool Chips VIII, IEEE Symposium on Low-Power and High-Speed Chips 2005.04
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A realization of multiple-output functions by a look-up table ring Reviewed
H. Qin,T. Sasao,M. Matsuura,K. Nakamura,S. Nagayama,Y. Iguchi
IEICE Transactions on Fundamentals of Electronics E87-A 3141 - 3150 2004.12
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強誘電体メモリ（FeRAM）の長期データ保持特性テスト法 Reviewed
小池,田辺,山田,豊島,中村
電子情報通信学会論文誌 J86-C ( 8 ) 902 - 912 2003.08
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An On-Chip 100GHz Sampling 8-channel Sampling-Oscilloscope Macro with Embedded Sampling-Clock Generator Reviewed
M.Takamiya,M.Mizuno,K.Nakamura
2002 International Solid-State Circuits Conference(ISSCC) 182 - 183 2002.02
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A 2.5GHz 4-phase Clock Generator with Scalable No-Feedback-Loop Architecture Reviewed
K.Yamaguchi,M.Fukaishi,T.Sakamoto,A.Akiyama,K.Nakamura
IEEE Journal of Solid-State Circuits 36 ( 11 ) 1666 - 1672 2001.11
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Optimizing Bias Circuit Design of Cascode Operational Amplifiers for Wide Dynamic Range Operations Reviewed
T.Fukumoto,H.Okada,K.Nakamura
2001 International Symposium on Low Power Electronics and Design, 2001.08
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interconnection as an IP macro of a CMOS library Reviewed
T.Yoshikawa,I.Hatakeyama,K.Miyoshi,K.Kurata,J.Sasaki,N.Kami,T.Sugimoto,M.Fukaishi,K.Nakamura,K.Tanaka,H.Nishi,T.Kudoh
Proceedings of the Ninth Symposium on High Performance Interconnects (HOTI '01), 31 - 35 2001.08
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Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro Reviewed
K. Takeda,Y.Aimoto,K.Nakamura,S.Masuoka,K.Ishikawa,K.Noda,T.Takeshima,T.Murotani
2001 IEEE Symposium on VLSI Circuits 229 - 230 2001.06