研究者詳細 - 山脇　彰

論文 - 山脇　彰

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Development of Self-Calibration Hardware Interface for a Peripheral on Super General Purpose SoC 査読有り国際誌

Hibiki Shinozaki, Akira Yamawaki

Proc. of The 13th IIAE International Conference on Industrial Application Engineering 2025 (ICIAE2025)erence on Industrial Application Engineering 2025 (ICIAE2025) ( The Institute of Industrial Applications Engineers ) 262 - 268 2025年03月

Parallel Execution Method Using Multiple High-level Synthesized Hardware for Compositing Sprite and Background 査読有り国際誌

Yuka Otani, Akira Yamawaki

Development of Single-frame Sprite Drawing Hardware Which Can Compose Background by High-level Synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Optimization of Image Usage for Sprite Drawing Hardware Combining High-Level Synthesis and FPGA Internal Memory 査読有り国際誌

Keigo Aoki, Akira Yamawaki

Proceedings of the 8th International Conference on Technology and Social Science 2024 (ICTSS 2024) GS03-1 - GS03-6 2024年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

フィリピンセブ(オンライン) 2024年12月15日 - 2024年12月19日

その他リンク： https://conf.e-jikei.org/ICTSS/2024/proceedings/materials/proc_files/GS/ICTSS2024_G03.pdf

Peripheral Specific Hardware Interface Architecture for Super General Purpose SoC 査読有り国際誌

Hibiki Shinozaki, Akira Yamawaki

Proceedings of the 8th International Conference on Technology and Social Science 2024 (ICTSS 2024) GS02-1 - GS02-6 2024年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

フィリピンセブ(オンライン) 2024年12月15日 - 2024年12月19日

その他リンク： https://conf.e-jikei.org/ICTSS/2024/proceedings/materials/proc_files/GS/ICTSS2024_G02.pdf

Development of single frame sprite drawing hardware in High-level Synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of the 8th International Conference on Technology and Social Science 2024 (ICTSS 2024) GS01-1 - GS01-6 2024年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

フィリピンセブ(オンライン) 2024年12月15日 - 2024年12月19日

その他リンク： https://conf.e-jikei.org/ICTSS/2024/proceedings/materials/proc_files/GS/ICTSS2024_G01.pdf

Hardware Implementation of Device Driver for an SPI Peripheral using High-Level Synthesis 査読有り国際誌

Shinozaki H., Yamawaki A.

International Conference on Intelligent Informatics and BioMedical Sciences, ICIIBMS ( 2024 ) 300 - 303 2024年11月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Okinawa 2024年11月21日 - 2024年11月23日

Combining with the register-transfer-level description, we aim to develop a generic hardware interface architecture for SPI devices using high-level synthesis that automatically converts software into hardware. Device drivers that control SPI devices will not be able to maximize their performance due to software overhead, but customized hardware interface may achieve. This paper evaluates the performance, circuit size, and power efficiency of a hardware device driver for BME280, which is a temperature, humidity, and barometric pressure sensor.

DOI： 10.1109/ICIIBMS62405.2024.10792835

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85219209929&origin=inward

Hardware Implementation of Spherical Diffuse Reflection in Ray-Casting Using High Level-Synthesis 査読有り国際誌

Kurata K., Yamawaki A.

Conference Proceeding - 23rd International Symposium on Communications and Information Technologies, ISCIT 2024 22 - 26 2024年09月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

タイバンコク(オンライン) 2024年09月23日 - 2024年09月25日

Game applications require high graphics, and it is not suitable for mobile devices which is battery-powered because of heavy processing load. Mobile terminals equipped with FPGA, which are dynamically reconfigurable hardware, can take advantage of the high processing performance and low power consumption of FPGA, thus helping to solve these problems. However, this system tends to have high development costs due to the need of circuit data for FPGA's operation. To avoid this problem, we make use of High-Level Synthesis, HLS. HLS is a tool that automatically generate hardware from software program, but it is not panacea. If there is no consideration of hardware structure, it sometimes generates inferior hardware. We are therefore developing a HLS-oriented program particularly focusing on ray-casting, which is utilized in the creation of high-graphic game applications, and have implemented spherical diffuse reflection which is one of the processes included in ray-casting. In this paper, we implemented fixed-point conversion to make numerous vector operations used in ray-casting more hardware-friendly. The experiment evaluates that the circuit size, execution time, and power efficiency. The results show that the fixed-point method contributes significantly to the reduction of the circuit size and the created hardware performs satisfactorily against the software.

DOI： 10.1109/ISCIT63075.2024.10793519

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85216580425&origin=inward

Development of sprite drawing hardware with two parallelisms using semi-parallel method 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 242 - 247 2024年09月

Development of Triangle Drawing Hardware by High-level Synthesis 査読有り国際誌

Kanta Shin, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 272 - 275 2024年09月

Comparison and evaluation of image sharpening hardware developed using high-level synthesis, 査読有り国際誌

Ryota Oka, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 267 - 271 2024年09月

Hardware Implementation of Spherical Specular Reflection in Ray-casting Using High-Level Synthesis 査読有り国際誌

Kazuki Kurata, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 260 - 266 2024年09月

Performance variation caused by sprite drawing pattern for high-level synthesized sprite drawing hardware 査読有り国際誌

Otani Y., Yamawaki A.

ACM International Conference Proceeding Series 1 - 5 2024年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We are developing a sprite drawing software suitable for automatic hardware generation by high-level synthesis. Sprite drawing stores the sprite image into a frame memory pointed to by the origin coordinates. Frame memory is typically realized with high-capacity DRAM such as DDR SDRAM. The DDR SDRAM is prone to stalls when the memory accesses have randomness. The performance of sprite drawing hardware may depend on the drawing pattern on the frame memory in contrast with a CPU hiding the frame memory by a cache memory. This paper investigates how hardware and software performance varies with varying sprite drawing patterns. The results show that hardware achieves better real-time performance than software execution, although the performance variation of hardware due to drawing conditions is slightly larger than that of software execution.

DOI： 10.1145/3686625.3686626

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85203795732&origin=inward

Hardware Implementation of Calibration Data Loading in Device Driver for an SPI Peripheral 査読有り国際誌

Shinozaki H., Yamawaki A.

ACM International Conference Proceeding Series 19 - 23 2024年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the IoT progresses, various SoCs are being developed. If a SoC is in high demand, the development cost per chip is small, but if the demand is localized, the development cost is large, resulting in more expensive products. To solve this problem, we aim to develop a general-purpose SoC with hardware interfaces for all peripheral devices. Since it is difficult to develop such a SoC due to hardware constraints, the dynamic reconfiguration of FPGA is used to deploy only what is necessary for processing in the reconfiguration unit. In addition, we aim to develop a general-purpose architecture that facilitates the design and development of dedicated hardware interfaces for each peripheral device. This architecture is to achieve a general-purpose SoC by seeking the cooperation of engineers around the world. Toward the development of this architecture, we will first focus on SPI devices. In developing hardware device drivers for SPI devices, RTL description is used for the parts that describe clock-cycle-based operations, and high-level synthesis is used for the parts that describe procedure-based operations. In this study, the BME280, a temperature, humidity, and barometric pressure sensor for SPI devices, is used to convert the device driver functionality to hardware for efficient use. This paper describes the hardware implementation of the part that reads multiple calibration data to correct the sensor data, and evaluates the performance, circuit size, and power efficiency through demonstration experiments using an actual device.

DOI： 10.1145/3686625.3686629

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85203790525&origin=inward

Development of Sprite Drawing Hardware Combining High-Level Synthesis and FPGA Internal Memory 査読有り国際誌

Aoki K., Yamawaki A.

ACM International Conference Proceeding Series 37 - 41 2024年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Mobile devices are required to have higher performance and more functionality while conserving more power. To realize high-performance and low-power game applications by dynamic hardware reconfiguration on a FPGA equipped with mobile devices, we are developing a hardware-oriented game library so that high-level synthesis can generate efficient hardware automatically. Usually, large images and other data used in games are stored in an external memory instead of hardware internally but loading them from the external memory may be time-consuming. Therefore, this paper proposes a hardware organization to utilize the internal memory in a FPGA to reduce the external memory accesses, and then develops a sprite drawing hardware combines software optimized for high-level synthesis and the internal memory in a FPGA. Through demonstration experiments using an actual device, this paper evaluates the execution time, circuit size, and power efficiency.

DOI： 10.1145/3686625.3686632

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85203803438&origin=inward

A Real-time Non-Photorealistic Rendering System using a High-Level Synthesized Hardware of Pencil Drawing Style Image Conversion 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 158 - 165 2024年03月

Development of Wired Zero-powered Sensor Network Group in Wired-wireless Hierarchical Sensor Network 査読有り国際誌

Akira Yamawaki, Seiichi Serikawa

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 182 - 187 2024年03月

Multi-staging Effect of Averaging Filter on High-Level Synthesized Pencil Drawing Style Image Conversion Hardware 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 174 - 181 2024年03月

Effect of Median Filter on High-level Synthesized Pencil Drawing Style Image Conversion Hardware 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 166 - 173 2024年03月

Light-weight color image conversion like pencil drawing for high-level synthesized hardware 査読有り国際誌

Tani H., Yamawaki A.

Artificial Life and Robotics 29 ( 1 ) 29 - 36 2024年02月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

We are developing pencil-drawing-style image conversion software suitable for high-level synthesis, HLS, technology that automatically converts software into hardware. The pencil-drawing-style image conversion consists of the former and latter processes. The former generates the images expressing edge strengths and their directions. The latter process convolves the line segment corresponding to the edge strength with its direction. As hardware-oriented software description, the medium data across the former and latter processes are optimized. In addition, the former and latter processes are overlapped between the FIFO buffer passing the medium data. The obtained image is still a gray-scaled image. To make it support the color image, this paper inserts a process compositing the original color image with the grayed pencil-drawing-style image to not intervene in the pipelined data path behavior. As a result, an HLS tool used is expected to generate a hardware module with the ideal pipelined data path by one output data/one clock. The experimental results show that the colorization hardware had no significant performance degradation issues for circuit size, run time, or power efficiency compared to the pencil drawing hardware with grayscale. Compared with the software execution, our hardware supporting color image can achieve 4.2 times the performance improvement and 130 times power efficiency.

DOI： 10.1007/s10015-023-00927-2

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85180442262&origin=inward

An investigation of line and frame based descriptions on designing sprite drawing hardware in high-level synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of 2023 11th International Japan-Africa Conference on Electronics, Communications and Computations (JAC-ECC) ( IEEE ) 176 - 179 2023年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

エジプト(オンライン) Alexandria 2023年12月18日 - 2023年12月20日

We are developing a sprite drawing process in a game software library optimized to make high-level synthesis, HLS, generate an efficient hardware. There are two description methods to realize an image processing consisting of several sub-processes. The one is line-based method processing every line and the another is frame-based method processing every image among them. Which method is better must be investigated when using HLS to develop a sprite drawing hardware. The experimental result shows that the frame-based method is better about performance because it reduces an overhead due to switching every line. However, the line-based method is more suitable from the viewpoints about the amount of hardware and power consumption.

DOI： 10.1109/JAC-ECC61002.2023.10479603

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85190685671&origin=inward

Process chaining without image and performance loss for pencil drawing style image conversion in High-Level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 10th IIAE International Conference on Intelligent Systems and Image Processing 2023 (ICISIP 2023) 148 - 153 2023年09月

An investigation of performance and power efficiency for parallax background scrolling hardware written in high-level synthesis 査読有り国際誌

Kilryong Lee, Akira Yamawaki

Journal of Physics: Conference Series 2559 ( 2559 ) 012008 2023年08月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

韓国済州島 2023年02月18日 - 2023年02月20日

We are developing a game programming software library so that high-level synthesis, HLS, can automatically generate high-performance and low-power hardware modules. A mobile terminal with a user-available reconfigurable device like Field programmable gate array, FPGA, we have proposed will efficiently perform game application built in HLS-oriented game library instead of power-hungry software execution. The dynamic hardware reconfiguration on a single FPGA can execute many kinds of game applications. Our previous research has developed software description methods for two-background scrolling in HLS-oriented game programming library by using two methods. They are (1) Full-parallel equips plural physical ports loading background images individually making HLS hardware execute the entire process parallelly increasing the amount of hardware: (2) Semi-parallel shares the single port loading background images serially, suppressing the hardware growth while achieving moderate performance by overlapping operation phases. We investigate two methods about execution time and power efficiency on the parallax scrolling with 2 to 4 backgrounds. The execution times of full-parallel hardware at 100MHz clock frequency are constantly about 9.65 [ms] while those of semi-parallel are 28, 38 and 47 [ms]. The PC at 3.2 GHz shows 78, 98 and 105 [ms] respectively as well. The power efficiencies about the full-parallel estimated considering hardware enlargement are 167, 208 and 112 times compared to the software execution in the PC, while those of semi-parallel are 94, 88 and 75 times. This fact indicates that the full-parallel is better strategy for parallax background scrolling in this case although more hardware resource are invested.

DOI： 10.1088/1742-6596/2559/1/012008

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85172277917&origin=inward

Wired-Wireless Hierarchical Sensor Network using Zero power Sensor Node 査読有り国際誌

Akira Yamawaki, Makoto Miyauchi, Seiichi Serikawa

Journal of Physics: Conference Series 2559 ( 2559 ) 012004 2023年08月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

韓国済州島 2023年02月18日 - 2023年02月20日

The wireless sensor network, WSN, is a promising technology to make our social life better. However, the maintenance of the battery attached to each sensor node avoids WSN widely be used. The zero standby-power sensor node (ZSSN) extends battery life by eliminating standby power, but they impose high cost and maintenance burdens because each node has its own battery and wireless module. This paper proposes a wired-wireless hierarchical sensor network consisting of a small network group of ZPSNs (Zero power sensor node) with large capacitor as power supply that are wired together, and the parent node has a wireless module and an energy harvester. The proposed WSN can suppress the number of energy harvesters and wireless modules to that of groups. There are no batteries by replaced to the capacitors. That is, our WSN can reduce the maintenance and cost caused by which there is no battery, and each only parent node has wireless module and energy harvester. The experimental result shows that the standby ZPSN can keep enough voltage 48 days on the large capacitor to operate in active mode correctly.

DOI： 10.1088/1742-6596/2559/1/012004

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85172276329&origin=inward

Process Integration to Realize Full Pipelined Pencil Drawing Style Image Conversion Hardware in High-Level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of 5th International Conference on Computer Communication and the Internet 2023 (ICCCI 2023) 251 - 255 2023年08月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本藤沢 2023年06月23日 - 2023年06月26日

We are developing pencil drawing style image conversion software suitable for High-Level Synthesis (HLS) technology that automatically converts software into hardware. As an initial step, we have developed software for HLS by dividing the entire process into former and latter sub-processes to reduce the size of the target, and then developed software for each of these sub-processes. Former and latter processes have been optimized for HLS, and the HLS hardware modules were able to achieve an ideal performance with well-pipelined data path. However, they are fired sequentially. So, the total performance has a rest of room to improve the performance by overlapping former and latter processes. This paper develops the HLS oriented software that the HLS can generate hardware module integrating former and later processes. This integration can achieve a totally pipelined data path across all processes. As a result, it is expected that the performance becomes ideal one without sequential executing part. The experimental result confirms the effectiveness of the proposed method by comparing the processing time, circuit size, and power efficiency with those of previous hardware.

DOI： 10.1109/ICCCI59363.2023.10210175

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85170036997&origin=inward

Development of High-performance Sprite Drawing Process in a Game Library for High-Level Synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of 5th International Conference on Computer Communication and the Internet 2023 (ICCCI 2023) 223 - 228 2023年08月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本藤沢 2023年06月23日 - 2023年06月26日

A mobile terminal dynamically reconfiguring an optimal hardware for each application can achieve higher performance and lower power consumption. To develop game applications running on such mobile terminal requires a high-level synthesizable game library whose functions can be automatically converted to hardware modules. Each function in a high-level synthesizable library, must be written considering characteristic of hardware to be converted to an efficient hardware. This paper focuses on the drawing of 2D sprite characters which is a common function among many conventional software game libraries. Sprite movement is realized by drawing and compositing with a background image. To achieve this, we develop a software description suitable for high-level synthesis while taking into hardware characteristics. The characteristics considered are the burst transfer of memory access and the parallelization of the former and later processes. Experimental results show that our high-level synthesis hardware is 1.6 times faster and sixteen times more power efficient than software execution.

DOI： 10.1109/ICCCI59363.2023.10210177

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85170059033&origin=inward

Hardware Development of Sphere Intersection in Ray-casting Using High-Level-Synthesis 査読有り国際誌

Kazuki Kurata, Akira Yamawaki

Proceedings of The 7th Imaging, Signal Processing and Communications 2023 (ICISPC2023) 86 - 90 2023年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本熊本 2023年07月21日 - 2023年07月23日

Game applications that require high graphics performance have a large processing load, which greatly affects the running time of battery-driven mobile terminals. Mobile terminals that support dynamic partial reconfiguration of hardware can perform high-performance and low-power graphics processing through power-efficient hardware execution, rather than software. This paper develops hardware for the intersection determination process in ray-casting, which is utilized in the creation of high-graphic game applications. In the development, the HLS, which is an automated software-to-hardware conversion tool is used. We developed the software of intersection determination process so that the HLS can generate small-resource-usage, high-performance, and power-efficient hardware. Intersection determination of ray-casting is carried out by vector and square root calculation. Usually, these calculations are executed in floating-point operation. However, this operation method tends to increase the size of the circuit because it requires a great deal of resources when implemented hardware. It is not desirable due to a huge circuit size means high power consumption. Therefore, this paper shows an optimal method in vector and square root calculations using fixed point, while considering its accuracy. Also, through demonstrations on actual machines, we evaluate its usefulness in terms of performance, circuit size and power efficiency.

DOI： 10.1109/ICISPC59567.2023.00024

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85183460173&origin=inward

Data Path parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of The 7th Imaging, Signal Processing and Communications 2023 (ICISPC2023) 97 - 101 2023年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本熊本 2023年07月21日 - 2023年07月23日

A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve higher performance and lower power consumption compared with a conventional one. We are developing a software game library so that the high-level synthesis, HLS, can automatically generate an efficient hardware module in such mobile terminals. The HLS library must be built with deep consideration of hardware organization. Otherwise, the HLS converts software into a large and slow hardware module. This paper focuses on the drawing of 2D sprite characters. Character movement is achieved by repeatedly compositing the background image and sprite image during drawing. The data paths are parallelized on the sprite drawing process so that the HLS can produce better hardware. The experiments confirm the effectiveness of the proposed method on the actual machine and simulation.

DOI： 10.1109/ICISPC59567.2023.00026

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85183473669&origin=inward

Memory access optimization for former process of pencil drawing style image conversion in High-level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Parallel and Distributed Computing, Applications and Technologies. PDCAT 2022. Lecture Notes in Computer Science ( Springer, Cham ) 13798 LNCS ( 13798 ) 57 - 68 2023年04月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本仙台 2022年12月07日 - 2022年12月09日

To effectively use high-level synthesis, which automatically converts software to hardware, it is necessary to create software programs considering hardware configuration. This paper attempts to automatically generate high-performance and power-saving hardware from software for pencil drawing style image conversion. The former process of the pencil drawing style image conversion reads the input image for each window and generates a lot of middle images. Automatic generation of better hardware requires an optimization of those memory accesses. The proposed method optimizing memory accesses achieves a performance improvement of about 65 times over the base hardware. As a result, the proposed method improved performance by about 1.4 times and 50 times compared to the software execution on a PC and an embedded CPU respectively.

DOI： 10.1007/978-3-031-29927-8_5

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85159485982&origin=inward

High-level Synthesized Hardware of Fundamental Morphological Operation and its Application 査読有り国際誌

Daiki Okamoto, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 276 - 281 2023年03月

Investigation Toward Realization of High-level Synthesizable Sprite Moving Functions 査読有り国際誌

Kyota Matsuda, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 269 - 275 2023年03月

Development of Relationship Interface between High-level Synthesis and Web Browser-based Hardware Verification System with Virtual Peripheral 査読有り国際誌

Tomomi Yoshizuka, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 320 - 324 2023年03月

Introduction Hardware Switching Functionality to Web browser-based FPGA Hardware Verification System 査読有り国際誌

Tomomi Yoshizuka, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 315 - 319 2023年03月

An investigation of software describing methods to design dual background scrolling hardware in high-level synthesis 査読有り国際誌

Lee K., Yamawaki A.

Artificial Life and Robotics 28 ( 3 ) 547 - 552 2023年03月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

DOI： 10.1007/s10015-023-00866-y

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85150612783&origin=inward

Hardware Development of Virtual Background Scrolling Independent on Physical Resolution in High-level Synthesis 査読有り国際誌

Kilryong Lee, Akira Yamawaki

Proceedings of The 28th International Symposium on Artificial Life and Robotics 2023 (AROB 2023) 725 - 728 2023年01月

Development of image uploading function in Web browser-based FPGA Hardware Verification System 査読有り国際誌

Tomomi Yoshizuka, Akira Yamawaki

Proceedings of The 28th International Symposium on Artificial Life and Robotics 2023 (AROB 2023) 736 - 739 2023年01月

Effect of Line Segment Size on Pencil Drawing-like Image Conversion Hardware Developed by High-level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of The 28th International Symposium on Artificial Life and Robotics 2023 (AROB 2023) 740 - 743 2023年01月

Development of High-level Synthesis Oriented Background Scroll Function Considering Hierarchy of Game Display Frame 査読有り国際誌

Lee K., Yamawaki A.

Proceedings of IEEE Region 10 Annual International Conference 2022 (TENCON2022) 2022-November 2022年11月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

2022年11月01日 - 2022年11月04日

We are developing background scrolling function in High-Level Synthesizable game programing library to realize high-performance and power-saving mobile terminals executing game applications by using hardware execution in Field Programmable Gate Array, FPGA. High-Level Synthesis converts software into hardware automatically and it can reduce heavy burden of hardware development. In game application, display resolution has not to be always same as game screen size. The hierarchy layering game screens with varying sizes on the display frame may provide more engaging effect to the game application. In such case like the size of game screen differs from the display resolution, the appropriate integration of the updated game screen into the display frame is required. Performing updating and embedding the game screen individually may lead to degrade the performance of hardware because useless memory copies become bottleneck. To solve this problem for the background scrolling on the game screen, we extend our function to fit the background scrolled to physical display resolution simultaneously. That is, this paper proposes a high-level synthesizable software description method for background scrolling considering hierarchy of display frame and evaluates this effect.

DOI： 10.1109/TENCON55691.2022.9977798

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85145664621&origin=inward

Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction 査読有り国際誌

Shinyamada K., Yamawaki A.

Artificial Life and Robotics 27 ( 3 ) 541 - 546 2022年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was N= 4 , which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing.

DOI： 10.1007/s10015-022-00777-4

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85134528992&origin=inward

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration 査読有り国際誌

Shojima A., Yamawaki A.

Artificial Life and Robotics 27 ( 3 ) 554 - 560 2022年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

The verification of image processing hardware using FPGAs requires various peripherals. Although commercially available FPGA boards also include peripherals, it is necessary to design and implement interface circuits to use them. Furthermore, since each board has different peripherals, new interfaces have to be designed each time. Also, these interface circuits are not generated by HLS. Therefore, we are developing a hardware verification environment that is independent of the peripherals of FPGA boards. The verification environment we proposed last time consists of a general-purpose FPGA board, a PC, and server/client programs running on the PC and on the CPU of the FPGA board. By virtualizing the peripherals to be installed in the product on the PC, verification can be performed regardless of the peripherals on the FPGA board. TCP/IP communication also makes it possible to verify huge images. However, in this verification environment, each verification has to be compiled on the FPGA implementation tool. Therefore, in this paper, we aim to create a verification environment in which hardware can be replaced dynamically during verification by implementing DPR.

DOI： 10.1007/s10015-022-00772-9

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85133573194&origin=inward

仮想周辺機器を備えた高位合成画像処理ハードウェア向け汎用検証環境招待有り

山脇彰, 庄嶋篤

画像ラボ ( 日本工業出版 ) 33 ( 5 ) 20 - 27 2022年05月

Background scrolling in high-level synthesis oriented game programing library 査読有り国際誌

Lee K., Yamawaki A.

Artificial Life and Robotics 27 ( 3 ) 455 - 460 2022年04月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

We are developing a game programing library which can be converted to hardware modules by high-level synthesis, HLS technology to realize high-performance and low-power mobile terminals executing game applications. High-level synthesis is a technology that converts software into hardware automatically. The game software is executed by high-speed and low-power hardware on the reconfigurable devices in the mobile terminals instead of power-hungry software execution. To make high-level synthesis tool generate a desirable hardware module, we must describe software program well considering the hardware organization. In this paper, we develop a background scrolling processing as one of functions in high-level synthesis-oriented game software library. The pure software to realize the background scrolling has two nested loops accessing to the same array in the main loop. The former loop must finish all read and write accesses to the arrays before starting the operations of the latter loop. This prevents the latter loop starting in parallel to the former loop even if they have some parallelism. As a result, it disturbs making hardware high-speeded and well-pipelined by high-level synthesis tool and may lead to a significant latency. In this paper, we show a program description method to avoid this problem. With this method, high-level synthesis tool may convert background scrolling processing efficiently. In addition, we also evaluate the execution time, resource usage and power consumption of the hardware module that high-level synthesis generated through the experiment.

DOI： 10.1007/s10015-022-00758-7

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85128090736&origin=inward

Development of an Embedded Device with Motion Detection by Dynamic Background Subtraction Using High-Level Synthesis 査読有り国際誌

Kohei Shinyamada, Akira Yamawaki

Proceedings of The 10th IIAE International Conference on Industrial Application Engineering 2022 ( 産業応用工学会 ) 173 - 180 2022年03月

動的背景差分による動体検知機能を備えたカメラ搭載組み込みシステムの高位合成を用いた開発査読有り

新山田公平, 山脇　彰

産業応用工学会論文誌 ( 産業応用工学会 ) 10 ( 1 ) 10 - 17 2022年03月

担当区分：最終著者,　責任著者記述言語：日本語掲載種別：研究論文（学術雑誌）

Hardware-based image processing is suitable for embedded systems because of its high speed and low power consumption. In addition, by using the technology of high-level synthesis, the creation of hardware can be done quickly and flexibly. In this study, we developed an embedded system with a camera that has a median-based dynamic background subtraction function. In this system, we introduced the concept of a ring buffer to run three pieces of hardware in parallel. As a result, when the image size is QVGA and the number of time-series images is 4, the maximum frame rate of the system is 194 fps. In addition, it was confirmed that the power efficiency of the system was much better than that of software processing.

DOI： 10.12792/jjiiae.10.1.10

CiNii Research

その他リンク： https://www.jstage.jst.go.jp/article/jjiiae/10/1/10_10/_article/-char/ja

An Investigation of Software Describing Method to Design Dual Background Scrolling Hardware in High-level Synthesis 査読有り国際誌

Kilryong Lee, Akira Yamawaki

Proceedings of The 27th International Symposium on Artificial Life and Robotics 2022 (AROB 2022) 697 - 700 2022年01月

Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction 査読有り国際誌

Kohei Shinyamada, Akira Yamawaki

Proceedings of The 27th International Symposium on Artificial Life and Robotics 2022 (AROB 2022) 782 - 786 2022年01月

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration 査読有り国際誌

Atsushi Shojima,, Akira Yamawaki

Proceedings of The 27th International Symposium on Artificial Life and Robotics 2022 (AROB 2022) 750 - 755 2022年01月

Building Primitive Functionality of Web browser-based FPGA Hardware Verification System 査読有り国際誌

Tomomi Yoshizuka, Akira Yamawaki

Proceedings of The 27th International Symposium on Artificial Life and Robotics 2022 (AROB 2022) 706 - 709 2022年01月

Development of Haze Removing Hardware Using High-Level Synthesis 査読有り国際誌

Shirai D., Yamawaki A.

Proceedings of International Conference on Artificial Life and Robotics ( 株式会社ALife Robotics ) 27 612 - 615 2022年01月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We have developed a hardware for low-power and high-speed haze removing to sharpen hazy images in batterypowered embedded image processing systems such as drones. For development, we used HLS (High-Level Synthesis), which automatically converts software into hardware. In this paper, we evaluate the performance and power efficiency of the hardware obtained by high-level synthesis based on the haze removing software developed considering the hardware specifications and show its effectiveness.

DOI： 10.5954/icarob.2022.os15-4

Scopus

CiNii Research

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85125148066&origin=inward

Hardware Development of Edge-Preserving Bubble Image Conversion in High-level Synthesis 査読有り国際誌

Qin J., Yamawaki A.

Proceedings of International Conference on Artificial Life and Robotics ( 株式会社ALife Robotics ) 27 608 - 611 2022年01月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The non-photorealistic rendering, NPR, is widely used in social networking service on the mobile device. To realize a real time NPR with low power making battery life of mobile device longer, we attempt to develop hardware module by using high-level synthesis, HLS, converting software to hardware automatically. This research focuses on edgepreserving bubble image, EPB, converting photos into image like filled with bubbles. We proposed a software description method for EPB algorithm so that HLS can generate a high-performance and low-power hardware module. Through the practical experiments, we show that our proposed description method can make HLS generate good hardware module improving the performance and power efficiency compared with the conventional method.

DOI： 10.5954/icarob.2022.os15-3

Scopus

CiNii Research

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85125150712&origin=inward

Development of High Performance Hardware by High-Level Synthesis of Median-Based Dynamic Background Subtraction Method with Multiple Line Buffers 査読有り国際誌

Shinyamada K., Yamawaki A.

Proceedings of IEEE Region 10 Annual International Conference 2021(TENCON2021) 2021-December 123 - 127 2021年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

オンライン 2021年12月07日 - 2021年12月10日

Hardware processing is suitable for embedded image processing systems because of its lower power consumption and higher performance compared to software processing. To facilitate development, a tool called high-level synthesis, which automatically converts high-level languages into hardware description languages, is used. However, high-level synthesis of pure software does not necessarily generate efficient hardware. In this study, we attempted to generate high-performance image processing hardware using a median-based dynamic background subtraction method. As a result, we found that high-performance hardware can be generated when multiple line buffers are introduced. Compared to the non-introduced one, the performance was improved by about 13 times.

DOI： 10.1109/TENCON54134.2021.9707206

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85125966122&origin=inward

Omnidirectional Background Scrolling in High-Level Synthesis Oriented Game Programing Library 査読有り国際誌

Lee K., Yamawaki A.

Proceedings of IEEE Region 10 Annual International Conference 2021 (TENCON2021) 2021-December 140 - 144 2021年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

オンライン 2021年12月07日 - 2021年12月10日

We are developing a game programing library which can be converted to good hardware modules by high-level synthesis, HLS, technology to realize high-performance and low-power mobile terminals executing game applications. High level synthesis, HLS, is a technology that converts software into hardware automatically. Some power-hungry parts of game software are executed by high-speed and low-power hardware on the reconfigurable devices in the mobile terminals. To make an HLS tool generate a desirable hardware module, we must describe software program well considering the hardware organization. In previous study, we developed the software describing method for horizontal background scrolling. This method improved the performance of HLS hardware significantly. In this paper, we are going to propose software description method for omnidirectional background scrolling based on previous study. With this method, HLS tool may convert background scrolling processing efficiently. In addition, we also evaluate the execution time, resource usage and power consumption of the hardware module that HLS generated through experiment.

DOI： 10.1109/TENCON54134.2021.9707379

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85125964637&origin=inward

Development of a Simple Verification Environment Using FPGA for image processing Hardware Created by High-Level-Synthesis Using TCP/IP 査読有り国際誌

Atsushi Shojima, Akira Yamawaki

Proceedings of the 8th IIAE International Conference on Intelligent Systems and Image Processing 2021 ( 産業応用工学会 ) 221 - 226 2021年09月

Effect of Sorting Algorithms on High-level Synthesized Image Processing Hardware 査読有り国際誌

Kohei Shinyamada, Akira Yamawaki

Proceedings of the 8th IIAE International Conference on Intelligent Systems and Image Processing 2021 ( 産業応用工学会 ) 16 - 20 2021年09月

Hardware Development of Color Image Contrast Enhancement by High-level Synthesis 査読有り国際誌

Akira Yamawaki, Mitsunori Mizumachi, Seiichi Serikawa

Proceedings of IEEE Region 10 Symposium (TENSYMP) 2021 ( IEEE Region 10 ) 697 - 701 2021年08月

Hardware Development of Skylight Estimation Processing in Haze Removing Using High-level Synthesis 査読有り国際誌

Daiki Shirai,Akira Yamawaki

Proceedings of The 9th IIAE International Conference on Industrial Application Engineering 2021 (ICIAE2021) ( 産業応用工学会 ) 107 - 111 2021年03月

Development of Primitive Circuit in a Scalable and Flexible PWM Mechanism Using FPGA 査読有り国際誌

Soma Doi,Akira Yamawaki

Proceedings of The 9th IIAE International Conference on Industrial Application Engineering 2021 (ICIAE2021) ( 産業応用工学会 ) 264 - 267 2021年03月

An Investigation of Mobile Device Supporting Online Self-dynamic Partial Reconfiguration on a Testbed System 査読有り国際誌

Yuma Chihara,Akira Yamawaki

Proceedings of The 9th IIAE International Conference on Industrial Application Engineering 2021 (ICIAE2021) ( 産業応用工学会 ) 218 - 221 2021年03月

Development of Generic Software System Transparent to Any Flexible and Scalable Sensor Array 査読有り国際誌

Ryota Nakamura,Akira Yamawaki

Proceedings of The 9th IIAE International Conference on Industrial Application Engineering 2021 (ICIAE2021) ( 産業応用工学会 ) 212 - 217 2021年03月

Performance Effect of I/O Peripheral Dynamic Reconfiguration on FPGA 査読有り国際誌

Kazuki Hashimoto,Akira Yamawaki

Proceedings of The 9th IIAE International Conference on Industrial Application Engineering 2021 (ICIAE2021) ( 産業応用工学会 ) 208 - 211 2021年03月

Development of a Projection-type Simple Stereoscopic Display with a Touch Panel Functionality 査読有り国際誌

Ryosuke Sato,Akira Yamawaki

Proceedings of The 9th IIAE International Conference on Industrial Application Engineering 2021 (ICIAE2021) ( 産業応用工学会 ) 112 - 115 2021年03月

High-level synthesis-oriented program description method considering display output in embedded video image processing system 査読有り国際誌

Kohei Shinyamada,Akira Yamawaki

Proceedings of The Twenty-Sixth International Symposium on Artificial Life and Robotics 2021 (AROB 26th 2021) ( 人工生命とロボット国際学会 ) 388 - 393 2021年01月

Evaluation of communication performance between sensor nodes in a flexible and scalable sensor array 査読有り国際誌

Ryota Nakamura,Akira Yamawaki

Proceedings of The Twenty-Sixth International Symposium on Artificial Life and Robotics 2021 (AROB 26th 2021) ( 人工生命とロボット国際学会 ) 461 - 465 2021年01月

Background Scrolling in High-level Synthesis Oriented Game Programing Library 査読有り国際誌

Kilryong Lee,Akira Yamawaki

Proceedings of The Twenty-Sixth International Symposium on Artificial Life and Robotics 2021 (AROB 26th 2021) ( 人工生命とロボット国際学会 ) 414 - 417 2021年01月

Development of a simple verification environment using FPGA of image processing hardware created by High-Level-Synthesis 査読有り国際誌

Atsushi Shojima,Akira Yamawaki

Proceedings of The Twenty-Sixth International Symposium on Artificial Life and Robotics 2021 (AROB 26th 2021) ( 人工生命とロボット国際学会 ) 422 - 426 2021年01月

Development and Evaluation of Hardware Dynamic Link Library on FPGA running Linux 査読有り国際誌

Takuma Sono,Akira Yamawaki

Proceedings of The Twenty-Sixth International Symposium on Artificial Life and Robotics 2021 (AROB 26th 2021) ( 人工生命とロボット国際学会 ) 427 - 430 2021年01月

Investigation of Feasibility for FPGA based Zero Standby-power Type Sensor Node 査読有り国際誌

Akira Yamawaki

Proceedings of the 8th IIAE International Conference on Industrial Application Engineering 2020 (ICIAE2020) ( the Institute of Industrial Applications Engineers ) 265 - 268 2020年03月

Sensor Data Gathering Time from Multiple Zero Standby power-type Sensor Nodes Simultaneously Awaken 査読有り国際誌

Akira Yamawaki, Makoto Miyauchi, Seiich Serikawa

Proceedings of the 8th IIAE International Conference on Industrial Application Engineering 2020 (ICIAE2020) ( the Institute of Industrial Applications Engineers ) 171 - 175 2020年03月

Performance Improvement of Hardware by Series Duplicating Data Buffer for High-level Synthesis 査読有り国際誌

Moena Yamasaki, Akira Yamawaki

Proceedings of the 8th IIAE International Conference on Industrial Application Engineering 2020 (ICIAE2020) ( the Institute of Industrial Applications Engineers ) 176 - 181 2020年03月

Development of Histogram Equalization Hardware By High-level synthesis 査読有り国際誌

Akira Yamawaki, Makoto Miyauchi, Seiich Serikawa

Proceedings of the 8th IIAE International Conference on Industrial Application Engineering 2020 (ICIAE2020) ( the Institute of Industrial Applications Engineers ) 261 - 264 2020年03月

A performance evaluation of read/write burst transfer by high-level synthesizable software for the alpha blending processing 査読有り

Yamagata Y., Yamawaki A.

Artificial Life and Robotics 25 ( 2 ) 253 - 257 2020年01月

担当区分：責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

© 2020, International Society of Artificial Life and Robotics (ISAROB). High-level synthesis, HLS is a technology to convert the software into the hardware automatically. It is expected as a technology that can greatly reduce the load of the hardware development. However, the current HLS that cannot convert the software not considered the hardware configuration into the optimum hardware. One of characteristics of the hardware to be considered is the burst transfer of memory access. In this paper, we evaluate the burst transfer with a subject of alpha blending processing as a theme. It is necessary to describe the program, so that the HLS tool can implicitly infer the burst transfer, because HLS tool does not have a pragma designating the burst transfer. We consider the description method of the program to infer the burst transfer and clarify the influence of read/write burst transfer on alpha blending.

DOI： 10.1007/s10015-020-00590-x

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85081391351&origin=inward

Development of Filled Circle Drawing in High-level Synthesis Oriented Game Programming Library 査読有り国際誌

Yuki Yamagata, Akira Yamawaki

Proceedings of 20th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT2019) ( IEEE ) 280 - 284 2019年12月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

オーストラリアゴールドコースト 2019年12月05日 - 2019年12月07日

We are developing a high-level synthesizable software game library to realize high performance and low power mobile terminals executing game applications. High-level synthesis, HLS, is a technology that automatically converts software into hardware. Games developed by HLS oriented game software library are executed by high-speed and low-power hardware reconfigured on reconfigurable devices in mobile terminals. This paper develops a circle drawing processing as one of functions in HLS oriented game software library. We employ Michener's algorithm which is suitable for hardware implementation as a circle drawing algorithm because it just consists of simple integer operations. We also show the program description method so that HLS tool can convert the circle drawing processing based on Michener's algorithm to a good hardware module. The experiments evaluate the execution time and the amount of hardware of the hardware module HLS generated.

DOI： 10.1109/PDCAT46702.2019.00058

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?eid=2-s2.0-85083221623&doi=10.1109%2fPDCAT46702.2019.00058&partnerID=40&md5=6cdf55dc987a247f1f11891406bfa90b

Effect of Parallel Processing by Duplicating Histogram in Automatic Image Binarization for High-level Synthesis 査読有り国際誌

Moena Yamasaki, Akira Yamawaki

Proceedings of 20th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT2019) ( IEEE ) 534 - 537 2019年12月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

オーストラリアゴールドコースト 2019年12月05日 - 2019年12月07日

The high-level synthesis converting software to hardware automatically is one of the important technologies for significantly reducing the burden caused by developing hardware module. The embedded image processing products need the HLS to quickly implement a hardware module achieving high-performance with low-power consumption instead of software implementation for high-computational processing. However, the HLS tool cannot generate a hardware module with high-performance and low-power consumption expected when the software program without deep consideration about the hardware organization to be generated is input. This paper shows a software description method to extract some parallelisms by duplicating the histograms in the automatic image binarization which is called as Otsu's method in order to improve a performance of the hardware module HLS generates. The experimental results show the effect of our description method about the performance and the amount of hardware. We also discuss about a trade-off among the parallelism, performance and amount of hardware.

DOI： 10.1109/PDCAT46702.2019.00105

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?eid=2-s2.0-85083184174&doi=10.1109%2fPDCAT46702.2019.00105&partnerID=40&md5=17695de156279fc5c76e9282bcea1c93

Duplicating same argument of function to realize efficient hardware for high-level synthesis 査読有り

Yamasaki M., Yamawaki A.

Artificial Life and Robotics 25 ( 2 ) 248 - 252 2019年11月

担当区分：責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

© 2019, International Society of Artificial Life and Robotics (ISAROB). High-level synthesis (HLS) automatically converting software into hardware is a promising technology to reduce the design burden significantly. However, to use HLS technology efficiently, software program must be described considering the hardware organization that HLS tool will generate. We are developing the HLS image processing library. However, some caution is required when using HLS for programs that read images. When the same image is read through an argument of the function, the input port corresponding to this argument on the hardware generated by HLS tool may cause the port conflict. As a result, the image reading is made serialized and this serialization disturbs the performance of the data path well pipelined by the HLS tool. This paper shows how to write a software program to avoid this problem. In addition, we adapt this method to two image processing and evaluate the effect of our proposal to them.

DOI： 10.1007/s10015-019-00576-4

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85075883857&origin=inward

Description Method for High-level Synthesis of Histogram Generation and Their Evaluation 査読有り

Moena Yamasaki, Akira Yamawaki

IEIE Transactions on Smart Processing & Computing 8 ( 3 ) 178 - 185 2019年06月

Performance Evaluation of Dynamic Partial Reconfiguration on FPGA by Hardware Time Division Execution 査読有り国際誌

Satoshi Yonemitsu, Akira Yamawaki

Proceedings of the 7th IIAEInternational Conference on Industrial Application Engineering 2019 ( Institute of Industrial Applications Engineers ) 265 - 269 2019年03月

A Study of Dynamic Partial Reconfiguration on FPGA of High-level Synthesized Hardware 査読有り国際誌

Takuma Sono, Akira Yamawaki

Proceedings of the 7th IIAEInternational Conference on Industrial Application Engineering 2019 ( Institute of Industrial Applications Engineers ) 261 - 264 2019年03月

Implementation of a single device measuring two biological signals by using dynamic analog circuit reconfiguration 査読有り

Tetsuya Suematsu, Akira Yamawaki

Proceedings of The Twenty-Fourth International Symposium on Artificial Life and Robotics 2019 608 - 611 2019年01月

A Performance Evaluation of Read / Write Burst Transfer by High-level Synthesizable Software for the Alpha Blending Processing 査読有り

Yuki Yamagata, Akira Yamawaki

Proceedings of The Twenty-Fourth International Symposium on Artificial Life and Robotics 2019 563 - 566 2019年01月

Duplicating Same Argument of Function to Realize Efficient Hardware for High-level Synthesis 査読有り

Moena Yamasaki, Akira Yamawaki

Proceedings of The Twenty-Fourth International Symposium on Artificial Life and Robotics 2019 559 - 562 2019年01月

An Evaluation of Burst Transfer Inferred by a High-level Synthesis Tool 査読有り

Yamagata Y., Yamawaki A.

IEIE Transactions on Smart Processing and Computing 8 ( 2 ) 143 - 149 2019年01月

担当区分：責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

© 2019 Institute of Electronics and Information Engineers. All rights reserved. High-level synthesis (HLS) is technology that automatically converts software to digital hardware. HLS has gained attention as a promising technology that can reduce the burden of hardware development. However, if a software program converted by HLS does not consider organization of the hardware, the current HLS technology cannot convert software to proper digital hardware. One of the characteristics of the hardware to be considered is burst transfer to memory access. Burst transfer attempts to speed up memory access by packing continuous data into a single address. This paper discusses a rectangle-drawing case study that demonstrates how to describe a C program so an HLS tool can infer burst transfer with an arbitrary burst length. Moreover, we consider the necessity to suppress optimization performed by the HLS tool to prevent increasing the amount of digital hardware when we implement the arbitrary burst length. Experiments clarify how performance and the hardware scale change based on the difference in the burst length and suppression of optimization.

DOI： 10.5573/IEIESPC.2019.8.2.143

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85068577459&origin=inward

Proposal of an ultrasonic sensor array with flexible and scalable organization 査読有り

Yuichi Morita, Sota Kono, Akira Yamawaki

Artificial Life and Robotics 1 - 6 2018年12月

An Evaluation of Burst Transfer Inferred by a High-level Synthesis Tool 査読有り

Yuki Yamagata,Akira Yamawaki

Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference 2120 - 2123 2018年10月

Describing Methods for High-level Synthesis of Histogram Generation and Their Evaluation 査読有り

Moena Yamasaki, Akira Yamawaki

Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference 2116 - 2119 2018年10月

Development of Pre/Post-Integrated Image Processing Hardware by High Level Synthesis for Camera Sensor Node 査読有り

Sota Miura, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 244 - 248 2018年09月

Development of Memory Mapped Register and Bus Switch Circuit for Hardware Virtualization in GEDY 査読有り

Sota Kono, Satoshi Yonemitsu, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 137 - 141 2018年09月

Investigation of Measuring Multiple Biological Signals by Analog Circuit Dynamic Reconfiguration 査読有り

Tetsuya Suematsu, Yuta Suzuki, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 142 - 145 2018年09月

Design of Daisy-chain Connection for Flexible and Scalable Ultrasonic Sensor Array 査読有り

Yuichi Morita, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 132 - 136 2018年09月

An Investigation to Realize Zero Standby Strain Sensor Node 査読有り

Yuta Suzuki, Yuichi Morita, Akira Yamawaki

Proceedings of the 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2018 70 - 73 2018年07月

Development of Image Compression Hardware by High level Synthesis for Wireless Camera Sensor Node 査読有り

Sota Miura, Akira Yamawaki

Proceedings of the 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2018 290 - 293 2018年07月

A Command List Based Automatic Controlling Method of UAV for Infrastructure Monitoring System with Zero-standby Sensor Node 査読有り

Yuta Suzuki, Shogo Yoshikawa, Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 215 - 218 2018年03月

A Consideration to Develop a High-level Synthesizable Software Game Library 査読有り

Yuki Yamagata,Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 202 - 205 2018年03月

Effect of Redundant Function Execution to Reduce Memory Access on High-level Synthesis 査読有り

Moena Yamasaki, Satoshi Yonemitsu, Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 206 - 209 2018年03月

Development of Image Processing Hardware by High-level Synthesis for High Performance and Low-power Camera Sensor Node on Wireless Sensor Network 査読有り

Sota Miura, Ayumi Mise, Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 210 - 214 2018年03月

A describing method of an image processing software in C for a high-level synthesis considering a function chaining 査読有り国際誌

Yamawaki A., Serikawa S.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E101D ( 2 ) 324 - 334 2018年02月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

© Copyright 2018 The Institute of Electronics, Information and Communication Engineers. This paper shows a describing method of an image processing software in C for high-level synthesis (HLS) technology considering function chaining to realize an efficient hardware. A sophisticated image processing would be built on the sequence of several primitives represented as sub-functions like the gray scaling, filtering, binarization, thinning, and so on. Conventionally, generic describing methods for each subfunction so that HLS technology can generate an efficient hardware module have been shown. However, few studies have focused on a systematic describing method of the single top function consisting of the sub-functions chained. According to the proposed method, any number of sub-functions can be chained, maintaining the pipeline structure. Thus, the image processing can achieve the near ideal performance of 1 pixel per clock even when the processing chain is long. In addition, implicitly, the deadlock due to the mismatch of the number of pushes and pops on the FIFO connecting the functions is eliminated and the interpolation of the border pixels is done. The case study on a canny edge detection including the chain of some sub-functions demonstrates that our proposal can easily realize the expected hardware mentioned above. The experimental results on ZYNQ FPGA show that our proposal can be converted to the pipelined hardware with moderate size and achieve the performance gain of more than 70 times compared to the software execution. Moreover, the reconstructed C software program following our proposed method shows the small performance degradation of 8% compared with the pure C software through a comparative evaluation preformed on the Cortex A9 embedded processor in ZYNQ FPGA. This fact indicates that a unified image processing library using HLS software which can be executed on CPU or hardware module for HW/SW co-design can be established by using our proposed describing method.

DOI： 10.1587/transinf.2017RCP0001

Scopus

CiNii Article

CiNii Research

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85041503725&origin=inward

Proposal of an Ultrasonic Sensor Array with Flexible and Scalable Organization 査読有り

Yuichi Morita, Sota Kono, Akira Yamawaki

Proceedings of The Twenty-Third International Symposium on Artificial Life and Robotics 2018 381 - 384 2018年01月

A Unified Detection Method of Indoor Three Events by Dynamic Reconfiguration of Analog Circuit 査読有り

Tetsuya Suematsu, Yasunobu Takaichi, Akira Yamawaki

Proceedings of the 5th International Conference on Intelligent Systems and Image Processing 2017 381 - 386 2017年09月

Door Monitoring System Using Sensor Node with Zero Standby Power 査読有り

Akira Yamawaki, Seiichi Serikawa

Transactions on Engineering Technologies: International MultiConference of Engineers and Computer Scientists 2016 73 - 87 2017年05月

Development of Analog to Digital Interface for Scalable Ultrasonic Sensor Array 査読有り

Yuichi Morita, Sota Kono, Akira Yamawaki

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017 159 - 164 2017年03月

Development of Wireless Monitoring Device for Window Security using Light Sensor 査読有り

Ryuji Funemizu, Yasunobu Takaichi, Akira Yamawaki

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017 340 - 345 2017年03月

A Fire Alarm Sensor Node with Long Battery Life by Zero Standby Power Consumption 査読有り

Toru Kuwatani, Yasunobu Takaichi, Akira Yamawaki

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017 327 - 330 2017年03月

An Architecture of Energy Efficient Restroom by Making Zero Standby Power 査読有り

Karen Shibasaki, Sota Kono, Akira Yamawaki

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017 323 - 326 2017年03月

Power Saving Effect of Dynamic Partial Reconfiguration on FPGA 査読有り

Satoshi Yonemitsu, Sota Kono, Akira Yamawaki

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017 165 - 170 2017年03月

Development of Reconfiguration unit for General Purpose Microcomputer with Dynamic Partial Reconfiguration 査読有り

Sota Kono, Gen Nishizawa, Akira Yamawaki

Proceedings of the 4th IIAE International Conference on Intelligent Systems and Image Processing 2016 229 - 232 2016年09月

Wake-up time Measurement of Wireless Sensor Node with Zero Standby-power 査読有り

Yasunobu Takaichi, Daichi Koide, Akira Yamawaki

Proceedings of the 4th IIAE International Conference on Intelligent Systems and Image Processing 2016 225 - 228 2016年09月

A Scalable Organization of 2-D Ultrasonic Sensor Array 査読有り

Yuichi Morita, Yasunobu Takaichi, Akira Yamawaki

Proceedings of the 4th IIAE International Conference on Intelligent Systems and Image Processing 2016 155 - 159 2016年09月

Battery Life Estimation of Sensor Node with Zero Standby Power Consumption 査読有り

Akira Yamawaki, Seiichi Serikawa

Proceedings of 19th IEEE International Conference on Computational Science and Engineering 166 - 172 2016年08月

High-level Synthesis Oriented Describing Method of Template Matching 査読有り

Miyu Fujita, Kazunari Yosikawa, Naohiro Iwanaga, Akira Yamawaki

Proceedings of the 4th IIAE International Conference on Industrial Application Engineering 2016 20 - 24 2016年03月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本別府 2016年03月26日 - 2016年03月30日

DOI： 10.12792/iciae2016.008

その他リンク： https://www2.ia-engineers.org/conference/index.php/iciae/iciae2016/paper/view/971/652

Applying sensor node with zero standby power to door monitor 査読有り

Yamawaki A., Serikawa S.

Lecture Notes in Engineering and Computer Science 2 576 - 580 2016年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

For the wireless sensor network (WSN), one of the most significant problems is the battery exchange for many sensor nodes. To make the battery changing rarely happen, we have proposed the sensor node architecture with zero standby power. We performed the preliminary experiments for the proposed node. However, we have never shown an application realized by it. In this paper, we demonstrate an application using our sensor node as the door monitor. The result of the case study have shown that our proposed sensor node can Implement a door monitoring system In the WSN and significantly reduced the power consumption during the standby compared with the conventional one.

Scopus

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A sensor node architecture with zero stanby power on wireless sensor network 招待有り査読有り

Akira Yamawaki, Mayu Yamanaka, Seiichi Serikawa

Artificial Life and Robotics 20 ( 3 ) 210 - 216 2015年10月

Improvement of Display Unit in Generic Verification Environment for Video Image Processing Hardware on FPGA 査読有り

Gen Nishizawa, Kazunari Yoshikaw, Akira Yamawaki

Proceedings of the 3rd IIAE International Conference on Intelligent Systems and Image Processing 2015 21 - 25 2015年09月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本福岡 2015年09月02日 - 2015年09月05日

DOI： 10.12792/icisip2015.007

その他リンク： https://www2.ia-engineers.org/conference/index.php/icisip/icisip2015/paper/view/837/545

Remote power strip with zero standby power controllable from every direction 査読有り

Daichi Koide, Kazunari Yoshikawa, Akira Yamawaki

Proceedings of the 3rd IIAE International Conference on Intelligent Systems and Image Processing 2015 3 - 6 2015年09月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本福岡 2015年09月02日 - 2015年09月05日

DOI： 10.12792/icisip2015.003

その他リンク： https://www2.ia-engineers.org/conference/index.php/icisip/icisip2015/paper/view/756/546

Remote Power Switch to Make Standby Power of Infrared Remote Controlled Product Zero 招待有り査読有り

Akira Yamawaki, Seiichi Serikawa

IAENG International Journal of Computer Science 42 ( 2 ) 132 - 138 2015年04月

Remote controlled power strip to make standby power consumption zero 査読有り

Daichi Koide, Mayu Yamanaka, Daisuke Tanaka, Takuya Itahashi, Akira Yamawaki

Proceedings of the 3rd International Conference on Industrial Application Engineering 2015 218 - 222 2015年03月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本北九州 2015年03月28日 - 2015年03月31日

DOI： 10.12792/iciae2015.041

その他リンク： https://www2.ia-engineers.org/conference/index.php/iciae/iciae2015/paper/view/633/413

Comparative Evaluation between Fixed and Floating Point Hardware Implementation of Image Conversion on High-level Synthesis 査読有り

Miyu Fujita, Kazunari Yosikawa, Naohiro Iwanaga, Akira Yamawaki

Proceedings of the 3rd International Conference on Industrial Application Engineering 2015 625 - 628 2015年03月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本北九州 2015年03月28日 - 2015年03月31日

DOI： 10.12792/iciae2015.108

その他リンク： https://www2.ia-engineers.org/conference/index.php/iciae/iciae2015/paper/view/641/481

Power Supply Circuit With Zero Standby Power Consumption on Infrared Remote Controlled Product by Using Energy Harvesting 査読有り

Akira Yamawaki, Seiichi Serikawa

Proceedings of the International MultiConference of Engineers and Computer Scientists 2015 2 655 - 660 2015年03月

A sensor node architecture with zero standby-power on wireless sensor network 査読有り

Akira Yamawaki, Mayu Yamanaka, Seiichi Serikawa

Proceedings of The Twentieth International Symposium on Artificial Life and Robotics 2015 455 - 460 2015年01月

Primary Experiment on a Prototype Hardware of a Supporting System for Visually Impaired People Operating Touchscreen 査読有り

Tatsuya Hamachi, Akira Yamawaki, Seiichi Serikawa

Proceedings of The Twentieth International Symposium on Artificial Life and Robotics 2015 243 - 248 2015年01月

A Single Pass Design Flow for Mixed-signal Reconfigurable Processor 査読有り

Akira Yamawaki, Seiichi Serikawa

Proceedings of 2014 International Workshop on Smart Info-Media Systems in Asia (SISA 2014) 58 - 63 2014年10月

Development of Remote Controllable Patrol Robot with Fire Extinguishing Function 査読有り

Hayato Takahashi, Daichi Takeshita, Akira Yamawaki, Seiichi Serikawa, Yuhki Kitazono

Proceedings of the 2nd International Conference onIntelligent Systems and Image Processing 2014 404 - 407 2014年09月

Development of Fixed-point Simulataneous Square Root and Logarithm Operations for High-level Synthesis 査読有り

Kazunari Yoshikawa, Naohiro Iwanaga, Tatuya Hamachi, Akira Yamawaki

Proceedings of the 2nd International Conference onIntelligent Systems and Image Processing 2014 264 - 269 2014年09月

An Implementation of Application Design Framework for a Dressed-up Touchscreen with a Tactile Feedback 査読有り

Mayu yamanaka, Makoto Miyauchi, Akira Yamawaki

Proceedings of the 2nd International Conference onIntelligent Systems and Image Processing 2014 30 - 37 2014年09月

触覚を有した着せ替え可能なタッチパネルの実現査読有り

山中麻由,山脇彰,芹川聖一

産業応用工学会論文誌 2 ( 2 ) 44 - 49 2014年09月

Application Design Framework for a Dressed-up Touchscreen 招待有り査読有り

Mayu Yamanaka, Yosuke Uchimura, Akira Yamawaki

Journal of the Institute of Industrial Applications Engineers 2 ( 2 ) 54 - 57 2014年04月

Development of Fixed-point Square Root Operation for High-level Synthesis 査読有り

Kazunari Yoshikawa,Naohiro Iwanaga,Akira Yamawaki

Proceedings of the 2nd International Conference on Industrial Application Engineering 2014 16 - 20 2014年03月

Effect of Parallel Processing on a Generic SoC Platform Using Dynamic Partial Reconfiguration 査読有り

Hiroyuki Tanabe, Kohei Miyata, Akira Yamawaki

INFORMATION 17 ( 2 ) 529 - 538 2014年02月

A Flexible Touch Switch with Arbitrary Shape and Arrangement 査読有り

Inoue Shun, Akira Yamawaki, Seiichi Serikawa

Journal of the Institute of Industrial Applications Engineers 1 ( 2 ) 52 - 55 2013年10月

Recognition of Road Mirror with Vehicle Camera 査読有り

Atsushi Kobayashi,Akira Yamawaki,Seiichi Serikawa

Proceedings of the 1st International Conference on ntelligent Systems and Image Processing 2013 175 - 178 2013年09月

Application Design Framework for a Dressed-up Touchscreen with a Tactile Feedback 査読有り

Mayu Yamanaka, Yosuke Uchimura, Akira Yamawaki

Proceedings of the 1st International Conference on ntelligent Systems and Image Processing 2013 4 - 7 2013年09月

Development of Fixed-point Trigonometric Function Library for High-level Synthesis 査読有り

Naohiro Iwanaga, Takayoshi Abe, Akira Yamawaki

Proceedings of the 1st International Conference on ntelligent Systems and Image Processing 2013 91 - 94 2013年09月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Kitakyushu 2013年09月26日 - 2013年09月27日

DOI： 10.12792/icisip2013.021

その他リンク： https://www2.ia-engineers.org/conference/index.php/icisip/icisip2013/schedConf/presentations

Hardware Platform of Camera-control Part on a Supporting System for Visually Impaired People Operating Touchscreen 査読有り

Tatsuya Hamachi,Takayoshi Abe,Akira Yamawaki

Proceedings of the 1st International Conference on ntelligent Systems and Image Processing 2013 95 - 98 2013年09月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Kitakyushu 2013年09月26日 - 2013年09月27日

DOI： 10.12792/icisip2013.022

その他リンク： https://www2.ia-engineers.org/conference/index.php/icisip/icisip2013/schedConf/presentations

Design of Water Level Sensor with Two-Pairs Capacitor 査読有り

Seiichi Serikawa, Yuhki Kitazono, Huimin Lu, Akira Yamawaki, Makoto Miyauchi

Journal of the Institute of Industrial Applications Engineers 1 ( 1 ) 11 - 14 2013年07月

Development of a Haptic Device Expressing Hardness of the Virtual Object Using Solenoid 査読有り

Shenjing Chen, Yuya Kawahara, Akira Yamawaki, Seiichi Serikawa

Journal of the Institute of Industrial Applications Engineers 1 ( 1 ) 43 - 47 2013年07月

Image Processing Flow on a Supporting System with Finger Camera for Visually Impaired People Operating Capacitive Touchscreen 招待有り査読有り

Akira Yamawaki, Seiichi Serikawa

IAENG International Journal of Computer Science 40 ( 2 ) 81 - 86 2013年05月

A Generic Verification Environment for Video Processing Hardware 査読有り

Takayoshi Abe, Hiroyuki Tanabe, Akira Yamawaki

Proceedings of the 1st International Conference on Industrial Applications Engineering 2013 236 - 239 2013年03月

A Realization of The Dressed-up Touchscreen With A Tactile Feedback 査読有り

Mayu Yamanaka, Ryohsuke Suzue, Akira Yamawaki

Proceedings of the 1st International Conference on Industrial Applications Engineering 2013 21 - 27 2013年03月

Effect of parallel processing on a generic SoC platform using DPR 査読有り

Hiroyuki Tanabe, Kohei Miyata, Akira Yamawaki

Proceedings of the 1st International Conference on Industrial Applications Engineering 2013 158 - 161 2013年03月

Proposal of a touch switch with arbitrary form and arrangement 査読有り

Shun Inouea,Kiyotada Matsura,Akira Yamawakia

Proceedings of the 1st International Conference on Industrial Applications Engineering 2013 162 - 168 2013年03月

Development of a Generic RGB to HSV Hardware 査読有り

Tatsuya Hamachi, Hiroyuki Tanabe, Akira Yamawaki

Proceedings of the 1st International Conference on Industrial Applications Engineering 2013 169 - 173 2013年03月

Hardware of the Elementary Function by CORDIC 査読有り

Naohiro Iwanaga, Hiroyuki Tanabe, Akira Yamawaki

Proceedings of the 1st International Conference on Industrial Applications Engineering 2013 182 - 185 2013年03月

Development of a Haptic Device Expressing Hardness of the Virtual Object Using Solenoid 査読有り

Shenjing Chen, Yuya Kawahara, Akira Yamawaki

Proceedings of the 1st International Conference on Industrial Applications Engineering 2013 202 - 206 2013年03月

指先カメラを用いた視覚障がい者向けタッチパネル操作支援システムにおける画像処理のハードウェア化査読有り

山脇彰,芹川聖一

産業応用工学会論文誌 1 ( 1 ) 10 - 19 2013年03月

A describing method of latency tolerant hardware for a pure ANSI-C/C++based high-level synthesis technology 査読有り

Akira Yamawaki,Seiichi Serikawa

The Eighteenth International Symposium on Artificial Life and Robotics 2013 387 - 390 2013年01月

A generic SoC platform using DPR feature to improve social life 査読有り

Hiroyuki Tanabe,Kohei Miyata,Akira Yamawaki,Seiichi Serikawa

2012 IEEE/SICE International Symposium on System Integration 125 - 128 2012年12月

A lightweight sensing method of tooth-touch sound for disabled person using remote controller 招待有り査読有り

Akira Yamawaki, Seiichi Serikawa

Journal on Artificial Life and Robotics 17 ( 2 ) 322 - 329 2012年12月

Multimodal Medical Image Fusion in Extended Contourlet Transform Domain 査読有り

Seiichi Serikawa, Huimin Lu, Yujie Li, Lifeng Zhang, Shiyuan Yang, Akira Yamawaki, Shota Nakashima, Yuhki Kitazono

Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing 2012 443 215 - 226 2012年08月

A Generic Describing Method of Memory Latency Hiding in a High-level Synthesis Technology 査読有り

Akira Yamawaki,Seiichi Serikawa

ACEEE International Journal on Information Technology 2 ( 2 ) 51 - 55 2012年04月

A lightweight sensing method of tooth-touch sound for disabled person using remote controller 査読有り

Akira Yamawaki, Seiichi Serikawa

Seventeenth International Symposium on Artificial Life and Robotics 774 - 778 2012年01月

A Wearable Supporting System for Visually Impaired People in Operating Capacitive Touchscreen 査読有り

Akira Yamawaki, Seiichi Serikawa

Applied Mechanics and Materials 103 687 - 694 2011年09月

High-level Synthesis Method Using Semi-programmable Hardware for C Program with Memory Access 招待有り査読有り

Akira Yamawaki,Masahiko Iwane

Engineering Letters 19 ( 1 ) 50 - 56 2011年02月

Introducing Semi-programmable Hardware to a Real High-Level Synthesis Tool 査読有り

Akira Yamawaki,Seiichi Serikawa,Masahiko Iwane

International Conference on Computer Science and Applications 2010 1 175 - 180 2010年10月

表示能力と汎用性が高い実ハードウェアを用いたプロセッサ教育支援システム査読有り

山脇彰,芹川聖一

電子情報通信学会論文誌D J93-D ( 10 ) 2058 - 2068 2010年10月

An Architecture of Prototyping System for Dynamic Partial Reconfiguration on FPGA 査読有り

Akira Yamawaki,Seiichi Serikawa

International Conference on Engineering of Reconfigurable Systems & Algorithms 163 - 166 2010年07月

A method using the same light sensor for detecting multiple events near a window in crimes involving intrusion into a home 査読有り

Akira Yamawaki,Takayuki Katakami,Yuhki Kitazono,Seiichi Serikawa

Artificial Life and Robotics 15 ( 1 ) 30 - 31 2010年07月

侵入窃盗における窓と鍵に対する3事象の光センサを用いた検知方式査読有り

山脇彰,片上貴之,北園優希,芹川聖一

電気学会論文誌E 130 ( 4 ) 137 - 138 2010年04月

An Efficient Hardware Architecture from C Program with Memory Access to Hardware 査読有り

Akira Yamawaki,Seiichi Serikawa,Masahiko Iwane

The 2010 International Conference on Computational Science and Its Applications, Part II, LNCS 6017 488 - 502 2010年03月

A Method Using Same Light Sensor for Detecting Multiple Events on Window in Home Intruding Crime 査読有り

Akira Yamawaki,Takayuki Katakami,Yuhki Kitazono,Seiichi Serikawa

The 15th International Symposium on Artificial Life and Robotics 1026 - 1028 2010年02月

An Educational Processor System with Visualization Mechanism using VGA 査読有り

Akira Yamawaki,Seiichi Serikawa

The 3rd Asia Pacific Embedded Systems Education and Research Conference S401 - S406 2009年12月

メモリアクセスを伴ったプログラムのFPGA実装に適したハードウェアアーキテクチャ査読有り

山脇彰,岩根雅彦

電子情報通信学会論文誌D J92-D ( 12 ) 2114 - 2126 2009年12月

An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware 査読有り

Akira Yamawaki,Seiichi Serikawa,Masahiko Iwane

The 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms (ERSA 2009) 233 - 239 2009年07月

セミプログラマブルハードウェアによる画像フィルタ用バッファリング手法の検討査読有り

山脇彰,岩根雅彦

電子情報通信学会論文誌A J92-A ( 3 ) 193 - 196 2009年03月

An Intermediate Hardware Model with Load/Store Unit for C to FPGA 査読有り

Akira Yamawaki,Masahiko Iwane

Seventeenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 279 - 279 2009年02月

An FPGA Implementation of a DWT with 5/3 Filter Using Semi-Programmable Hardware 査読有り

Akira Yamawaki,Kazuharu Morita,Masahiko Iwane

The 2008 IEEE Asia Pacific Conference on Circuits and Systems 709 - 712 2008年12月

FPGAベースオンチップマルチプロセッサにおける同期付きキャッシュメモリの実装と評価査読有り

山脇彰,岩根雅彦

情報処理学会論文誌 49 ( 4 ) 1657 - 1668 2008年04月

A Programmable Load/Store Unit on C-based Hardware Design for FPGA 査読有り

Akira Yamawaki,Masahiko Iwane

IEEE International Conference on Field-Programmable Technology 2007 361 - 364 2007年12月

An FPGA Implementation of a Snoop Cache with Synchronization for a Multiprocessor System-On-Chip 査読有り

Akira Yamawaki,Masahiko Iwane

The 13th International Conference on Parallel and Distributed Systems (ICPADS'2007) 1 1 - 8 2007年12月

チップマルチプロセッサの同期付きキャッシュメモリに対するミスペナルティ隠蔽機構査読有り

山脇彰,岩根雅彦

情報処理学会論文誌 47 ( 2 ) 566 - 581 2006年02月

Coherence Maintenances to Realize an Efficient Parallel Processing for a Cache Memory with Synchronization on a Chip-Multiprocessor 査読有り

Akira Yamawaki,Masahiko Iwane

The 8th IEEE/ACM International Symposium on Parallel Architectures,Algorithms, and Networks 324 - 331 2005年12月

An Efficient Parallel Processing Using a Cache Memory With Synchronization on a SOC-multiprocessor 査読有り

Akira Yamawaki,Masahiko Iwane

International Conference on Circuits, Signals, and Systems (CSS 2005) 142 - 147 2005年10月

An Evaluation of Memory Effect to Performance on a Real Reconfigurable Computing System 査読有り

Kosei Shimoo,Kouji Kawano,Akira Yamawaki,Masahiko Iwane

International Symposium on Signals, Circuits & Systems 769 - 772 2005年07月

同期共有変数キャッシュの同期状態を拡張した効果査読有り

山脇彰,岩根雅彦

電子情報通信学会論文誌 J87-D-I ( 12 ) 1136 - 1139 2004年12月

Hardware design in statement level parallel processing 査読有り

Kosei Shimoo,Akira Yamawaki,Masahiko Iwane.

2004 IEEE Asia-Pacific Conference on Circuits and Systems 317 - 320 2004年12月

Easily Customizable Open Soft Processor Cores 査読有り

Akira Yamawaki,Masahiko Iwane

The 2004 1st IEEE Technical Exhibition Based Conference on Robotics and Automation ( TExCRA 2004 ) 79 - 80 2004年11月

A new parallel processing paradigm using a reconfigurable computing system 査読有り

Kosei Shimoo,Akira Yamawaki,Masahiko Iwane

International Symposium on Communications and Information Technologies 2004 (ISCIT2004) 797 - 800 2004年10月

EVALUATION OF MECHANISMS INTRODUCED TO IMPROVE PERFORMANCE OF TSVM CACHE 査読有り

Akira Yamawaki,Masahiko Iwane

IASTED PARALLEL AND DISTRIBUTED COMPUTING AND NETWORKS 502 - 507 2004年02月

Implementation and Evaluation of Novel Cache Architecture for Communicating Shared Variable with Synchronization on a SOC-multiprocessor 査読有り

Akira Yamawaki,Masahiko Iwane

The First Workshop on Embedded Parallel Architectures(WEPA-1) 1 - 6 2004年02月

Organization of Shared Memory with Synchronization on Multiprocessor-on-a-chip 査読有り

Akira Yamawaki,Masahiko Iwane

Proc. 9th Int. Conf. on Parallel and Distributed Systems 83 - 90 2002年12月

同期通信用メモリにおけるカウンタとブロッキングの効果査読有り

山脇彰,岩根雅彦

電子情報通信学会論文誌 J84-D-I ( 9 ) 1457 - 1460 2001年09月

Tagged communication and synchronization memory for multiprocessor-on-a-chip 査読有り

Masahiko Iwane,Akira Yamawaki,Makoto Tanaka

Systems and Computers in Japan 32 ( 4 ) 1 - 13 2001年03月

マルチプロセッサオンチップにおけるCAMを用いた同期通信用メモリ査読有り

岩根雅彦,山脇彰,田中誠

電子情報通信学会論文誌 J83-D-I ( 3 ) 317 - 328 2000年03月

CAMによる同期通信機構を持ったマルチプロセッサの開発

岩根雅彦,山脇彰,松田孝史,東由美

九州工業大学研究報告(工学) ( 71 ) 43 - 50 1999年04月

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