研究者詳細 - 山脇　彰

論文 - 山脇　彰

分割表示181 件中 1 - 20 件目／全件表示 >>

Development of Self-Calibration Hardware Interface for a Peripheral on Super General Purpose SoC 査読有り国際誌

Hibiki Shinozaki, Akira Yamawaki

Proc. of The 13th IIAE International Conference on Industrial Application Engineering 2025 (ICIAE2025)erence on Industrial Application Engineering 2025 (ICIAE2025) ( The Institute of Industrial Applications Engineers ) 262 - 268 2025年03月

Parallel Execution Method Using Multiple High-level Synthesized Hardware for Compositing Sprite and Background 査読有り国際誌

Yuka Otani, Akira Yamawaki

Development of Single-frame Sprite Drawing Hardware Which Can Compose Background by High-level Synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Optimization of Image Usage for Sprite Drawing Hardware Combining High-Level Synthesis and FPGA Internal Memory 査読有り国際誌

Keigo Aoki, Akira Yamawaki

Proceedings of the 8th International Conference on Technology and Social Science 2024 (ICTSS 2024) GS03-1 - GS03-6 2024年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

フィリピンセブ(オンライン) 2024年12月15日 - 2024年12月19日

その他リンク： https://conf.e-jikei.org/ICTSS/2024/proceedings/materials/proc_files/GS/ICTSS2024_G03.pdf

Peripheral Specific Hardware Interface Architecture for Super General Purpose SoC 査読有り国際誌

Hibiki Shinozaki, Akira Yamawaki

Proceedings of the 8th International Conference on Technology and Social Science 2024 (ICTSS 2024) GS02-1 - GS02-6 2024年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

フィリピンセブ(オンライン) 2024年12月15日 - 2024年12月19日

その他リンク： https://conf.e-jikei.org/ICTSS/2024/proceedings/materials/proc_files/GS/ICTSS2024_G02.pdf

Development of single frame sprite drawing hardware in High-level Synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of the 8th International Conference on Technology and Social Science 2024 (ICTSS 2024) GS01-1 - GS01-6 2024年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

フィリピンセブ(オンライン) 2024年12月15日 - 2024年12月19日

その他リンク： https://conf.e-jikei.org/ICTSS/2024/proceedings/materials/proc_files/GS/ICTSS2024_G01.pdf

Hardware Implementation of Device Driver for an SPI Peripheral using High-Level Synthesis 査読有り国際誌

Shinozaki H., Yamawaki A.

International Conference on Intelligent Informatics and BioMedical Sciences, ICIIBMS ( 2024 ) 300 - 303 2024年11月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Japan Okinawa 2024年11月21日 - 2024年11月23日

Combining with the register-transfer-level description, we aim to develop a generic hardware interface architecture for SPI devices using high-level synthesis that automatically converts software into hardware. Device drivers that control SPI devices will not be able to maximize their performance due to software overhead, but customized hardware interface may achieve. This paper evaluates the performance, circuit size, and power efficiency of a hardware device driver for BME280, which is a temperature, humidity, and barometric pressure sensor.

DOI： 10.1109/ICIIBMS62405.2024.10792835

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85219209929&origin=inward

Hardware Implementation of Spherical Diffuse Reflection in Ray-Casting Using High Level-Synthesis 査読有り国際誌

Kurata K., Yamawaki A.

Conference Proceeding - 23rd International Symposium on Communications and Information Technologies, ISCIT 2024 22 - 26 2024年09月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

タイバンコク(オンライン) 2024年09月23日 - 2024年09月25日

Game applications require high graphics, and it is not suitable for mobile devices which is battery-powered because of heavy processing load. Mobile terminals equipped with FPGA, which are dynamically reconfigurable hardware, can take advantage of the high processing performance and low power consumption of FPGA, thus helping to solve these problems. However, this system tends to have high development costs due to the need of circuit data for FPGA's operation. To avoid this problem, we make use of High-Level Synthesis, HLS. HLS is a tool that automatically generate hardware from software program, but it is not panacea. If there is no consideration of hardware structure, it sometimes generates inferior hardware. We are therefore developing a HLS-oriented program particularly focusing on ray-casting, which is utilized in the creation of high-graphic game applications, and have implemented spherical diffuse reflection which is one of the processes included in ray-casting. In this paper, we implemented fixed-point conversion to make numerous vector operations used in ray-casting more hardware-friendly. The experiment evaluates that the circuit size, execution time, and power efficiency. The results show that the fixed-point method contributes significantly to the reduction of the circuit size and the created hardware performs satisfactorily against the software.

DOI： 10.1109/ISCIT63075.2024.10793519

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85216580425&origin=inward

Development of sprite drawing hardware with two parallelisms using semi-parallel method 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 242 - 247 2024年09月

Development of Triangle Drawing Hardware by High-level Synthesis 査読有り国際誌

Kanta Shin, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 272 - 275 2024年09月

Comparison and evaluation of image sharpening hardware developed using high-level synthesis, 査読有り国際誌

Ryota Oka, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 267 - 271 2024年09月

Hardware Implementation of Spherical Specular Reflection in Ray-casting Using High-Level Synthesis 査読有り国際誌

Kazuki Kurata, Akira Yamawaki

Proc. of 11th International Conference on Intelligent Systems and Image Processing 2024 (ICISIP 2024) 260 - 266 2024年09月

Performance variation caused by sprite drawing pattern for high-level synthesized sprite drawing hardware 査読有り国際誌

Otani Y., Yamawaki A.

ACM International Conference Proceeding Series 1 - 5 2024年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We are developing a sprite drawing software suitable for automatic hardware generation by high-level synthesis. Sprite drawing stores the sprite image into a frame memory pointed to by the origin coordinates. Frame memory is typically realized with high-capacity DRAM such as DDR SDRAM. The DDR SDRAM is prone to stalls when the memory accesses have randomness. The performance of sprite drawing hardware may depend on the drawing pattern on the frame memory in contrast with a CPU hiding the frame memory by a cache memory. This paper investigates how hardware and software performance varies with varying sprite drawing patterns. The results show that hardware achieves better real-time performance than software execution, although the performance variation of hardware due to drawing conditions is slightly larger than that of software execution.

DOI： 10.1145/3686625.3686626

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85203795732&origin=inward

Hardware Implementation of Calibration Data Loading in Device Driver for an SPI Peripheral 査読有り国際誌

Shinozaki H., Yamawaki A.

ACM International Conference Proceeding Series 19 - 23 2024年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As the IoT progresses, various SoCs are being developed. If a SoC is in high demand, the development cost per chip is small, but if the demand is localized, the development cost is large, resulting in more expensive products. To solve this problem, we aim to develop a general-purpose SoC with hardware interfaces for all peripheral devices. Since it is difficult to develop such a SoC due to hardware constraints, the dynamic reconfiguration of FPGA is used to deploy only what is necessary for processing in the reconfiguration unit. In addition, we aim to develop a general-purpose architecture that facilitates the design and development of dedicated hardware interfaces for each peripheral device. This architecture is to achieve a general-purpose SoC by seeking the cooperation of engineers around the world. Toward the development of this architecture, we will first focus on SPI devices. In developing hardware device drivers for SPI devices, RTL description is used for the parts that describe clock-cycle-based operations, and high-level synthesis is used for the parts that describe procedure-based operations. In this study, the BME280, a temperature, humidity, and barometric pressure sensor for SPI devices, is used to convert the device driver functionality to hardware for efficient use. This paper describes the hardware implementation of the part that reads multiple calibration data to correct the sensor data, and evaluates the performance, circuit size, and power efficiency through demonstration experiments using an actual device.

DOI： 10.1145/3686625.3686629

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85203790525&origin=inward

Development of Sprite Drawing Hardware Combining High-Level Synthesis and FPGA Internal Memory 査読有り国際誌

Aoki K., Yamawaki A.

ACM International Conference Proceeding Series 37 - 41 2024年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Mobile devices are required to have higher performance and more functionality while conserving more power. To realize high-performance and low-power game applications by dynamic hardware reconfiguration on a FPGA equipped with mobile devices, we are developing a hardware-oriented game library so that high-level synthesis can generate efficient hardware automatically. Usually, large images and other data used in games are stored in an external memory instead of hardware internally but loading them from the external memory may be time-consuming. Therefore, this paper proposes a hardware organization to utilize the internal memory in a FPGA to reduce the external memory accesses, and then develops a sprite drawing hardware combines software optimized for high-level synthesis and the internal memory in a FPGA. Through demonstration experiments using an actual device, this paper evaluates the execution time, circuit size, and power efficiency.

DOI： 10.1145/3686625.3686632

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85203803438&origin=inward

A Real-time Non-Photorealistic Rendering System using a High-Level Synthesized Hardware of Pencil Drawing Style Image Conversion 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 158 - 165 2024年03月

Development of Wired Zero-powered Sensor Network Group in Wired-wireless Hierarchical Sensor Network 査読有り国際誌

Akira Yamawaki, Seiichi Serikawa

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 182 - 187 2024年03月

Multi-staging Effect of Averaging Filter on High-Level Synthesized Pencil Drawing Style Image Conversion Hardware 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 174 - 181 2024年03月

Effect of Median Filter on High-level Synthesized Pencil Drawing Style Image Conversion Hardware 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 12th IIAE International Conference on Industrial Application Engineering 2024 (ICIAE2024) 166 - 173 2024年03月

Light-weight color image conversion like pencil drawing for high-level synthesized hardware 査読有り国際誌

Tani H., Yamawaki A.

Artificial Life and Robotics 29 ( 1 ) 29 - 36 2024年02月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

We are developing pencil-drawing-style image conversion software suitable for high-level synthesis, HLS, technology that automatically converts software into hardware. The pencil-drawing-style image conversion consists of the former and latter processes. The former generates the images expressing edge strengths and their directions. The latter process convolves the line segment corresponding to the edge strength with its direction. As hardware-oriented software description, the medium data across the former and latter processes are optimized. In addition, the former and latter processes are overlapped between the FIFO buffer passing the medium data. The obtained image is still a gray-scaled image. To make it support the color image, this paper inserts a process compositing the original color image with the grayed pencil-drawing-style image to not intervene in the pipelined data path behavior. As a result, an HLS tool used is expected to generate a hardware module with the ideal pipelined data path by one output data/one clock. The experimental results show that the colorization hardware had no significant performance degradation issues for circuit size, run time, or power efficiency compared to the pencil drawing hardware with grayscale. Compared with the software execution, our hardware supporting color image can achieve 4.2 times the performance improvement and 130 times power efficiency.

DOI： 10.1007/s10015-023-00927-2

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85180442262&origin=inward

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