研究者詳細 - 山脇　彰

論文 - 山脇　彰

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An Evaluation of Burst Transfer Inferred by a High-level Synthesis Tool 査読有り

Yamagata Y., Yamawaki A.

IEIE Transactions on Smart Processing and Computing 8 ( 2 ) 143 - 149 2019年01月

担当区分：責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

© 2019 Institute of Electronics and Information Engineers. All rights reserved. High-level synthesis (HLS) is technology that automatically converts software to digital hardware. HLS has gained attention as a promising technology that can reduce the burden of hardware development. However, if a software program converted by HLS does not consider organization of the hardware, the current HLS technology cannot convert software to proper digital hardware. One of the characteristics of the hardware to be considered is burst transfer to memory access. Burst transfer attempts to speed up memory access by packing continuous data into a single address. This paper discusses a rectangle-drawing case study that demonstrates how to describe a C program so an HLS tool can infer burst transfer with an arbitrary burst length. Moreover, we consider the necessity to suppress optimization performed by the HLS tool to prevent increasing the amount of digital hardware when we implement the arbitrary burst length. Experiments clarify how performance and the hardware scale change based on the difference in the burst length and suppression of optimization.

DOI： 10.5573/IEIESPC.2019.8.2.143

Scopus

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Proposal of an ultrasonic sensor array with flexible and scalable organization 査読有り

Yuichi Morita, Sota Kono, Akira Yamawaki

Artificial Life and Robotics 1 - 6 2018年12月

An Evaluation of Burst Transfer Inferred by a High-level Synthesis Tool 査読有り

Yuki Yamagata,Akira Yamawaki

Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference 2120 - 2123 2018年10月

Describing Methods for High-level Synthesis of Histogram Generation and Their Evaluation 査読有り

Moena Yamasaki, Akira Yamawaki

Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference 2116 - 2119 2018年10月

Development of Pre/Post-Integrated Image Processing Hardware by High Level Synthesis for Camera Sensor Node 査読有り

Sota Miura, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 244 - 248 2018年09月

Development of Memory Mapped Register and Bus Switch Circuit for Hardware Virtualization in GEDY 査読有り

Sota Kono, Satoshi Yonemitsu, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 137 - 141 2018年09月

Investigation of Measuring Multiple Biological Signals by Analog Circuit Dynamic Reconfiguration 査読有り

Tetsuya Suematsu, Yuta Suzuki, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 142 - 145 2018年09月

Design of Daisy-chain Connection for Flexible and Scalable Ultrasonic Sensor Array 査読有り

Yuichi Morita, Akira Yamawaki

Proceedings of the 6th IIAE International Conference on Intelligent Systems and Image Processing 2018 132 - 136 2018年09月

An Investigation to Realize Zero Standby Strain Sensor Node 査読有り

Yuta Suzuki, Yuichi Morita, Akira Yamawaki

Proceedings of the 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2018 70 - 73 2018年07月

Development of Image Compression Hardware by High level Synthesis for Wireless Camera Sensor Node 査読有り

Sota Miura, Akira Yamawaki

Proceedings of the 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2018 290 - 293 2018年07月

A Command List Based Automatic Controlling Method of UAV for Infrastructure Monitoring System with Zero-standby Sensor Node 査読有り

Yuta Suzuki, Shogo Yoshikawa, Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 215 - 218 2018年03月

A Consideration to Develop a High-level Synthesizable Software Game Library 査読有り

Yuki Yamagata,Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 202 - 205 2018年03月

Effect of Redundant Function Execution to Reduce Memory Access on High-level Synthesis 査読有り

Moena Yamasaki, Satoshi Yonemitsu, Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 206 - 209 2018年03月

Development of Image Processing Hardware by High-level Synthesis for High Performance and Low-power Camera Sensor Node on Wireless Sensor Network 査読有り

Sota Miura, Ayumi Mise, Akira Yamawaki

Proceedings of the 6 th IIAE International Conference on Industrial Application Engineering 2018 210 - 214 2018年03月

A describing method of an image processing software in C for a high-level synthesis considering a function chaining 査読有り国際誌

Yamawaki A., Serikawa S.

IEICE Transactions on Information and Systems ( 一般社団法人電子情報通信学会 ) E101D ( 2 ) 324 - 334 2018年02月

担当区分：筆頭著者,　最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

© Copyright 2018 The Institute of Electronics, Information and Communication Engineers. This paper shows a describing method of an image processing software in C for high-level synthesis (HLS) technology considering function chaining to realize an efficient hardware. A sophisticated image processing would be built on the sequence of several primitives represented as sub-functions like the gray scaling, filtering, binarization, thinning, and so on. Conventionally, generic describing methods for each subfunction so that HLS technology can generate an efficient hardware module have been shown. However, few studies have focused on a systematic describing method of the single top function consisting of the sub-functions chained. According to the proposed method, any number of sub-functions can be chained, maintaining the pipeline structure. Thus, the image processing can achieve the near ideal performance of 1 pixel per clock even when the processing chain is long. In addition, implicitly, the deadlock due to the mismatch of the number of pushes and pops on the FIFO connecting the functions is eliminated and the interpolation of the border pixels is done. The case study on a canny edge detection including the chain of some sub-functions demonstrates that our proposal can easily realize the expected hardware mentioned above. The experimental results on ZYNQ FPGA show that our proposal can be converted to the pipelined hardware with moderate size and achieve the performance gain of more than 70 times compared to the software execution. Moreover, the reconstructed C software program following our proposed method shows the small performance degradation of 8% compared with the pure C software through a comparative evaluation preformed on the Cortex A9 embedded processor in ZYNQ FPGA. This fact indicates that a unified image processing library using HLS software which can be executed on CPU or hardware module for HW/SW co-design can be established by using our proposed describing method.

DOI： 10.1587/transinf.2017RCP0001

Scopus

CiNii Article

CiNii Research

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Proposal of an Ultrasonic Sensor Array with Flexible and Scalable Organization 査読有り

Yuichi Morita, Sota Kono, Akira Yamawaki

Proceedings of The Twenty-Third International Symposium on Artificial Life and Robotics 2018 381 - 384 2018年01月

A Unified Detection Method of Indoor Three Events by Dynamic Reconfiguration of Analog Circuit 査読有り

Tetsuya Suematsu, Yasunobu Takaichi, Akira Yamawaki

Proceedings of the 5th International Conference on Intelligent Systems and Image Processing 2017 381 - 386 2017年09月

Door Monitoring System Using Sensor Node with Zero Standby Power 査読有り

Akira Yamawaki, Seiichi Serikawa

Transactions on Engineering Technologies: International MultiConference of Engineers and Computer Scientists 2016 73 - 87 2017年05月

Development of Analog to Digital Interface for Scalable Ultrasonic Sensor Array 査読有り

Yuichi Morita, Sota Kono, Akira Yamawaki

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017 159 - 164 2017年03月

Development of Wireless Monitoring Device for Window Security using Light Sensor 査読有り

Ryuji Funemizu, Yasunobu Takaichi, Akira Yamawaki

Proceedings of the 5th IIAE International Conference on Industrial Application Engineering 2017 340 - 345 2017年03月

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