研究者詳細 - 山脇　彰

論文 - 山脇　彰

分割表示181 件中 21 - 40 件目／全件表示 >>

An investigation of line and frame based descriptions on designing sprite drawing hardware in high-level synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of 2023 11th International Japan-Africa Conference on Electronics, Communications and Computations (JAC-ECC) ( IEEE ) 176 - 179 2023年12月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

エジプト(オンライン) Alexandria 2023年12月18日 - 2023年12月20日

We are developing a sprite drawing process in a game software library optimized to make high-level synthesis, HLS, generate an efficient hardware. There are two description methods to realize an image processing consisting of several sub-processes. The one is line-based method processing every line and the another is frame-based method processing every image among them. Which method is better must be investigated when using HLS to develop a sprite drawing hardware. The experimental result shows that the frame-based method is better about performance because it reduces an overhead due to switching every line. However, the line-based method is more suitable from the viewpoints about the amount of hardware and power consumption.

DOI： 10.1109/JAC-ECC61002.2023.10479603

Scopus

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Process chaining without image and performance loss for pencil drawing style image conversion in High-Level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of the 10th IIAE International Conference on Intelligent Systems and Image Processing 2023 (ICISIP 2023) 148 - 153 2023年09月

An investigation of performance and power efficiency for parallax background scrolling hardware written in high-level synthesis 査読有り国際誌

Kilryong Lee, Akira Yamawaki

Journal of Physics: Conference Series 2559 ( 2559 ) 012008 2023年08月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

韓国済州島 2023年02月18日 - 2023年02月20日

We are developing a game programming software library so that high-level synthesis, HLS, can automatically generate high-performance and low-power hardware modules. A mobile terminal with a user-available reconfigurable device like Field programmable gate array, FPGA, we have proposed will efficiently perform game application built in HLS-oriented game library instead of power-hungry software execution. The dynamic hardware reconfiguration on a single FPGA can execute many kinds of game applications. Our previous research has developed software description methods for two-background scrolling in HLS-oriented game programming library by using two methods. They are (1) Full-parallel equips plural physical ports loading background images individually making HLS hardware execute the entire process parallelly increasing the amount of hardware: (2) Semi-parallel shares the single port loading background images serially, suppressing the hardware growth while achieving moderate performance by overlapping operation phases. We investigate two methods about execution time and power efficiency on the parallax scrolling with 2 to 4 backgrounds. The execution times of full-parallel hardware at 100MHz clock frequency are constantly about 9.65 [ms] while those of semi-parallel are 28, 38 and 47 [ms]. The PC at 3.2 GHz shows 78, 98 and 105 [ms] respectively as well. The power efficiencies about the full-parallel estimated considering hardware enlargement are 167, 208 and 112 times compared to the software execution in the PC, while those of semi-parallel are 94, 88 and 75 times. This fact indicates that the full-parallel is better strategy for parallax background scrolling in this case although more hardware resource are invested.

DOI： 10.1088/1742-6596/2559/1/012008

Scopus

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Wired-Wireless Hierarchical Sensor Network using Zero power Sensor Node 査読有り国際誌

Akira Yamawaki, Makoto Miyauchi, Seiichi Serikawa

Journal of Physics: Conference Series 2559 ( 2559 ) 012004 2023年08月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

韓国済州島 2023年02月18日 - 2023年02月20日

The wireless sensor network, WSN, is a promising technology to make our social life better. However, the maintenance of the battery attached to each sensor node avoids WSN widely be used. The zero standby-power sensor node (ZSSN) extends battery life by eliminating standby power, but they impose high cost and maintenance burdens because each node has its own battery and wireless module. This paper proposes a wired-wireless hierarchical sensor network consisting of a small network group of ZPSNs (Zero power sensor node) with large capacitor as power supply that are wired together, and the parent node has a wireless module and an energy harvester. The proposed WSN can suppress the number of energy harvesters and wireless modules to that of groups. There are no batteries by replaced to the capacitors. That is, our WSN can reduce the maintenance and cost caused by which there is no battery, and each only parent node has wireless module and energy harvester. The experimental result shows that the standby ZPSN can keep enough voltage 48 days on the large capacitor to operate in active mode correctly.

DOI： 10.1088/1742-6596/2559/1/012004

Scopus

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Process Integration to Realize Full Pipelined Pencil Drawing Style Image Conversion Hardware in High-Level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of 5th International Conference on Computer Communication and the Internet 2023 (ICCCI 2023) 251 - 255 2023年08月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本藤沢 2023年06月23日 - 2023年06月26日

We are developing pencil drawing style image conversion software suitable for High-Level Synthesis (HLS) technology that automatically converts software into hardware. As an initial step, we have developed software for HLS by dividing the entire process into former and latter sub-processes to reduce the size of the target, and then developed software for each of these sub-processes. Former and latter processes have been optimized for HLS, and the HLS hardware modules were able to achieve an ideal performance with well-pipelined data path. However, they are fired sequentially. So, the total performance has a rest of room to improve the performance by overlapping former and latter processes. This paper develops the HLS oriented software that the HLS can generate hardware module integrating former and later processes. This integration can achieve a totally pipelined data path across all processes. As a result, it is expected that the performance becomes ideal one without sequential executing part. The experimental result confirms the effectiveness of the proposed method by comparing the processing time, circuit size, and power efficiency with those of previous hardware.

DOI： 10.1109/ICCCI59363.2023.10210175

Scopus

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Development of High-performance Sprite Drawing Process in a Game Library for High-Level Synthesis 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of 5th International Conference on Computer Communication and the Internet 2023 (ICCCI 2023) 223 - 228 2023年08月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本藤沢 2023年06月23日 - 2023年06月26日

A mobile terminal dynamically reconfiguring an optimal hardware for each application can achieve higher performance and lower power consumption. To develop game applications running on such mobile terminal requires a high-level synthesizable game library whose functions can be automatically converted to hardware modules. Each function in a high-level synthesizable library, must be written considering characteristic of hardware to be converted to an efficient hardware. This paper focuses on the drawing of 2D sprite characters which is a common function among many conventional software game libraries. Sprite movement is realized by drawing and compositing with a background image. To achieve this, we develop a software description suitable for high-level synthesis while taking into hardware characteristics. The characteristics considered are the burst transfer of memory access and the parallelization of the former and later processes. Experimental results show that our high-level synthesis hardware is 1.6 times faster and sixteen times more power efficient than software execution.

DOI： 10.1109/ICCCI59363.2023.10210177

Scopus

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Hardware Development of Sphere Intersection in Ray-casting Using High-Level-Synthesis 査読有り国際誌

Kazuki Kurata, Akira Yamawaki

Proceedings of The 7th Imaging, Signal Processing and Communications 2023 (ICISPC2023) 86 - 90 2023年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本熊本 2023年07月21日 - 2023年07月23日

Game applications that require high graphics performance have a large processing load, which greatly affects the running time of battery-driven mobile terminals. Mobile terminals that support dynamic partial reconfiguration of hardware can perform high-performance and low-power graphics processing through power-efficient hardware execution, rather than software. This paper develops hardware for the intersection determination process in ray-casting, which is utilized in the creation of high-graphic game applications. In the development, the HLS, which is an automated software-to-hardware conversion tool is used. We developed the software of intersection determination process so that the HLS can generate small-resource-usage, high-performance, and power-efficient hardware. Intersection determination of ray-casting is carried out by vector and square root calculation. Usually, these calculations are executed in floating-point operation. However, this operation method tends to increase the size of the circuit because it requires a great deal of resources when implemented hardware. It is not desirable due to a huge circuit size means high power consumption. Therefore, this paper shows an optimal method in vector and square root calculations using fixed point, while considering its accuracy. Also, through demonstrations on actual machines, we evaluate its usefulness in terms of performance, circuit size and power efficiency.

DOI： 10.1109/ICISPC59567.2023.00024

Scopus

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Data Path parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware 査読有り国際誌

Yuka Otani, Akira Yamawaki

Proceedings of The 7th Imaging, Signal Processing and Communications 2023 (ICISPC2023) 97 - 101 2023年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本熊本 2023年07月21日 - 2023年07月23日

A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve higher performance and lower power consumption compared with a conventional one. We are developing a software game library so that the high-level synthesis, HLS, can automatically generate an efficient hardware module in such mobile terminals. The HLS library must be built with deep consideration of hardware organization. Otherwise, the HLS converts software into a large and slow hardware module. This paper focuses on the drawing of 2D sprite characters. Character movement is achieved by repeatedly compositing the background image and sprite image during drawing. The data paths are parallelized on the sprite drawing process so that the HLS can produce better hardware. The experiments confirm the effectiveness of the proposed method on the actual machine and simulation.

DOI： 10.1109/ICISPC59567.2023.00026

Scopus

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Memory access optimization for former process of pencil drawing style image conversion in High-level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Parallel and Distributed Computing, Applications and Technologies. PDCAT 2022. Lecture Notes in Computer Science ( Springer, Cham ) 13798 LNCS ( 13798 ) 57 - 68 2023年04月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

日本仙台 2022年12月07日 - 2022年12月09日

To effectively use high-level synthesis, which automatically converts software to hardware, it is necessary to create software programs considering hardware configuration. This paper attempts to automatically generate high-performance and power-saving hardware from software for pencil drawing style image conversion. The former process of the pencil drawing style image conversion reads the input image for each window and generates a lot of middle images. Automatic generation of better hardware requires an optimization of those memory accesses. The proposed method optimizing memory accesses achieves a performance improvement of about 65 times over the base hardware. As a result, the proposed method improved performance by about 1.4 times and 50 times compared to the software execution on a PC and an embedded CPU respectively.

DOI： 10.1007/978-3-031-29927-8_5

Scopus

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High-level Synthesized Hardware of Fundamental Morphological Operation and its Application 査読有り国際誌

Daiki Okamoto, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 276 - 281 2023年03月

Investigation Toward Realization of High-level Synthesizable Sprite Moving Functions 査読有り国際誌

Kyota Matsuda, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 269 - 275 2023年03月

Development of Relationship Interface between High-level Synthesis and Web Browser-based Hardware Verification System with Virtual Peripheral 査読有り国際誌

Tomomi Yoshizuka, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 320 - 324 2023年03月

Introduction Hardware Switching Functionality to Web browser-based FPGA Hardware Verification System 査読有り国際誌

Tomomi Yoshizuka, Akira Yamawaki

Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023 ( 産業応用工学会 ) 315 - 319 2023年03月

An investigation of software describing methods to design dual background scrolling hardware in high-level synthesis 査読有り国際誌

Lee K., Yamawaki A.

Artificial Life and Robotics 28 ( 3 ) 547 - 552 2023年03月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

We are developing a game programing library which can be converted to hardware modules by high-level synthesis, HLS technology to realize high-performance and low-power mobile terminals executing game applications. High-level synthesis is a technology that converts software into hardware automatically. The game software is executed by high-speed and low-power hardware on the reconfigurable devices in the mobile terminals instead of power-hungry software execution. To make high-level synthesis tool generate desirable hardware module, we must describe software program well considering the hardware organization. In this paper, we developed two software description methods for dual background scrolling processing as one of functions in high-level synthesis-oriented game software library. We also evaluate the execution time, resource usage, and power consumption of hardware modules that high-level synthesis generated through the experiments and investigate which hardware module has better performance.

DOI： 10.1007/s10015-023-00866-y

Scopus

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Hardware Development of Virtual Background Scrolling Independent on Physical Resolution in High-level Synthesis 査読有り国際誌

Kilryong Lee, Akira Yamawaki

Proceedings of The 28th International Symposium on Artificial Life and Robotics 2023 (AROB 2023) 725 - 728 2023年01月

Development of image uploading function in Web browser-based FPGA Hardware Verification System 査読有り国際誌

Tomomi Yoshizuka, Akira Yamawaki

Proceedings of The 28th International Symposium on Artificial Life and Robotics 2023 (AROB 2023) 736 - 739 2023年01月

Effect of Line Segment Size on Pencil Drawing-like Image Conversion Hardware Developed by High-level Synthesis 査読有り国際誌

Honoka Tani, Akira Yamawaki

Proceedings of The 28th International Symposium on Artificial Life and Robotics 2023 (AROB 2023) 740 - 743 2023年01月

Development of High-level Synthesis Oriented Background Scroll Function Considering Hierarchy of Game Display Frame 査読有り国際誌

Lee K., Yamawaki A.

Proceedings of IEEE Region 10 Annual International Conference 2022 (TENCON2022) 2022-November 2022年11月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

2022年11月01日 - 2022年11月04日

We are developing background scrolling function in High-Level Synthesizable game programing library to realize high-performance and power-saving mobile terminals executing game applications by using hardware execution in Field Programmable Gate Array, FPGA. High-Level Synthesis converts software into hardware automatically and it can reduce heavy burden of hardware development. In game application, display resolution has not to be always same as game screen size. The hierarchy layering game screens with varying sizes on the display frame may provide more engaging effect to the game application. In such case like the size of game screen differs from the display resolution, the appropriate integration of the updated game screen into the display frame is required. Performing updating and embedding the game screen individually may lead to degrade the performance of hardware because useless memory copies become bottleneck. To solve this problem for the background scrolling on the game screen, we extend our function to fit the background scrolled to physical display resolution simultaneously. That is, this paper proposes a high-level synthesizable software description method for background scrolling considering hierarchy of display frame and evaluates this effect.

DOI： 10.1109/TENCON55691.2022.9977798

Scopus

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Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction 査読有り国際誌

Shinyamada K., Yamawaki A.

Artificial Life and Robotics 27 ( 3 ) 541 - 546 2022年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was N= 4 , which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing.

DOI： 10.1007/s10015-022-00777-4

Scopus

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Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration 査読有り国際誌

Shojima A., Yamawaki A.

Artificial Life and Robotics 27 ( 3 ) 554 - 560 2022年07月

担当区分：最終著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

The verification of image processing hardware using FPGAs requires various peripherals. Although commercially available FPGA boards also include peripherals, it is necessary to design and implement interface circuits to use them. Furthermore, since each board has different peripherals, new interfaces have to be designed each time. Also, these interface circuits are not generated by HLS. Therefore, we are developing a hardware verification environment that is independent of the peripherals of FPGA boards. The verification environment we proposed last time consists of a general-purpose FPGA board, a PC, and server/client programs running on the PC and on the CPU of the FPGA board. By virtualizing the peripherals to be installed in the product on the PC, verification can be performed regardless of the peripherals on the FPGA board. TCP/IP communication also makes it possible to verify huge images. However, in this verification environment, each verification has to be compiled on the FPGA implementation tool. Therefore, in this paper, we aim to create a verification environment in which hardware can be replaced dynamically during verification by implementing DPR.

DOI： 10.1007/s10015-022-00772-9

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85133573194&origin=inward

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