論文 - 中村 和之
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A 0.10um CMOS, 1.2V, 2GHz Phase-Locked Loop with Gain Compensation VCO 査読有り
K. Minami,M. Fukaishi,M. Mizuno,H. Onishi,K. Noda,K. Imai,T. Horiuchi,H. Yamaguchi,T. Sato,K. Nakamura,M.Yamashina
IEEE Custom Integrated Circuits Conf. (CICC) 213 - 216 2001年05月
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A 2Gb/s 21CH Low Latency Transceiver Circuit for Inter-Processor Communication 査読有り
T.Tanahashi,K.Kurisu,H.Yamaguchi,S.Tomari,T.Matsuzaka,K.Nakamura,M.Fukaishi,S.Naramoto,T.Sato
2001 ISSCC Digest of technical Papers 60 - 61 2001年02月
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A 2.5GHz 4-phase Clock Generator with Scalable and No Feedback Loop Architecture 査読有り
K.Yamaguchi,M.Fukaishi,T.Sakamoto,A.Akiyama,K.Nakamura
2001 ISSCC Digest of technical Papers, 398 - 399 2001年02月
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A 20-Gb/s CMOS Multichannel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Displays 査読有り
M.Fukaishi,K.Nakamura,H.Heiuchi,Y.Hirota,Y.Nakazawa,H.Ikeno,H.Hayama,M.Yotsuyanagi
IEEE Journal of Solid-State Circuits 35 1611 - 1618 2000年11月
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A CMOS 50% duty cycle repeater using complementary phase blending 査読有り
K.Nakamura,M.Fukaishi,M.Yotsuyanagi et al
2000 Symposium on VLSI Cricuits 48 - 49 2000年06月
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A 20-Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Display 査読有り
M.Fukaishi,K.Nakamura,M.Yotsuyanagi,et.al.
2000 ISSCC Digest of technical Papers 260 - 261 2000年02月
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Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology 査読有り
M,Kurisu,M.Fukaishi,H.Asazawa,M.Nishikawa,K.Nakamura,M.Yotsuyanagi
IEICE Transactions on Electronics E82-C ( 3 ) 428 - 437 1999年03月
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A 4.25-Gb/s CMOS fiber channel transceiver with asynchronoustree-type demultiplexer and frequency conversion architecture 査読有り
M.Fukaishi,K.Nakamura,M.Sato,Y.Tsutsui,S.Kishi,M.Yotsuyanagi
IEEE Journal of Solid-State Circuits 33 2139 - 2147 1998年12月
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A 6Gbps 0.18um CMOS Phase Detecting DEMUX Module Using Half-Frequency Clock 査読有り
K.Nakamura,M.Fukaishi,M.Yotsuyanagi et. al.
1998 Symposium on VLSI Cricuits 196 - 197 1998年06月
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A 4.25Gbps CMOS Fiber Channel Transceiver with Asynchronous Binary Tree-type Demultiplexer and Frequency Conversion Architecture 査読有り
M.Fukaishi,K.Nakamura,M.Yotsuyanagi et.,al.
1998 ISSCC Digest of technical Papers 306 - 307 1998年02月
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A 500MHz 4Mb CMOS Pipe-line Burst Cache SRAM with Point-to-Point Noise Reduction Coding I/O 査読有り
K.Nakamura,K.Takeda,H.Toyoshima,K.node,H.Ohkubo,T.Uchida,T.Shimizu,T.Itani,K.Tokashiki,K.Kishimoto
IEEE Journal of Solid-State Circuits 32 1758 - 1765 1997年11月
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A 500MHz 4Mb CMOS Pipe-line Burst Cache SRAM with Point-to-Point Noise Reduction Coding I/O 査読有り
K.Nakamura,K.Takeda,H.Toyoshima,K.node,H.Ohkubo,T.Uchida,T.Shimizu,T.Itani,K.Tokashiki ,K.Kishimoto
1997 ISSCC Digest of Technical Papers 406 - 407 1997年02月
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A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM 査読有り
H.Toyoshima,S.Kuhara,K.Takeda,K.Nakamura,H.Okamura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki
IEEE Journal of Solid-State Circuits 31 1610 - 1617 1996年11月
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A 50% Noise Reduction Interface Using Low-weight Coding 査読有り
K.Nakamura,Mark. A. Horowitz
1996 Symposium on VLSI Cricuits 144 - 145 1996年06月
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A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM 査読有り
S.Kuhara,H.Toyoshima,K.Takeda,K.Nakamura,H.Okamura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki
1996 ISSCC Digest of technical Papers 1996年02月
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PLL Timing Design Techniques for Large-scale, High-speed, Low-cost SRAMs 査読有り
K.Nakamura,S.Kuhara,T.Kimura,M.Takada,H.Suzuki,H.Yoshida,T.Yamazaki
Transactions on Electronics E78-C ( 7 ) 805 - 811 1995年07月
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Design of 1.28-GB/s Bandwidth 2-Mb SRAM for Integrated Memory Array Processor Application 査読有り
T.Kimura,K.Nakamura,Y.Aimoto,T.Manabe,N.Yamashita,Y.Fujita,S.Okazaki,M.Yamashina
IEEE Journal of Solid-State Circuits 30 637 - 643 1995年06月
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High Speed Sub-micron Bi-CMOS Memory 査読有り
M.Takada,K.Nakamura,T.Yamazaki
IEEE Transactions on Electron Devices 42 ( 3 ) 497 - 505 1995年03月
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A 3.84GIPS Integrated Memory Array Processor 査読有り
Y.Fujita,N.Yamashita,T.Kimura,K.Nakamura,S.Okazaki
IEICE transactions on Systems and Computers J78-D-I ( 2 ) 82 - 90 1995年02月
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An SIMD Type Integrated Memory Array Processor (IMAP) 査読有り
Y.Fujita,N.Yamashita,T.Kimura,K.Nakamura,S.Okazaki
International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) 1994年12月