Papers - MORIE Takashi
-
An Image Recognition Algorithm Using Relationships between Segmented Coarse Regions Reviewed
T. Nakano,T. Morie
Brain-Inspired IT II, International Congress Series 1291 241 - 244 2006.04
-
An Analog CMOS Circuit for Spiking Neuron Models Reviewed
H. Tanaka,T. Morie,K. Aihara
Brain-Inspired IT II, International Congress Series 1291 217 - 220 2006.04
-
Subjective Contour Generation Using a Pixel-parallel Anisotropic Diffusion Algorithm Reviewed
Y. Kim,T. Morie
Brain-Inspired IT II, International Congress Series 1291 241 - 244 2006.04
-
Face Position Detection by a Convolutional Neural Network Using an Image Filtering Processor VLSI Reviewed
K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata
Brain-Inspired IT II, International Congress Series 1291 253 - 256 2006.04
-
Digital VLSI Architecture for Image Matching Based on 2D Cross-correlation Reviewed
M. Mitarai,K. Korekado,T. Morie
RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 277 - 280 2006.03
-
An FPGA-based Real-time Moving-object Detection System Based on Neuronal Propagation in the Hippocampus Reviewed
H. Liang,T. Morie,H. Nakayama,K. Nakada,H. Hayashi
RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 509 - 512 2006.03
-
Design of an 2D Image Matching Processor LSI Based on Merged Analog/Digital Architecture Reviewed
M. Sakai,T. Morie,M. Mitarai,K. Korekado
RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 81 - 84 2006.03
-
Design of a CMOS Pixel Circuit for Coarse Region Segmentation/Extraction Based on Merged Analog/Digital Architecture Reviewed
N. Kato,T. Morie
RISP 2007 International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07) 89 - 92 2006.03
-
A Pixel Circuit Implementing an Anisotropic Diffusion Algorithm for Subjective Contour Generation Using Merged Analog-Digital circuit Approach Reviewed
Y. Kim,T. Morie
2006 RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'06) 2006.03
-
FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation Reviewed
T. Nakano,T. Morie,H. Ishizu,H. Ando,A. Iwata
Intelligent Automation and Soft Computing 12 ( 3 ) 307 - 316 2006.03
-
顔/物体認識のためのElastic Graph MatchingのFPGA実装とその性能評価
中野鉄平,森江隆
電子情報通信学会 ニューロコンピューティング研究会 25 - 30 2005.11
-
Associative Memory Operation in a Hopfield-type Spiking Neural Network with Modulation of Resting Membrane Potential Reviewed
H. Tanaka,T. Morie,K. Aihara
2005 Int. Symp. on Nonlinear Theory and its Applications (NOLTA2005) 313 - 316 2005.10
-
An Image Recognition Algorithm Using Coarse Region Segmentation and Relationship between the Regions Reviewed
T. Nakano,T. Morie
Abstracts of Brain-Inspired Information Technology (BrainIT2005) 81 - 81 2005.10
-
Subjective Contour Generation Using a Pixel-parallel Anisotropic Diffusion Algorithm Reviewed
Y. Kim,T. Morie
Abstracts of Brain-Inspired Information Technology (BrainIT2005) 94 - 94 2005.10
-
An Analog CMOS Circuit for Spiking Neuron Models Reviewed
H. Tanaka,T. Morie,K. Aihara
Abstracts of Brain-Inspired Information Technology (BrainIT2005) 2005.10
-
Face Position Detection Using an Image Filtering Processor VLSI Reviewed
K. Korekado,T. Morie,O. Nomura,T. Nakano,M. Matsugu,A. Iwata
Abstracts of Brain-Inspired Information Technology (BrainIT2005) 86 - 86 2005.10
-
A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Reviewed
D. Atuti,T. Morie,K. Aihara
Abstracts of Brain-Inspired Information Technology (BrainIT2005) 73 - 73 2005.10
-
A Convolutional Neural Network VLSI Architecture Using Sorting Algorithm Reviewed
O. Nomura,T. Morie,K. Korekado,M. Matsugu,A. Iwata
Int. Conf. on Advances in Natural Computation (ICNC'05) 1006 - 1014 2005.08
-
A Gabor Filtering VLSI Processor Mimicking a Primary Visual Cortex Function Reviewed
T. Morie,K. Nakamura,K. Korekado
Post-IJCNN2005 Workshop, Biologically-Inspired Models and Hardware for Human-like Intelligent Functions (BIMH2005) 2005.08
-
A Digital LSI Architecture of Elastic Graph Matching and Its FPGA Implementation Reviewed
T. Nakano,T. Morie
Proc. Int. Joint Conference on Neural Networks (IJCNN05) 689 - 694 2005.07