Papers - MORIE Takashi
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減衰シナプスを導入したスパイキングニューロンによるホップフィールドネットワークを用いた高速連想メモリ
佐々木寛弥,森江隆,岩田穆
電子情報通信学会 信学技報 55 - 60 2003.11
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A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture Reviewed
K. Korekado,T. Morie,O. Nomura,H. Ando,T. Nakano,M. Matsugu,A. Iwata
Knowledge-Based Intelligent Information and Engineering Systems (KES2003) 2 169 - 176 2003.09
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A Face/Object Recognition System Using FPGA Implementation of Coarse Region Segmentation Reviewed
T. Nakano,T. Morie,and A. Iwata
SICE Annual Conference 2003 1418 - 1423 2003.08
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Coarse Image Region Segmentation Using Resistive-fuse Networks Implemented in FPGA Reviewed
T. Nakano,H. Ando,H. Ishizu,T. Morie,A. Iwata
The 7th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2003) Proceedings IV 186 - 191 2003.07
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A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models Reviewed
T. Morie,T. Matsuura,M. Nagata,A. Iwata
IEEE Transactions on Nanotechnology 2 ( 3 ) 158 - 164 2003.04
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Pulse Modulation VLSI Implementation of Clustering Algorithm Based on Stochastic Association Model Reviewed
T. Morie,T. Matsuura,A. Iwata
Artificial Neural Networks and Neural Information Processing ICANN/ICONIP 2003 International Conference Supplementary Proceedings 434 - 437 2003.04
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大局的画像領域分割のためのデジタル方式抵抗ヒューズネットワークの設計とFPGAへの実装
中野鉄平,森江隆,安藤博士,石津任章,岩田穆
電子情報通信学会技術研究報告(ICD) 2003.03
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パルスタイミングに基づくスパイキングホップフィールドネットワークによる高速連想メモリ
佐々木寛弥,森江隆,伊井慎一郎,岩田穆
電子情報通信学会技術研究報告(NC) 2002.11
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A Cellular-Automaton-Type Image Extraction Algorithm and Its Implementation Using an FPGA Reviewed
T. Nakano,T. Morie,M. Nagata,A. Iwata
Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems 2 197 - 200 2002.10
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自律移動ロボット用のビジョンシステムと画素選択処理機能を有する並列マッチングプロセッサの開発
山本美子,武田幹雄,渡部悠紀,岩田穆,森江隆,渡邊睦
電子情報通信学会技術研究報告（DSP,ICD,IE） 2002.10
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画像処理IPとFPGA実装
石津任章,武田幹雄,馬場祥宏,佐野誠,藤原義也,原正純,森江隆,岩田穆
電子情報通信学会技術研究報告（DSP,ICD,IE） 2002.10
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An Image Region Extraction LSI Based on a Merged/Mixed-Signal Nonlinear Oscillator Network Circuit Reviewed
H. Ando,T. Morie,M. Nagata,A. Iwata
28th European Solid-State Circuits Conference 703 - 706 2002.09
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適応型CMOSイメージセンサ
今村俊文,山本美子,岩田穆,石津任章,森江 隆
電子情報通信学会技術研究報告(ICD) 2002.09
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An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing Reviewed
K. Katayama,M. Nagata,T. Morie,A. Iwata
IEICE Transactions on Electronics E85-C ( 8 ) 1596 - 1603 2002.08
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A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models Reviewed
T. Morie,T. Matsuura,M. Nagata,A. Iwata
2002 IEEE Silicon Nanoelectronics Workshop 53 - 54 2002.06
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A Multi-Nano-Dot Circuit and Structure Using Thermal-Noise Assisted Tunneling for Stochastic Associative Processing Reviewed
T. Morie,T. Matsuura,M. Nagata,A. Iwata
Journal of Nanoscience and Nanotechnology 2 ( 3 ) 343 - 349 2002.06
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Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits Reviewed
M. Nagata,T. Morie,A. Iwata
IEEE 2002 Custom Integrated Circuit Conference 501 - 504 2002.05
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Image Segmentation/Extraction Using Nonlinear Cellular Networks and their VLSI Implementation Using Pulse-Modulation Techniques Reviewed
IEICE Trans. Fundamentals E85-A ( 2 ) 381 - 388 2002.04
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An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures Reviewed
T. Morie,T. Matsuura,M. Nagata,and A. Iwata
Advances in Neural Information Processing Systems 14,MIT Press 1115 - 1122 2002.04
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Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models Reviewed
M. Nagata,Y. Murasaka,Y. Nishimori,T. Morie,and A. Iwata
Proc. 7th Asia and South Pacific Design Automation Conference 71 - 76 2002.04