研究者詳細 - 田向　権

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85109018904&origin=inward

An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing 査読有り

Kawashima I., Katori Y., Morie T., Tamukoh H.

2021 International Conference on Field-Programmable Technology, ICFPT 2021 2021年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In our work, a new area-efficient multiply-accumulation scheme for time-domain neural processing named differential multiply-accumulation is proposed. Our new scheme reduces hardware resources utilization of multiply-accumulation with suppressing the increasing computational time resulting from the time-multiplexing. As a result, 2,048 neurons of fully connected CBM and RC-CBM were synthesized for a single field-programmable gate array (FPGA).

DOI： 10.1109/ICFPT52863.2021.9609809

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85123208884&origin=inward

Cycle-Generative Adversarial Network for Generating a Pseudo Realistic Food Dataset Using RGB and Depth Images 査読有り

aama Obada Al, Yoshimoto Yuma, Tamukoh Hakaru

Journal of Advances in Artificial Life Robotics ( 株式会社 ALife Robotics ) 2 ( 3 ) 128 - 133 2021年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

Constructing a food dataset is time and effort consuming due to the requirement for covering the feature variations of food samples. Additionally, a large dataset is needed for training neural networks. Generative adversarial networks (GANs) are a recently developed technique to learn deep representations without extensively annotated training data. They can be used in several applications, including generating food datasets. This paper advocates the use of Cycle-GAN to generate a large pseudo-realistic food dataset based on a large number of simulated images and a small number of real images in comparison to traditional techniques. A single depth camera in three different angles and a turntable are arranged to capture real RGB-D images of food samples. 3D modeling software is used to generate simulated images using the same configuration of captured real images. Results showed that Cycle-GAN realistic style transfer on simulated food objects is achievable, and that it can be an efficient tool to minimize real image capturing efforts.

DOI： 10.57417/jaalr.2.3_128

その他リンク： https://kyutech.repo.nii.ac.jp/records/2001340

深層ニューラルネットワークを用いた領域推定と部分テンプレートマッチングによる道路標示検出システム査読有り

三井悠也, 宮崎椋瑚, 吉元裕真, 石田裕太郎, 伊藤太久磨, 通山恭一, 田向権

知能と情報 ( 日本知能情報ファジィ学会 ) 33 ( 1 ) 566 - 571 2021年01月

担当区分：最終著者記述言語：日本語掲載種別：研究論文（学術雑誌）

<p>本研究では，自動運転技術における自車位置推定のために，You Only Look Once（YOLO）を処理に組み込むことで道路標示検出システムの性能向上を行う．従来手法では，輝度値に基づくテンプレートマッチングで道路標示を検出する．しかし，この手法では日光による白飛びや標示の掠れにより検出できないものが存在する．これに対し，提案手法ではYOLOで道路標示の存在する領域を探索し，テンプレートマッチングの適用範囲を制限する．これにより，誤検出の発生を抑制でき，テンプレートマッチングの検出閾値を下げ，これまで未検出であった道路標示の数を削減できる．また，テンプレートマッチングの探索領域も制限され，処理速度も向上できる．実験の結果，提案手法は誤検出数は0のまま，従来手法よりも未検出数を低減できた．また，従来手法と比較してシステムのAccuracyは0.013，処理速度は4.6 FPS上がった．</p>

DOI： 10.3156/jsoft.33.1_566

CiNii Article

その他リンク： https://ci.nii.ac.jp/naid/130007986500

A hardware-oriented algorithm of GMM-MRCoHOG for high-performance human detection by an FPGA 査読有り

Nagamine Y., Yoshihiro K., Shibata M., Yamada H., Enokida S., Tamukoh H.

Proceedings of SPIE - The International Society for Optical Engineering 11766 2021年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this study, we propose a hardware-oriented Gaussian mixture model - multiresolution co-occurrence histograms of oriented gradients (GMM-MRCoHOG) algorithm for efficient human detection by a field-programmable gate array (FPGA). GMM-MRCoHOG is a HOG-based human detection method in which the computation of angles is quantized to 36 directions and 2D Gaussian distribution computation causes a decrease in processing speed and an increase in hardware resource usage. We propose a hardware-oriented algorithm to solve these problems. First, we propose a rough angle computation method of comparison with a tangent table. Second, we propose a bit-shifting-based Gaussian distribution computation method. Experimental results show that the proposed hardware-oriented algorithm does not significantly reduce the detection accuracy of GMM-MRCoHOG. High-level synthesis results of the FPGA implementation show that fast, low-resource processing is possible.

DOI： 10.1117/12.2591024

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85103287974&origin=inward

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach 査読有り

Yamaguchi M., Iwamoto G., Nishimura Y., Tamukoh H., Morie T.

IEEE Access 9 2644 - 2654 2021年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

DOI： 10.1109/ACCESS.2020.3047619

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85099097466&origin=inward

A dataset generation for object recognition and a tool for generating ROS2 FPGA node 査読有り

Amano H., Mori H., Mizutani A., Ono T., Yoshimoto Y., Ohkawa T., Tamukoh H.

2021 International Conference on Field-Programmable Technology, ICFPT 2021 2021年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper introduces our autonomous driving system equipped with recognition processing units from a camera image for hazard object / human-doll detection and drive lane detection. In particular, this paper focuses on a dataset generation method for neural networks and a generation tool 'FPGA Oriented Easy Synthesizer Tool (FOrEST)' for ROS2-FPGA nodes. The results show that mAP of a neural network trained by the generated dataset is 94%, and a overhead of ROS2-FPGA communication by the FOrEST is 2-3 ms.

DOI： 10.1109/ICFPT52863.2021.9609880

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85123206616&origin=inward

Hardware-Oriented Pigeon-Inspired Optimization Algorithm and its FPGA Implementation 査読有り

Tatsuya Hayashi, Kentaro Honda, and Hakaru Tamukoh

Proc. of Int. Workshop on Smart Info-Media Systems in Asia (SISA2020) 71 - 76 2020年12月

Object Recognition Using Tactile Information and Its Application to Service Robots 査読有り

Daiju Kanaoka, Yutaro Ishida, and Hakaru Tamukoh

Proc. of Int. Workshop on Smart Info-Media Systems in Asia (SISA2020) 101 - 104 2020年12月

Multi-sampling Classifiers for the Cooking Activity Recognition Challenge 査読有り国際誌

Ninnart Fuengfusin, Hakaru Tamukoh

Human Activity Recognition Challenge. Smart Innovation, Systems and Technologies 199 2020年11月

Design and Implementation of Pulse-Coupled Phase Oscillators on a Field-Programmable Gate Array for Reservoir Computing 査読有り国際誌

Pramanta D., Tamukoh H.

Communications in Computer and Information Science 1333 333 - 341 2020年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2020, Springer Nature Switzerland AG. Reservoir computing (RC) has been viewed as a model of a neurological system. The RC framework constructs a recurrent neural network, which mimics parts of the brain, to solve temporal problems. To construct a neural network inside a reservoir, we adopt the pulse-coupled phase oscillator (PCPO) with neighbor topology connections on a field-programmable gate array (FPGA). Neural spikes for the PCPO are generated by the Winfree model. The low resource consumption of the proposed model in time-series generation tasks was confirmed in an evaluation study. We also demonstrate that on the FPGA, we can expand a 3 $$\times $$ 3 PCPO into a 10 $$\times $$ 10 PCPO, generate spike behavior, and predict the target signal with a maximum frequency of 418.796 MHz.

DOI： 10.1007/978-3-030-63823-8_39

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85097087623&origin=inward

FPGA Implementation and Verification of Reservoir Computing Based on Pseudo-Billiard Dynamics in Hypercube 査読有り国際誌

Daichi Yamamoto, Ichiro Kawashima, Hakaru Tamukoh, Takashi Morie, and Yuichi Katori

2020 International Symposium on Nonlinear Theory and Its Applications (NOLTA2020) 264 - 264 2020年11月

Performance Evaluation of Reservoir Computing Using Pseudo-billiard Dynamics in Hypercube 査読有り国際誌

Daichi Kamimura, Yuichi Katori, Hakaru Tamukoh, and Takashi Morie

2020 International Symposium on Nonlinear Theory and Its Applications (NOLTA2020) 135 - 135 2020年11月

A Reservoir Computing System Using a CMOS Chaotic Boltzmann Machine Chip Controlled by SoC FPGA 査読有り国際誌

Yuta Nishimura, Masatoshi Yamaguchi, Daichi Kamimura, Hakaru Tamukoh, and Takashi Morie

2020 International Symposium on Nonlinear Theory and Its Applications (NOLTA2020) 137 - 137 2020年11月

A Brain-inspired Artificial Intelligence Model of Hippocampus, Amygdala, and Prefrontal Cortex on Home Service Robots 査読有り国際誌

Yuichiro Tanaka, Hakaru Tamukoh, Katsumi Tateno, Yuichi Katori, and Takashi Morie

2020 International Symposium on Nonlinear Theory and Its Applications (NOLTA2020) 138 - 141 2020年11月

A Reservoir Based Q-learning Model for Autonomous Mobile Robots 査読有り国際誌

Masafumi Inada, Yuichiro Tanaka, Hakaru Tamukoh, Katsumi Tateno, Takashi Morie, and Yuichi Katori

2020 International Symposium on Nonlinear Theory and Its Applications (NOLTA2020) 213 - 216 2020年11月

Performance Evaluation of Reservoir Computing Using Pseudo-Billiard Dynamics in Hypercube 査読有り

Kamimura Daichi, Katori Yuichi, Tamukoh Hakaru, Morie Takashi

IEICE Proceeding Series ( The Institute of Electronics, Information and Communication Engineers ) 74 135 - 135 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

We proposed reservoir models using chaotic Boltzmann machines (CBMs) based on pseudo-billiard dynamics in hypercube. In order to utilize CBMs as a reservoir, we must control the chaotic behavior and satisfy the echo state property. We added an external reference clock signal to control the CBM. In this paper, we demonstrate the effect of an external reference clock signal and show that our model works as a reservoir by using NARMA task.

DOI： 10.34385/proc.74.a4l-c-1

その他リンク： https://kyutech.repo.nii.ac.jp/records/2001359

FPGA Implementation and Verification of Reservoir Computing Based on Pseudo-Billiard Dynamics in Hypercube 査読有り

Yamamoto Daichi, Kawashima Ichiro, Tamukoh Hakaru, Morie Takashi, Katori Yuichi

IEICE Proceeding Series ( The Institute of Electronics, Information and Communication Engineers ) 74 264 - 264 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Reservoir computing (RC) is a framework that constructs recurrent neural networks that can be utilized for generation, prediction, and discrimination of complex time-series. The recurrent connection on the RC is sparse and fixed, and thus, the computational cost of learning is small. The pseudo-billiard dynamics in a hypercube is known to be applicable for various types of computation. This hypercube based computing is very efficient for hardware implementation. In this research, we implement the hypercube based RC model in a digital circuit with hardware-oriented algorithms and verify its performance and effectiveness as a new artificial intelligence platform.

DOI： 10.34385/proc.74.b4l-b-4

その他リンク： https://kyutech.repo.nii.ac.jp/records/2001342

A Brain-Inspired Artificial Intelligence Model of Hippocampus, Amygdala, and Prefrontal Cortex on Home Service Robots 査読有り

Tanaka Yuichiro, Tamukoh Hakaru, Tateno Katsumi, Katori Yuichi, Morie Takashi

IEICE Proceeding Series ( The Institute of Electronics, Information and Communication Engineers ) 74 138 - 141 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

We propose a brain-inspired artificial intelligence model that acquires local knowledge from a small number of human-robot interactions, and uses this knowledge for future prediction. We focus on areas of the brain: the hippocampus, the amygdala, and the prefrontal cortex, thereby providing an internal representation of place and time, a value judgment, and a prediction. By integrating these functions, our model achieves local knowledge acquisition and future prediction. The proposed model is evaluated in a task for home service robots. In the experiment, the model learns local time-series events from a small number of interactions, and predicts the future events.

DOI： 10.34385/proc.74.a4l-c-4

その他リンク： https://kyutech.repo.nii.ac.jp/records/2001270

A Reservoir Computing System Using a CMOS Chaotic Boltzmann Machine Chip Controlled by SoC FPGA 査読有り

Nishimura Yuta, Yamaguchi Masatoshi, Kamimura Daichi, Tamukoh Hakaru, Morie Takashi

IEICE Proceeding Series ( The Institute of Electronics, Information and Communication Engineers ) 74 137 - 137 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Reservoir computing (RC) has received increasing attention as a computational framework for recurrent neural networks. As an implementation of reservoir, using a chaotic Boltzmann machine (CBM) was proposed, and we prototyped a CMOS CBM LSI chip controlled by an external reference clock (CBM-crc LSI) for working as a reservoir. We have developed a system using a System-on-Chip Field programmable gate array (SoC FPGA). In this paper, we propose a reservoir system that consists of a CBM-crc LSI controlled by an SoC FPGA and show the results of the system operations.

DOI： 10.34385/proc.74.a4l-c-3