研究者詳細 - 田向　権

その他リンク： https://ci.nii.ac.jp/naid/130007551490

競技会活動を通じたホームサービスロボットの研究開発査読有り

吉元裕真, 岩元剛毅, 橋本康平, 森江隆, 田向権, 堀三晟, 石田裕太郎, 木山雄太, 黒田裕貴, 田中悠一朗, 久野昌隆, 藤田啓斗, 新谷嘉也

ロボティクス・メカトロニクス講演会講演概要集 ( 一般社団法人日本機械学会 ) 2018 ( 0 ) 2P2 - E02 2018年01月

記述言語：日本語掲載種別：研究論文（学術雑誌）

In real world applications of home service robots, they are required to be able to perform housekeeping or other tasks. "RoboCup@Home" is a competition for benchmarking home service robots. It includes tests to service robots for real world implementation. These tests require the combination of intelligent functions such as object detection and voice recognition. We have developed a home service robot "Exi@" and evaluated its performance by participating in RoboCup@Home. This paper describes real world implementation of robots and RoboCup@Home. The functions embedded in Exi@ and a task "Restaurant" are also explained.

DOI： 10.1299/jsmermd.2018.2P2-E02

その他リンク： https://ci.nii.ac.jp/naid/130007552042

ホームサービスロボットにおける命令文中の単語意味ベクトルに注目した最適行動識別査読有り

石田裕太郎, 能勢啓輔, 安藤充宏, 田向権

ロボティクス・メカトロニクス講演会講演概要集 ( 一般社団法人日本機械学会 ) 2018 ( 0 ) 2P1 - B18 2018年01月

担当区分：最終著者記述言語：日本語掲載種別：研究論文（学術雑誌）

Service robots must assemble and execute its own action based on user's voice instructions. Additionally, in order to assist human daily life, the service robots execute not a single action like an industrial robot but plurality of actions must be combined according to the situation. As the number of actions the robots can perform increases, phrase of the voice instructions increases to an enormous pattern. Therefore, the robots must understand the instructions by natural language processing. In this paper, we focus on general purpose service robot (GPSR) task of RoboCup@Home, which is a competition for performance of the service robots, and identify behavior of the robots from natural language by using word vectorization and machine learning.

DOI： 10.1299/jsmermd.2018.2P1-B18

その他リンク： https://ci.nii.ac.jp/naid/130007551866

A pulse-width-modulation mode CMOS integrated circuit implementation of threshold-coupled map 査読有り

Uenohara Seiji, Morie Takashi, Tamukoh Hakaru, Aihara Kazuyuki

Nonlinear Theory and Its Applications, IEICE ( 一般社団法人電子情報通信学会 ) 9 ( 2 ) 268 - 280 2018年01月

記述言語：英語掲載種別：研究論文（学術雑誌）

We propose a coupled-map-lattice complementary-metal-oxide-semiconductor very-large-scale-integration (CMOS VLSI) circuit based on the threshold-coupled map (TCM) that has been proposed previously as a unidirectional connected network model exhibiting different spatiotemporal patterns according to its underlying nonlinear map and update scheme. We introduce mutual connections and arbitrarily valued connection weights into the TCM to realize cellular automata. In this study, we design, fabricate, and evaluate a CMOS integrated circuit with which to implement this extended TCM (ETCM). The ETCM is a universal Turing machine as confirmed in circuit experiments using the fabricated circuit, which can achieve Rule110 of a one-dimensional cellular automaton.

DOI： 10.1587/nolta.9.268

その他リンク： https://ci.nii.ac.jp/naid/130006602774

Robust Boat Detection System using HSV Adaptive Background Modeling and Multiresolution Co-occurrence Histograms of Oriented Gradients, 査読有り

Daisuke Shuto, Kouji Okumura, Naoki Matsubara, Shaoning Pang, Hakaru Tamukoh and Abdolhossein Sarrafzadeh

Proc. of Int. Workshop on Smart Info-Media Systems in Asia (SISA2017) 128 - 132 2017年09月

カーロボ連携大学院での自動車・ロボットの知能化高度化に向けた専門人材育成査読有り

森江隆, 石井和男, 我妻広明, 田向権, 榎田修一, 齊藤剛史, 松永良一, 松波勲, 大貝晴俊,

工学教育 65 ( 4 ) 51 - 56 2017年08月

A CMOS chaotic Boltzmann machine circuit and three-neuron network operation 査読有り

Yamaguchi M., Tamukoh H., Suzuki H., Morie T.

Proceedings of the International Joint Conference on Neural Networks 2017-May 1218 - 1224 2017年06月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2017 IEEE. This paper proposes CMOS VLSI implementation of a chaotic Boltzmann machine (CBM) model, which uses analog nonlinear dynamics instead of stochastic operation as in the original Boltzmann machine model. The CBM model is suitable for efficient VLSI implementation of Boltzmann machines because it requires no random number generator circuits, which consume a considerable footprint on a VLSI chip as well as considerable power. We describe the design results of CMOS circuits of neuron and synapse units. The neuron circuit uses subthreshold operation of MOSFETs to realize the exponential function used in the CBM model. We also provide measurement results of a fabricated CMOS chip for single-neuron unit circuit operation and demonstrate chaotic behavior in a three-neuron network.

DOI： 10.1109/IJCNN.2017.7965991

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85031020313&origin=inward

Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links 査読有り

Dinda Pramanta, Takashi Morie, Hakaru Tamukoh

Journal of Robotics, Networking and Artificial Life 4 ( 1 ) 91 - 96 2017年06月

Implementation of multi-FPGA Communication using Pulse-Coupled Phase Oscillators 査読有り

Dinda Pramanta, Takashi Morie, Hakaru Tamukoh

Proc. of the 2017 International Conference On Artificial Life And Robotics 17 2017年01月

Multi-Valued Quantization Neural Networks toward Hardware Implementation 査読有り

Yoshiya Aratani, Yeoh Yoeng Jye, Akihiro Suzuki, Daisuke Shuto, Takashi Morie, Hakaru Tamukoh

Proc. of the 2017 International Conference On Artificial Life And Robotics 58 2017年01月

Implementation of Multi-FPGA Communication using Pulse-Coupled Phase Oscillators 査読有り

Pramanta Dinda, Morie Takashi, Tamukoh Hakaru

人工生命とロボットに関する国際会議予稿集 ( 株式会社ALife Robotics ) 22 128 - 131 2017年01月

担当区分：最終著者記述言語：英語掲載種別：研究論文（学術雑誌）

This paper proposes an implementation of multi-Field Programmable Gate Array (FPGA) communication using pulse-coupled phase oscillators. At first, we construct a digital phase oscillator circuit with adjustable in-phase parameters. While performing the synchronization task, the oscillators are connected into the first input and first output (FIFO) interface. The communication in-between of FPGAs will occur by enabling the following inputs and outputs on the FIFO through the Gigabit Transceiver (GTX) clock domain. Pulse-coupled phase oscillators of Winfree's model are utilized as a spike generator and we expect the ideal of model circuit will synchronize. We employ two FPGA boards of Virtex6 ML605 and implement four oscillators on a hardware level. Experimental results show that first spike synchronizing over two FPGAs takes 12.47 μsec with data bit speed stream 3.2Gbps.

DOI： 10.5954/icarob.2017.os9-1

Hardware implementation of deep self-organizing map networks 査読有り

Tanaka Y., Tamukoh H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10613 LNCS 439 - 441 2017年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2017. We aim to develop a recognition system of high accuracy and low power consumption by designing a digital circuit for deep neural networks (DNNs), and by implementing the circuit on field programmable gate arrays (FPGAs). DNNs include numerous multiply operations, whereas FPGAs include a limited number of multipliers. We aim to reduce the number of multiply operations generated by the algorithms within DNNs. Deep self-organizing map networks (DSNs) [1] are DNNs comprising self-organizing maps (SOMs) [2] as shown in Fig. 1. A hardware-oriented algorithm for SOMs has been proposed herein [3]. The algorithm represents SOMs by replacing multiply operations with bitshift operations. DSNs that include only a few multiply operations can then be represented by employing the algorithm. In this paper, we propose a hardware-oriented algorithm and a hardware architecture for DSNs. The hardware-oriented algorithm reduces multiply operations and exponential functions in a computation of SOM Module as shown in Fig. 1. In addition, we confirm that the algorithm does not worsen performance of DSN by a software simulation. Figure 2 shows error rates of DSN during learning MNIST Dataset [4]. The performance of the proposed algorithm achieve comparable results to the conventional algorithm. We also describe a DSN comprising three layers by Verilog-HDL as shown in Fig. 1, and implement it on a Xilinx Vertex-6 XC6VLX240T FPGA. Experimental results showed that the proposed DSN circuit estimates a label of an input image in 2 µs while the software implemented using an Intel Core i5-3470 (3.20 GHz) CPU estimates it in about 1 ms. Thus the hardware is 500 times faster than the software. Its logic utilization is shown in Table 1.

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85034254406&origin=inward

Evaluation of hardware oriented MRCoHOG using logic simulation 査読有り

Yamasaki Y., Ooe S., Suzuki A., Kuno K., Yamada H., Enokida S., Tamukoh H.

VISIGRAPP 2017 - Proceedings of the 12th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications 5 341 - 345 2017年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Copyright © 2017 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved. Human detection require high speed and high accuracy processing. One of the high performance techniques of the detection is multi-resolution co-occurrence histogram of oriented gradients (MRCoHOG). Since the calculation of co-occurrence requires a huge amount of processing resources, it is difficult to realize real-time human detection with MRCoHOG. Accordingly, hardware implementation is considered to be effective. In this paper, a hardware oriented MRCoHOG is proposed. In the proposed method, we simplify complicated calculation such as multiplications and square root operation for efficient hardware implementation. Experimental results show that the proposed method achieves better human detection rate than the ordinary method. Moreover, MRCoHOG is implemented in a digital circuit with the proposed method. According to logic simulation of the proposed circuit, the processing speed of the hardware implementation is 466 times higher than the software implementation.

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85047884344&origin=inward

An implementation of a spiking neural network using digital spiking silicon neuron model on a SIMD processor 査読有り

Hori S., Zapata M., Madrenas J., Morie T., Tamukoh H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10613 LNCS 437 - 438 2017年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2017. We implement a digital spiking silicon neuron (DSSN) [1] in a single instruction multiple data (SIMD) processor. The SIMD processor is a scalable, reconfigurable, and real-time spiking neural network emulator based on field programmable gate arrays [2]. We implement the DSSN model in the SIMD processor for the first time. The behavior of the membrane potential of one neuron based on the DSSN model is shown in Fig. 1. The operation results of the SIMD processor with 16-bit fixed-point operation are compared with software simulation results based on 64-bit floating-point operation. From the results, it is concluded that the SIMD processor successfully emulated the behavior of the membrane potential. In addition, a full-connection network consisting of 100 neurons is simulated in a software using fixed-point binary numbers to evaluate the bit width for the SIMD processor. In this experiment, the network stores two patterns selected from [1]. In the recall phase, the first pattern with noise is given to this network to recall the pattern. Experimental results show that the network with 16-bit fixed-point numbers, each of which includes a 12-bit fraction, a 3-bit integer, and a 1-bit sign, successfully recalled the input pattern as shown in Fig. 2. Here, Muis a recall rate [1]. From this result, a large DSSN network simulation on the SIMD processor is promising.

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85034266960&origin=inward

A hardware-oriented dropout algorithm for efficient FPGA implementation 査読有り

Yeoh Y., Morie T., Tamukoh H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10639 LNCS 821 - 829 2017年01月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© Springer International Publishing AG 2017. This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

DOI： 10.1007/978-3-319-70136-3_87

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85035101597&origin=inward

オントロジーに基づく自動運転向け意思決定システムの推論速度評価査読有り

橋本康平, 石田裕太郎, 三好竜平, 市瀬龍太郎, 我妻広明, 田向権

日本知能情報ファジィ学会ファジィシステムシンポジウム講演論文集 ( 日本知能情報ファジィ学会 ) 33 ( 0 ) 681 - 684 2017年01月

カーロボ連携大学院での自動車・ロボットの知能化高度化に向けた専門人材育成査読有り

森江隆, 石井和男, 我妻広明, 田向権, 榎田修一, 齊藤剛史, 松永良一, 松波勲, 大貝晴俊

工学教育 ( 公益社団法人日本工学教育協会 ) 65 ( 4 ) 4_51 - 4_56 2017年01月

記述言語：日本語掲載種別：研究論文（学術雑誌）

The Joint Graduate School Intelligent Car and Robotics Course, called “Car-Robo Joint Graduate School” is an educational program that started in 2012 mainly at The Kitakyushu Science and Research Park (KSRP). Graduate schools of engineering in Kyushu Institute of Technology, the University of Kitakyushu, and Waseda University at KSRP participate in this program. The purpose of this program is to foster highly skilled personnel in technical fields on intelligent car and robot technology. They will gain practical ability as leaders, mastering their special fields, understanding the peripheral technologies, and leading research and development teams. The special-feature program of this course is seven comprehensive practicums as team learning. Internship students of national colleges of technology and other universities as well as master and PhD course students of these graduate schools participate in the practicums.

DOI： 10.4307/jsee.65.4_51

その他リンク： https://ci.nii.ac.jp/naid/130005966874

Depth-Based Visual Servoing Using Low-Accurate Arm 査読有り

Hofer L., Tanaka M., Tamukoh H., Nassiraei A., Morie T.

Proceedings - 2016 Joint 8th International Conference on Soft Computing and Intelligent Systems and 2016 17th International Symposium on Advanced Intelligent Systems, SCIS-ISIS 2016 524 - 531 2016年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

© 2016 IEEE. This paper proposes a visual-servoing method dedicated to grasping of daily-life objects. In order to obtain an affordable solution, we use a low-accurate robotic arm. Our method corrects errors by using an RGB-D sensor. It is based on SURF invariant features which allows us to perform object recognition at a high frame rate. We define regions of interest based on depth segmentation, and we use them to speed-up the recognition and to improve reliability. The system has been tested on a real-world scenario. In spite of the lack of accuracy of all the components and the uncontrolled environment, it grasps objects successfully on more than 95% of the trials.

DOI： 10.1109/SCIS-ISIS.2016.0116

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85010441822&origin=inward

Lightness modification method considering craik-o'brien effect for protanopia and deuteranopia 査読有り

Bao S., Tanaka G., Tamukoh H., Suetake N.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E99A ( 11 ) 2008 - 2011 2016年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Copyright © 2016 The Institute of Electronics, Information and Communication Engineers. Protanopes and deuteranopes are difficult to distinguish some color pairs. In this letter, a new lightness modification method which considers the Craik-O'Brien effect is proposed. The lightness modification is performed at parts which are difficult to distinguish in the protanopia or deuteranopia. Experiments show the validity of the proposed method.

DOI： 10.1587/transfun.E99.A.2008