研究者詳細 - 田向　権

論文 - 田向　権

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Hardware/Software Complex System and Its Application 招待有り

Hakaru Tamukoh

Proc. of the 13th Kyutech-Postech Joint Workshop on Neuroinformatics 4 - 6 2013年08月

Fast image-enlargement algorithm for the augmentation of the high-frequency component by employing a hierarchical predefined codebook 査読有り

Tamukoh H., Kawano H., Suetake N., Cha B., Aso T.

International Journal of Innovative Computing, Information and Control 9 ( 2 ) 903 - 914 2013年05月

記述言語：英語掲載種別：研究論文（学術雑誌）

High-quality image enlargement is achieved by the augmentation of the high-frequency components that deteriorate as a result of image enlargement. A codebook-based method, which utilizes the relationship of the low- and high-frequency image components, is a proven method of high-quality image enlargement. However, this method requires a significant calculation time to be employed for a codebook search process, and thus is not suitable for real-time processing. In this paper, we propose a fast image-enlargement algorithm that includes a hierarchical predefined codebook and a fast edge-patch detection rule. A hierarchical codebook search reduces the number of comparisons that need to be made in comparison with a conventional full codebook search. In addition, applying the augmentation of the high-frequency components to only the edge patches detected under the proposed rule reduces the calculation time. The experimental results show that the calculation time of the proposed method is around 180 times faster than that of the fastest existing codebook-based method. The proposed method realizes high-quality image enlargement in terms of both objective and subjective evaluations in comparison with conventional methods. © 2013 ICIC International.

Kyutacar

Scopus

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A TCP/IP Hardware Stack Directly Connectable to WEB Application Circuit 査読有り

Kotoko Fujita, Nadav Bergstein, Hakaru Tamukoh and Masatoshi Sekine

Proc. of IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI) 2013年04月

画像音声認識・音声合成・並列演算・画像通信における論理回路による実装例

関根優年, 田向権

電子情報通信学会誌 ( 電子情報通信学会 ) 96 ( 2 ) 2013年02月

Fast Image-Enlargement Algorithm for the Augmentation of the High-Frequency Component by Employing a Hierarchical Predefined Codebook 査読有り

Hakaru Tamukoh, Hideaki Kawano, Noriaki Suetake, Byungki Cha, and Takashi Aso

International Journal of innovative Computing Information and Control 9 ( 2 ) 903 - 914 2013年02月

A Modified Prticle Swarm Optimization Considering Component Combined with Personal Best Positions 査読有り

Ryosuke Kubota and Hakaru Tamukoh

Proc. of 7th WSEAS International Conference on Circuits, Systems, Signal and Telecommunications (CSST '13) 2013年01月

A Data Embedded Reduction Image Generation Method for High-Quality Image Enlargement 査読有り

Hakaru Tamukoh, Hideaki Kawano, Noriaki Suetake, Masatoshi Sekine, Byungki Cha, and Takashi Aso

Proc. of 7th WSEAS International Conference on Circuits, Systems, Signal and Telecommunications (CSST '13) 2013年01月

Hardware/Software Complex System Model for Brain Process by Configurable Circuits 査読有り

Masatoshi Sekine, Hakaru Tamukoh, and Jiang Li

International Journal on Computing 3 ( 1 ) 1 - 7 2013年01月

Brain Process: Hardware/Software Complex System Using Logic Circuits in FPGA Array Named Vocalise 査読有り

Masatoshi Sekine, Hakaru Tamukoh, J. Li, K. Manabe, T. Suzuki, K. Okamot, B. Ogasawara, R. Uegaki, K. Fujita, Y. Atsumari

Journal of Procedia Engineering 50 253 - 264 2012年10月

Live demonstration: Internet Booster a novel WEB application platform accelerated by reconfigurable virtual hardware circuits 査読有り

Tamukoh H., Bergstein N., Fujita K., Sekine M.

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems 2012年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This live demonstration presents an Internet Booster (IB) which is a novel WEB application platform accelerated by virtual hardware circuits. Akey-idea of IB is obtaining relevant WEB applications virtual hardware circuit through the Internet. The downloaded virtual hardware circuit is dynamically reconfigured into an FPGA and cooperates with software and network to accelerate WEB application. In order to realize the concept of IB, we develop a hwModule VC FPGA Cardbus board and a networked hw/sw complex system to access virtual hardware circiuts via the Internet. Furthermore, we also develop a virtual hardware video codec and a TCP/IP hardware stack to construct a demonstration system. In the live demonstration, we show a WEB streaming application accelerated by IB on the local area network environment. The demonstration system achieves full-color VGA size (24 bits RGB, 640 × 480 pixels) video streaming with around 20 frames per second. © 2012 IEEE.

DOI： 10.1109/ISCAS.2012.6272135

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=84866605736&origin=inward

A look-Up Table-based Lightness Modification for Increasing Visibility of Dichromats 査読有り

Hakaru Tamukoh, Masatoshi Sekine, Go Tanaka and Noriaki Suetake

Proc. of Int. Workshop on Smart Info-Media Systems in Asia (SISA2012) 39 - 42 2012年09月

Hardware Accelerated WEB Platform based on FPGA Array Server and Mobile FPGA Card 査読有り

Jiang Li, Hakaru Tamukoh and Masatoshi Sekine

Proc. of 3rd International Conference on Internet Technology and Applications (iTAP2012) 4 in CD-ROM 2012年08月

Live Demonstration: ``Internet Booster" A Novel WEB Application Platform Accelerated by Reconfigurable Virtual Hardware Circuits 査読有り

Hakaru Tamukoh, Nadav Bergstein, Kotoko Fujita and Masatoshi Sekine

Proc. of IEEE International Symposium on Circuit and Systems (ISCAS2012) 76 2012年05月

2D/3D FPGA Array for Brain Process and Numerical Computation 査読有り

Jiang Li, Kenichi Takahashi, Hakaru Tamukoh and Masatoshi Sekine

Proc. of 8th International Conference on Natural Computation (ICNC'12) 16 - 19 2012年05月

Distributed Computing Circuits in Scalable 2D/3D FPGA Array for 2D/3D Poisson Equation Problem 査読有り

Jiang Li, Kenichi Takahashi, Hakaru Tamukoh and Masatoshi Sekine

Proc. of IEEE Symposium on Low-Power and High-Speed Chips COOL Chips XV 2 in CD-ROM 2012年04月

An FPGA Implementation of Hierarchal Predefined Codebook based Image Enlargement 査読有り

Hakaru Tamukoh, Hideaki Kawano, Noriaki Suetake, Masatoshi Sekine, Byungki Cha, and Takashi Aso

Proc. of Int. Workshop on Advanced Image Technology 622 - 625 2012年01月

High-Performance WEB Application Accelerated by Networked hw/sw Complex System and Virtual Hardware Circuit 招待有り査読有り

Hakaru Tamukoh, Masatoshi Sekine

Int. Symposium on Semiconductor Manufacturing Intelligence 6 in CD-ROM 2012年01月

Rough winner-take-all for hardware oriented vector quantization algorithm 査読有り

Tamukoh H., Horio K., Yamakawa T., Sekine M.

IEICE Electronics Express 8 ( 11 ) 773 - 779 2011年06月

担当区分：筆頭著者記述言語：英語掲載種別：研究論文（学術雑誌）

In this paper, we propose a hardware oriented vector quantization algorithm employing rough-winner-take-all neural network. The proposed algorithm is almost same as K-means clustering which is the simplest vector quantization. The only different point is that the proposed method employs rough-winner-take-all as the substitute of ordinary winner-take-all. In a rough-winner-take-all strategy, the winner is roughly selected in the early learning stage and is strictly assigned in the later stage. The simulation results show that the quantization performance of the proposed method is nearly equal to Neural Gas which is an excellent vector quantization. Besides, the proposed method can be realized as an extra mode of existing K-means or Self- Organizing Map hardware by changing its winner-take-all controlling. © IEICE 2011.

DOI： 10.1587/elex.8.773

Kyutacar

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79958822511&origin=inward

Rough-winner-take-all for Hardware Oriented Vector Quantization Alogrithm 査読有り

Hakaru Tamukoh, Keiichi Horio, Takeshi Yamakawa and Masatoshi Sekine

IEICE Electronics Express 8 ( 11 ) 773 - 779 2011年06月

Internet booster: A networked hw/sw complex system and its application to hi-performance web application 査読有り

Tamukoh H., Hanai K., Kurogi R., Matsushita S., Watanabe M., Kobayashi Y., Sekine M.

2010 World Automation Congress, WAC 2010 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

An internet booster (IB) based on a networked hw/sw complex system is presented. The key-idea of IB is obtaining relevant WEB applications virtual hardware circuit through internet; just as same as downloading general WEB applications specific software from the server. The downloaded virtual hardware circuit is realized into an FPGA and cooperates with server's application which is also constructed with FPGA. In order to realize IB, the networked hw/sw complex system is proposed which provides remote FPGA reconfiguration and handshake mechanism between FPGAs over the internet. In this paper, we implement WEB application as IB; where the WEB application performs real time compression, transferring and extension of video. Experimental results show that we succeed in downloading virtual hardware circuit, dynamic reconfiguration and remote operation over the internet. Besides, we also achieved full-color VGA size (24bits RGB, 640x480 pixels) video streaming with 20 frames per second using a wavelet transfer based virtual video codec. The result leads that the proposed networked hw/sw complex system and IB can provide a new WEB application program environment which features both the hispeed of hardware and the flexibility of software. © 2010 TSI Press.

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=78651462612&origin=inward

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