研究者詳細 - 大村　一郎

論文 - 大村　一郎

分割表示190 件中 21 - 40 件目／全件表示 >>

A testing method for evaluating shoot-through immunity of IGBTs in an inverter 査読有り国際誌

K. Hasegawa, S. Abe, M. Tsukuda, I. Omura, T. Ninomiya

Microelectronics Reliability 2021年11月

Determination of Abnormality of IGBT Images Using VGG16 査読有り国際誌

T. Ogawa, H. Lu, A. Watanabe, I. Omura and T. Kamiya

Proc. of The 21th International Conference on Control, Automation and Systems (ICCAS 2021) 2021年10月

Multipurpose Strategy for Energy Storage System Based on Capital Asset Pricing Model With Ensemble Approach 査読有り国際誌

Kazufumi Yuasa, Miki Ueshima, Tadatoshi Babasaki, Ichiro Omura

IEEE Access ( IEEE ) 9 106725 - 106733 2021年07月

Improved DICM with an IR camera for Imaging of Strain and Temperature in Cross Section of TO packages 査読有り国際誌

Yoshiki Masuda, Akihiko Watanabe, Ichiro Omura

Proc. of ISPSD 2021 2021年05月

Benchmarking of Digital Gate Driven IGBTs: New Eoff-Vsurge Trade-off Approach 査読有り国際誌

Kouji Harasaki, Masanori Tsukuda and Ichiro Omura

Proc. of ISPSD 2021 2021年05月

DUT Temperature Coefficient and Power Cycles to Failure 査読有り国際誌

Yuma Kawauchi, Kenji Akimoto, Akihiko Watanabe and Ichiro Omura

Proc. of ISPSD 2021 2021年05月

Altitude Dependent Failure Rate Calculation for High Power Semiconductor Devices in Aviation Electronics 査読有り国際誌

Srikanth Gollapudi and Ichiro Omura

Japanese Journal of Applied Physics 2021年04月

Study of parasitic oscillation of a multi-chip SiC MOSFET circuit based on a signal flow graph model by TCAD simulation 査読有り国際誌

Hiroshi Kono, Ichiro Omura

Solid-State Electronics ( Elsevier ) 177 2021年03月

Multipurpose strategy for energy storage system based on capital asset pricing model with ensemble approach 査読有り国際誌

Yuasa K., Ueshima M., Babasaki T., Omura I.

Yuasa K., Ueshima M., Babasaki T., Omura I. 2021年01月

3.3 kV back-gate-controlled IGBT (BC-IGBT) using manufacturable double-side process technology 査読有り国際誌

Saraya T., Itou K., Takakura T., Fukui M., Suzuki S., Takeuchi K., Tsukuda M., Satoh K., Matsudai T., Kakushima K., Hoshii T., Tsutsui K., Iwai H., Ogura A., Saito W., Nishizawa S., Omura I., Ohashi H., Hiramoto T.

Technical Digest - International Electron Devices Meeting, IEDM 2020年12月

Shoot-through protection for an inverter consisting of the next-generation IGBTs with gate impedance reduction 査読有り

Hasegawa K., Abe S., Tsukuda M., Omura I., Ninomiya T.

Microelectronics Reliability 114 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

Attention has been paid to the next-generation IGBT toward CMOS compatible wafer processes, which can be driven by a 5-V logic level due to its low threshold gate voltage. This low threshold voltage makes the so-called shoot-through fault severer. Even though the switching speed of the IGBT is intentionally reduced, the shoot-through fault can happen. This paper presents shoot-through protection for an inverter consisting of the next-generation IGBTs with gate impedance reduction. Theoretical analysis reveals the criterion of the gate impedance with taking parasitic parameters of the inverter into account.

DOI： 10.1016/j.microrel.2020.113765

Scopus

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Effect of cell size reduction on the threshold voltage of UMOSFETs 査読有り

Baba Y., Omura I.

Microelectronics Reliability 114 2020年11月

記述言語：英語掲載種別：研究論文（学術雑誌）

UMOSFET on-resistances have been dramatically improved in recent decades with the miniaturization of cell size by innovations in the fabrication process. However, with miniaturization, failure in the gate oxide, large deviations in the threshold voltage and reductions in avalanche capability have emerged as design problems for mass production. In particular, threshold voltage increase have appeared with the introduction of a trench source contact. The source contact trench and MOS gate trench are fabricated next to each other with a narrow silicon mesa region, and the voltage increase appear when the silicon mesa width becomes narrower than 80 nm. So far, it appears that the P+ layer dopant in the contact sidewall diffuses toward the gate oxide and the channel doping increases, which causes the increase in the threshold voltage Vth. We analyzed the distribution of Vth at the wafer level/shot level and found for the first time that the increase in Vth is caused by the punch-through effect from the channel depletion layer to the contact P+ layer, and thus, sidewall dopant diffusion will not affect the increase in Vth. We established an analytical model for the increase in Vth. Our model showed that for the field plate type UMOSFET with a shorter gate contact length, not only is there a increase in Vth, but also it is difficult to control Vth using the conventional channel implantation method.

DOI： 10.1016/j.microrel.2020.113747

Scopus

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Identification of normal and abnormal from ultrasound images of power devices using VGG16 査読有り

Ogawa T., Lu H., Watanabe A., Omura I., Kamiya T.

International Conference on Control, Automation and Systems 2020-October 415 - 418 2020年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Power devices are semiconductor devices that handle high voltages and large currents, which are used in electric vehicles, televisions, and trains. Therefore, high reliability and safety are required, and to ensure this, power cycle tests are performed to analyze the breakdown process. Conventional tests are often difficult to analyze due to the influence of sparks generated during the test. Therefore, new tests are being developed by adding ultrasound to conventional methods. The new technology is capable of continuously recording structural changes inside the device during testing, which is expected to make testing much easier than conventional testing. However, the new technology still has some challenges. The main problems are the lack of a method for analyzing large amounts of image data and the extraction of small changes in image features that are difficult to distinguish with the human eye, and the establishment of such a system is required. In this paper, we use deep learning for image classification of the obtained ultrasound images. We propose a new network model with the addition of Batch normalization and Global average pooling to VGG16, which is a pre-trained model. In the experiment, accuracy=98.29%, TPR=98.96% and FPR=7.43% classification accuracy was obtained.

DOI： 10.23919/ICCAS50221.2020.9268275

Scopus

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Altitude Dependent Failure Rate Calculation for High Power Semiconductor Devices in Aviation Electronics 査読有り国際誌

Srikanth Gollapudi, Ichiro Omura

International Conference on Solid State Devices and Materials (SSDM2020) 2020年09月

太陽光併設蓄電システムの自家消費型長期運用戦略に関する一検討査読有り

湯淺一史，植嶋美喜，馬場﨑忠利，大村一郎

電子情報通信学会論文誌 B ( 電子情報通信学会 ) J103-B ( 9 ) 382 - 390 2020年09月

Active Voltage Balancing for Series Connected IGBT System using Gate Delay Compensation 査読有り

Ravi Nath Tripathi, Masanori Tsukuda, Ichiro Omura

2019 International Conference on Solid State Devices and Materials 725 - 726 PS-4-02 2020年09月

V-I Curve Based Condition Monitoring System for Power Devices 査読有り

Tsukuda M., Guan L., Watanabe K., Yamaguchi H., Takao K., Omura I.

Proceedings of the International Symposium on Power Semiconductor Devices and ICs 2020-September 82 - 85 2020年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

According to gaining importance of power electronics systems in the society, reliability issues of power semiconductor devices are the constrains on availability of the system operations. Regular interval based maintenance for higher availability, on the other hand, increases operation cost since the lifetime of power devices have a large deviation with production lots or conditions which they are used. Condition based maintenance (CBM) of power semiconductor devices will be a promising solution for both the availability and cost of power electronics system maintenance. In this study, a high signal resolution condition monitoring system board has been demonstrated. The system monitors real time V-I curve for both switching device and diode with case temperature and the data is stored on board memory and can be monitored on-line. The board was mounted on the gate driver board being supplied power from the gate driver board and demonstrated on a commercial 60kVA inverter.

DOI： 10.1109/ISPSD46842.2020.9170059

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85090597949&origin=inward

13kV UHV-IGBT: Feasibility Study 査読有り

Ito A., Omura I.

Proceedings of the International Symposium on Power Semiconductor Devices and ICs 2020-September 50 - 53 2020年09月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Increasing the rated voltage of IGBTs is indispensable for realizing future energy transmission systems such as gigawatt-class UHVDC and high-power motor drives with reduced number of series connection or simplified circuit topology. The voltage of IGBTs, however, has stagnated for 20 years at 6.5kV because of several issues. In this paper, we investigated the feasibility of a 13kV ultra-high voltage IGBT with twice the breakdown voltage of conventional IGBTs using TCAD simulations. As a result, the use of a double gate structure proved to be practical under DC bus voltage of 6.6 kV and a switching frequency of 150 Hz.

DOI： 10.1109/ISPSD46842.2020.9170034

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85090549853&origin=inward

Dynamic Current Balancing of Parallel Connected IGBT Devices using PCB Sensors for Integration in Power Modules 査読有り国際誌

Ravi Nath Tripathi; Masanori Tsukuda; Ichiro Omura

11th International Conference on Integrated Power Electronics Systems (CIPS2020) ( VDE ) 2020年05月

Simultaneous Imaging of Strain and Temperature using Single IR Camera 査読有り国際誌

Yoshiki Masuda, Akihiko Watanabe and Ichiro Omura

11th International Conference on Integrated Power Electronics Systems (CIPS2020) ( VDE ) 2020年05月

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